Texas Instruments CD74HC195M, CD74HC195E, CD54HC195F3A Datasheet
Data sheet acquired from Harris Semiconductor
/
j
/
SCHS165
September 1997
CD74HC195
High Speed CMOS Logic
4-Bit Parallel Access Register
[ /Title
(CD74
HC195
)
Sub-
ect
(High
Speed
CMOS
Logic
4-Bit
Parallel
Access
Register)
Autho
Features
• Asynchronous Master Reset
K, (D) Inputs to First Stage
•J,
• Fully Synchronous Serial or Parallel Data Transfer
• Shift Right and Parallel Load Capability
• Complementary Output From Last Stage
• Buffered Inputs
• Typical f
C
= 15pF, TA = 25oC
L
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High NoiseImmunity: N
V
CC
= 50MHz at VCC = 5V,
MAX
= 5V
o
C to 125oC
= 30%, NIH= 30%of VCCat
IL
Description
The device is useful in a wide variety of shifting, counting
and storage applications. It performs serial, parallel, serial to
parallel, or parallel to serial data transfers at very high
speeds.
The two modes of operation, shift right (Q
load, are controlled by the state of the Parallel Enable (
input. Serial data enters the first flip-flop (Q
inputs when the
direction Q
transition. The J and K inputs provide the flexibility of the JKtype input for special applications and by tying the two pins
together, the simple D-type input for general applications.
The device appears as four common-clocked D flip-flops
when the
tion, data on the parallel inputs (D0-D3) is transferred to the
respective Q
be achieved by tying the Q
holding the
All parallel and serial data transfers are synchronous, occurring
after each Low to High clock transition. The CD74HC195 series
utilizes edge triggering; therefore, there is no restriction on the
activity of the J,
than set-up and hold time requirements. A Low on the
asynchronous Master Reset (
independent of any other input condition.
PE input is high, and is shifted one bit in the
0-Q1-Q2-Q3
PE input is Low. After the Low to High clock transi-
0-Q3
PE input low.
K, Pn and PE inputs for logic operations, other
following each Low to High clock
outputs. Shift left operation (Q3-Q2) can
outputs to the Dn-1 inputs and
n
MR) input sets all Q outputs Low,
) and parallel
0-Q1
) via the J and K
0
PE)
PInout
MR
D0
D1
D2
D3
GND
1
2
J
3
K
4
5
6
7
8
CD74HC195
(PDIP, SOIC)
TOP VIEW
Ordering Information
PKG.
PART NUMBER TEMP. RANGE (oC) PACKAGE
CD74HC195E -55 to 125 16 Ld PDIP E16.3
16
V
CC
15
Q
0
14
Q
1
13
Q
2
12
Q
3
11
Q
3
10
CP
9
PE
CD74HC195M -55 to 125 16 Ld SOIC M16.15
NOTES:
1. When ordering, use the entire part number.
2. Die for this part number is available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.
NO.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1997
1
File Number 1482.1
Functional Diagram
CP
MR
CD74HC195
D0D1D2D
PE
94567
2
J
10
3
K
1
15 14 13 12
3
11
Q
3
Q0Q1Q2Q
3
TRUTH TABLE
INPUTS OUTPUT
OPERATING MODES
MR CP PE J KDnQ0Q
Q
1
Q
2
Q
3
3
Asynchronous Reset L XXXXXLLLLH
Shift, Set First Stage H ↑ hhhX
H
Shift, Reset First Stage H ↑ hllXLq0q
Shift, Toggle First Stage H ↑ hhlXq
0
Shift, Retain First Stage H ↑ hlhXq0q
Parallel Load H ↑ lXXdnd0d
q
0
q
0
0
1
q
1
1
q
1
q
1
d
2
q
2
q
2
q
2
q
2
q
q
q
q
d3 d2
2
2
2
2
NOTE: H = High Voltage Level
L = Low Voltage Level,
X = Don’t Care
↑ = Transition from Low to High Level
l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition
h = Low Voltage Level One Set-up Time prior to the High to Low Clock Transition,
dn (qn) = Lower Case Letters Indicate the State of the Referenced Input (or output) One Set-up Time Prior to the Low to High Clock
Transition.
2
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