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CD54HC194F3A
Datasheet
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Texas Instruments CD74HCT194E, CD74HC194M96, CD74HC194M, CD74HC194E, CD54HC194F3A Datasheet

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CD74HC194,
/ j
[ /Title (CD74 HC194, CD74H CT194)
Sub-
ect (High­Speed CMOS Logic 4-Bit
Data sheet acquired from Harris Semiconductor SCHS164
September 1997
Features
• Four Operating Modes
- Shift Right, Shift Left, Hold and Reset
• Synchronous Parallel or Serial Operation
• Typical f T
= 25oC
A
• Asynchronous Master Reset
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
= 0.8V (Max), VIH = 2V (Min)
IL
- CMOS Input Compatibility, I
= 60MHz at VCC = 5V, CL = 15pF,
= 30%, NIH = 30% of V
IL
≤ 1µA at VOL, V
l
o
CD74HCT194
High-Speed CMOS Logic
4-Bit Bidirectional Universal Shift Register
Description
The Harris CD74HC194 and CD74HCT194 are 4-bit shift
C to 125oC
CC
OH
registers with Asynchronous Master Reset ( allel mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the output after the posi­tive transition of the clock input (CP). During parallel loading serial data flow is inhibited. Shift left and shift right are accomplished synchronously on the positive clock edge with serial data entered at the shift left (DSL) serial input for the shift right mode, and at the shift right (DSR) serial input for the shift left mode. Clearing the register is accomplished by a Low applied to the Master Reset (
MR) pin.
Ordering Information
PART NUMBER TEMP. RANGE (oC) PACKAGE
CD74HC194E -55 to 125 16 Ld PDIP E16.3 CD74HCT194E -55 to 125 16 Ld PDIP E16.3 CD74HC194M -55 to 125 16 Ld SOIC M16.15
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.
2. Die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information.
MR). In the par-
PKG.
NO.
Pinout
CD74HC194, CD74HCT194
(PDIP, SOIC)
TOP VIEW
V
1
MR
2
DSR
3
D
0
4
D
1
5
D
2
6
D
3
DSL
7 8
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© Harris Corporation 1997
1
16
CC
15
Q
0
14
Q
1
13
Q
2
12
Q
3
11
CP
10
S1
9
S0
File Number 1668.1
Functional Diagram
CD74HC194, CD74HCT194
D
D
D
D
DSL
DSR
S0 S1
MR
CP
3
0
4
1
5
2
6
3
2 9 10 1 11
7
15
14
13
12
GND = 8
= 16
V
CC
Q
0
Q
1
Q
2
Q
3
TRUTH TABLE
INPUTS OUTPUT
OPERATING
MODE
CP MR S1 S0 DSR DSL D
n
Q
Q
0
Q
1
Q
2
3
Reset (Clear) X L X X X X X LLLL Hold (Do Nothing) X H l (Note 2) l (Note 2) X X X q Shift Left ↑ H h l (Note 2) X l X q
↑ H h l (Note 2) X h X q
0
1
1
Shift Right ↑ H l (Note 2) h l X X L q
↑ H l (Note 2) h h X X H q
Parallel Load ↑ Hh hXXdnd
0
q
1
q
2
q
2
0
0
d
1
q
2
q
3
q
3
q
1
q
1
q
2
q
3
L
H
q
2
q
2
d
3
NOTES:
1. H = High VoltageLevel, h = High Voltage Level One Set-up Time Prior To The Low to High Clock Transition, L = Low Voltage Level, l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition, dn(qn) = Lower Case Letters Indicate the State of the Referenced Input (or output) One Set-up Time Prior to the Low To High Clock Transition, X = Don’t Care, ↑ = Transition from Low to High Level
2. The High to Low transition of the S0 and S1 Inputs on the CD74HC194, CD74HCT194 should only take place while CP is High for Conventional Operation.
2
CD74HC194, CD74HCT194
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
OK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, I
O
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, I
CC orIGND
. . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, V
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
CC
Thermal Resistance (Typical, Note 3) θJA (oC/W)
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CC
DC Electrical Specifications
PARAMETER SYMBOL
HC TYPES
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage CMOS Loads
High Level Output Voltage TTL Loads
Low Level Output Voltage CMOS Loads
V
IH
V
IL
V
OH
V
OL
TEST
CONDITIONS
25oC -40oC TO 85oC -55oC TO 125oC
VCC (V)
- - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V
- - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V
VIH or
V
-0.02 2 1.9 - - 1.9 - 1.9 - V
IL
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
VIH or
V
0.02 2 - - 0.1 - 0.1 - 0.1 V
IL
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
Low Level Output Voltage TTL Loads
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
3
CD74HC194, CD74HCT194
DC Electrical Specifications (Continued)
TEST
CONDITIONS
25oC -40oC TO 85oC -55oC TO 125oC
PARAMETER SYMBOL
Input Leakage Current
Quiescent Device Current
HCT TYPES
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage CMOS Loads
High Level Output Voltage TTL Loads
Low Level Output Voltage CMOS Loads
Low Level Output Voltage TTL Loads
VCC (V)
I
VCC or
I
-6--±0.1 - ±1-±1 µA
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
GND
I
CC
VCC or
0 6 - - 8 - 80 - 160 µA
GND
V
IH
- - 4.5 to
2-- 2 - 2 - V
5.5
V
IL
- - 4.5 to
- - 0.8 - 0.8 - 0.8 V
5.5
V
OH
VIH or
V
IL
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-4 4.5 3.98 - - 3.84 - 3.7 - V
V
OL
VIH or
V
IL
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
4 4.5 - - 0.26 - 0.33 - 0.4 V
Input Leakage Current
Quiescent Device Current
Additional Quiescent Device Current Per
I
VCC to
I
0 5.5 - - ±0.1 - ±1-±1 µA
GND
I
CC
VCC or
0 5.5 - - 8 - 80 - 160 µA
GND
∆I
CC
V
CC
-2.1
- 4.5 to
5.5
- 100 360 - 450 - 490 µA
Input Pin: 1 Unit Load (Note 4)
NOTE:
4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT UNIT LOADS
CP 0.6 MR 0.55
DSL, DSR, D
n
Sn 1.10
NOTE: Unit Load is ∆ICClimit specified in DC Electrical Specifications table, e.g. 360µA max at 25oC.
0.25
4
Prerequisite For Switching Function
CD74HC194, CD74HCT194
PARAMETER SYMBOL
HC TYPES
Max. Clock Frequency (Figure 1)
MR Pulse Width (Figure 2)
Clock Pulse Width (Figure 1)
Set-up Time Data to Clock (Figure 3)
Removal Time, MR to Clock (Figure 2)
f
MAX
t
t
t
t
REM
W
W
SU
TEST
25oC -40oC TO 85oC -55oC TO 125oC
CONDITIONS VCC (V)
- 26-5-4-MHz
4.5 30 - 24 - 20 - MHz 6 35 - 28 - 23 - MHz
- 2 80 - 100 - 120 - ns
4.5 16 - 20 - 24 - ns 614-17-20-ns
- 2 80 - 100 - 120 - ns
4.5 16 - 20 - 24 - ns 614-17-20-ns
- 2 70 - 90 - 105 - ns
4.5 14 - 18 - 21 - ns 612-15-19-ns
- 2 60 - 75 - 90 - ns
4.5 12 - 15 - 18 - ns
UNITSMIN MAX MIN MAX MIN MAX
Set-Up Time S1, S0 to Clock (Figure 4)
Set-up Time DSL, DSR to Clock (Figure 4)
Hold Time S1, S0 to Clock (Figure 4
Hold Time Data to Clock (Figure 3)
HCT TYPES
Max. Clock Frequency (Figure 1) f MR Pulse Width (Figure 2) t Clock Pulse Width (Figure 1) t Set-up Time, Data to Clock
(Figure 3)
t
SU
t
SU
t
H
t
H
MAX
W W
t
SU
610-13-15-ns
- 2 80 - 100 - 120 - ns
4.5 16 - 20 - 24 - ns 614-17-20-ns
- 2 70 - 90 - 105 - ns
4.5 14 - 18 - 21 - ns 612-15-18-ns
- 20-0-0-ns
4.50-0-0-ns 60-0-0-ns
- 20-0-0-ns
4.50-0-0-ns 60-0-0-ns
- 4.5 27 - 22 - 18 - MHz
- 4.5 16 - 20 - 24 - ns
- 4.5 16 - 20 - 24 - ns
- 4.5 14 - 18 - 21 - ns
Removal Time MR to Clock (Figure 2)
t
REM
- 4.5 12 - 15 - 18 - ns
5
CD74HC194, CD74HCT194
Prerequisite For Switching Function (Continued)
TEST
PARAMETER SYMBOL
Set-up Time
t
SU
CONDITIONS VCC (V)
- 4.5 20 - 25 - 30 - ns
S1, S0 to Clock (Figure 4) Set-up Time
t
SU
- 4.5 14 - 18 - 21 - ns
DSL, DSR to Clock (Figure 4) Hold Time
t
H
- 4.50-0-0-ns
S1, S0 to Clock (Figure 4) Hold Time
t
H
- 4.50-0-0-ns
Data to Clock (Figure 3)
Switching Specifications Input t
PARAMETER SYMBOL
, tf = 6ns
r
CONDITIONS
TEST
V
CC
(V)
HC TYPES
Propagation Delay, Clock to Output (Figure 1)
t
PLH
, t
PHLCL
= 50pF 2 - 175 220 265 ns
4.5 - 35 44 53 ns 6 - 30 37 45 ns
Propagation Delay,
t
PLH
, t
PHL
- 5 14 - - - ns
Clock to Q Output Transition Time
(Figure 1)
t
TLH
, t
THLCL
= 50pF 2 - 75 95 110 ns
4.5 - 15 19 22 ns 6 - 13 16 19 ns
Propagation Delay, MR to Output (Figure 2)
t
PHL
CL= 50pF 2 - 140 175 210 ns
4.5 - 28 35 42 ns 6 - 24 30 36 ns
Input Capacitance C Maximum Clock Frequency f Power Dissipation
MAX
C
IN
PD
---1010 10pF
- 5 60 - - - MHz
- 5 55 - - - pF
Capacitance (Notes 5, 6)
HCT TYPES
Propagation Delay,
t
PLH
, t
PHLCL
= 50pF 4.5 - 37 46 56 ns
Clock to Output (Figure 1) Propagation Delay,
t
PLH
, t
PHL
- 5 15 - - - ns
Clock to Q Output Transition Times
t
TLH
, t
THLCL
= 50pF 4.5 - 15 19 22 ns
(Figure 1) Propagation Delay,
t
PHL
CL= 50pF 4.5 - 40 50 60 ns
MR to Output (Figure 2) Input Capacitance C Maximum Clock Frequency f Power Dissipation
MAX
C
IN
PD
---1010 10pF
- 5 50 - - - MHz
- 5 60 - - - pF
Capacitance (Notes 5, 6)
NOTES:
5. CPD is used to determine the dynamic power consumption, per gate.
6. PD = V
2
fi + ∑ (CL V
CC
2
) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
CC
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN MAX MIN MAX MIN MAX
25oC -40oC TO 85oC -55oC TO 125oC
UNITSTYP MAX MAX MAX
6
Test Circuits and Waveforms
CD74HC194, CD74HCT194
INPUT LEVEL
CP
10%
90% V
S
t
t
PHL
r
t
W
V
t
S
10%
f
V
Q
V
S
t
THL
FIGURE 1. CLOCK PRE-REQUISITE TIMES AND
PROPAGATION AND OUTPUT TRANSITION TIMES
VALID
DAT A
CP
V
S
t
SU
t
H
V
S
INPUT LEVEL GND INPUT LEVEL
GND
FIGURE 3. DATA PRE-REQUISITE TIMES FIGURE4. PARALLELLOAD OR SHIFT-LEFT/SHIFT-RIGHT
S
GND
t
PLH
90%
V
S
10%
t
TLH
MR
CP
V
t
PHL
Q
V
S
t
S
W
t
REM
V
S
V
S
INPUT LEVEL GND
INPUT LEVEL GND
FIGURE 2. MASTER RESET PRE-REQUISITE TIMES AND
PROPAGATION DELAYS
VALID
S OR DS
CP
V
S
t
SU
t
H
V
S
INPUT LEVEL GND
INPUT LEVEL GND
PRE-REQUISITE TIMES
7
IMPORTANT NOTICE
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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
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