Texas Instruments CD74HCT174M96, CD74HCT174M, CD74HCT174E, CD74HC174M96, CD74HC174M Datasheet

...
CD74HC174,
/ j
[ /Title (CD74 HC174 , CD74 HCT17
4) Sub­ect
(High Speed CMOS Logic Hex D­Type Flip­Flop
Data sheet acquired from Harris Semiconductor SCHS159
August 1997
Features
• Buffered Positive Edge Triggered Clock
• Asynchronous Common Reset
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
at VCC = 5V
= 30%, NIH = 30% of V
IL
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
= 0.8V (Max), VIH = 2V (Min)
IL
- CMOS Input Compatibility, I
1µA at VOL, V
l
o
C to 125oC
CC
OH
CD74HCT174
High Speed CMOS Logic
Hex D-Type Flip-Flop with Reset
Description
The Harris CD74HC174 and CD74HCT174 are edge triggered flip-flops which utilize silicon gate CMOS circuitry to implement D-type flip-flops. They possess low pow er and speeds comparable to low power Schottky TTL circuits. The devices contain six master-slave flip-flops with a common clock and common reset. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the CLOCK input. The input, when low, sets all outputs to a low state.
Each output can drive ten low power Schottky TTL equivalent loads. The CD74HCT174 is functional as well as, pin compatible to the 74LS174.
Ordering Information
TEMP.RANGE
PART NUMBER
CD74HC174E -55 to 125 16 Ld PDIP E16.3 CD74HCT174E -55 to 125 16 Ld PDIP E16.3 CD74HC174M -55 to 125 16 Ld SOIC M16.15 CD74HCT174M -55 to 125 16 Ld SOIC M16.15
(oC) PACKAGE
MR
PKG.
NO.
Pinout
CD74HCT174W -55 to 125 Wafer
NOTES:
1. When ordering,use theentire part number.Add the suffix 96 to obtain the variant in the tape and reel.
2. Die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information.
CD74HC174, CD74HCT174
(PDIP, SOIC)
TOP VIEW
MR
Q D D Q D Q
GND
1 2
0
3
0
4
1
5
1
6
2
7
2
8
16 15 14 13 12 11 10
9
V Q D D Q D Q CP
CC
5 5 4
4 3
3
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© Harris Corporation 1997
1
File Number 1608.1
Functional Diagram
CD74HC174, CD74HCT174
CP
MR
D
0
D
1
D
2
D
3
D
4
D
5
CP D R
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
TRUTH TABLE
INPUTS OUTPUT
RESET (MR) CLOCK CP DATA D
n
Q
n
LXXL
Logic Diagram
3 (4, 6, 11, 13, 14) D
D
n
1
MR
9
CP
H HH H LL HLXQ
0
NOTE: H = High Voltage Level, L = Low Voltage Level,X = Irrelevant,= Transition from Low to High Level, Q0 = Level Before the Indicated Steady-State Input Conditions Were Established
C
L
p n
C
C
L
R
L
p n
C
L
CP
C
L
p n
C
C
L
C
L
L
p n
C
L
TO OTHER FIVE F/F
TO OTHER FIVE F/F
ONE OF SIX F/F
C
L
2 (5, 7, 10, 12, 15)
Q
816
V
Q
CC
n
2
CD74HC174, CD74HCT174
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
OK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, I
O
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, I
CC orIGND
. . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, V
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
CC
Thermal Resistance (Typical, Note 3) θJA (oC/W)
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CC
DC Electrical Specifications
PARAMETER SYMBOL
HC TYPES
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage CMOS Loads
High Level Output Voltage TTL Loads
Low Level Output Voltage CMOS Loads
Low Level Output Voltage TTL Loads
Input Leakage Current
Quiescent Device Current
V
IH
V
IL
V
OH
V
OL
I
I
I
CC
TEST
CONDITIONS
25oC -40oC TO +85oC -55oC TO 125oC
VCC (V)
- - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V
- - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V
VIH or
V
-0.02 2 1.9 - - 1.9 - 1.9 - V
IL
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
VIH or
V
0.02 2 - - 0.1 - 0.1 - 0.1 V
IL
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
VCC or
-6--±0.1 - ±1-±1 µA
GND
VCC or
0 6 - - 8 - 80 - 160 µA
GND
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
3
CD74HC174, CD74HCT174
DC Electrical Specifications (Continued)
TEST
CONDITIONS
PARAMETER SYMBOL
HCT TYPES
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage CMOS Loads
High Level Output Voltage TTL Loads
Low Level Output Voltage CMOS Loads
Low Level Output Voltage TTL Loads
Input Leakage Current
Quiescent Device Current
Additional Quiescent Device Current Per Input Pin: 1 Unit Load (Note 4)
NOTE:
4. For dual-supply systems theorectical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
V
IH
V
IL
V
OH
V
OL
I
I
I
CC
I
CC
- - 4.5 to
- - 4.5 to
VIH or
V
VIH or
V
VCC to
GND
VCC or
GND
V
CC
-2.1
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
IL
IL
VCC (V)
5.5
5.5
-4 4.5 3.98 - - 3.84 - 3.7 - V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
4 4.5 - - 0.26 - 0.33 - 0.4 V
0 5.5 - - ±0.1 - ±1-±1 µA
0 5.5 - - 8 - 80 - 160 µA
- 4.5 to
5.5
25oC -40oC TO +85oC -55oC TO 125oC
2-- 2 - 2 - V
- - 0.8 - 0.8 - 0.8 V
- 100 360 - 450 - 490 µA
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HCT Input Loading Table
INPUT UNIT LOADS
CP 0.80 MR 0.55
D 0.15
NOTE: Unit Load is ICClimit specified in DC Electrical Specifications table, e.g. 360µA max at 25oC.
Prerequisite For Switching Function
TEST
PARAMETER SYMBOL
HC TYPES
Clock Pulse Width t
MR Pulse Width t
CONDITIONS VCC (V)
w
w
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN MAX MIN MAX MIN MAX
- 2 80 - 100 - 120 - ns
4.5 16 - 20 - 24 - ns 614-17-20-ns
- 2 80 - 100 - 120 - ns
4.5 16 - 20 - 24 - ns 614-17-20-ns
4
CD74HC174, CD74HCT174
Prerequisite For Switching Function (Continued)
PARAMETER SYMBOL
Setup Time, Data to Clock t
Hold Time, Data to Clock t
Removal Time, MR to Clock t
Clock Frequency f
HCT TYPES
Clock Pulse Width t MR Pulse Width t Setup Time, Data to Clock t Hold Time, Data to Clock t Removal Time, MR to Clock t Clock Frequency f
SU
H
REM
MAX
w w
SU
H REM MAX
TEST
25oC -40oC TO 85oC -55oC TO 125oC
CONDITIONS VCC (V)
- 2 60 - 75 - 90 - ns
4.5 12 - 15 - 18 - ns 610-13-15-ns
- 25-5-5-ns
4.55-5-5-ns 65-5-5-ns
- 25-5-5-ns
4.55-5-5-ns 65-5-5-ns
- 26-5-4-MHz
4.5 30 - 24 - 20 - MHz 6 35 - 28 - 24 - MHz
- 4.5 20 - 25 - 30 - ns
- 6 25 - 31 - 38 - ns
- 4.5 16 - 20 - 24 - ns
- 65-5-5-ns
- 4.5 12 - 15 - 18 - ns
- 6 25 - 20 - 17 - MHz
UNITSMIN MAX MIN MAX MIN MAX
Switching Specifications Input t
PARAMETER SYMBOL
HC TYPES
Propagation Delay,Clockto Q t
Propagation Delay, MR to Q t
Output Transition Times t
Input Capacitance C Power Dissipation
Capacitance (Notes 5, 6)
PLH
PLH
TLH
, t
, t
, t
IN
C
PD
, tf = 6ns
r
TEST
25oC -40oC TO 85oC -55oC TO 125oC
CONDITIONS VCC (V)
PHLCL
= 50pF 2 - 165 205 250 ns
4.5 - 33 41 50 ns 6 - 28 35 43 ns
CL= 15pF 5 13 - - - ns
PHLCL
= 50pF 2 - 150 190 225 ns
4.5 - 30 38 45 ns 6 - 26 33 38 ns
CL= 15pF 5 12 - - - ns
THLCL
= 50pF 2 - 75 95 110 ns
4.5 - 15 19 22 ns 6 - 13 16 19 ns
---1010 10pF
- 5 38 - - - pF
UNITSTYP MAX MAX MAX
5
CD74HC174, CD74HCT174
Switching Specifications Input t
, tf = 6ns (Continued)
r
TEST
PARAMETER SYMBOL
CONDITIONS VCC (V)
HCT TYPES
Propagation Delay,Clockto Q t
PLH
, t
PHLCL
= 50pF 4.5 - 40 50 60 ns
CL= 15pF 5 17 - - - ns
Propagation Delay, MR to Q t
PLH
, t
PHLCL
= 50pF 4.5 - 44 55 66 ns
CL= 15pF 5 18 - - - ns Output Transition Times t Input Capacitance C Power Dissipation
TLH
C
, t
THLCL
IN
PD
= 50pF 4.5 - 15 19 22 ns
---1010 10pF
- 5 44 - - - pF Capacitance (Notes 5, 6)
NOTES:
5. CPD is used to determine the dynamic power consumption, per flip-flop.
6. PD=V
CC
2
fi+(CLV
2
+fO)where fi=Input Frequency, fO=Input Frequency, CL=Output Load Capacitance, VCC=Supply Voltage.
CC
Test Circuits and Waveforms
25oC -40oC TO 85oC -55oC TO 125oC
UNITSTYP MAX MAX MAX
90%
t
PLH
IC
t
TLH
tfC
L
50%
t
H(L)
t
SU(L)
t
THL
90%
50%
10% t
PHL
C
L
50pF
V
CC
GND
V
CC
50% GND
GND
CLOCK
INPUT
DAT A
INPUT
t
SU(H)
OUTPUT
t
REM
V
CC
SET, RESET OR PRESET
trC
L
90%
10%
t
H(H)
50%
FIGURE 1. HC SETUP TIMES, HOLD TIMES, REMOVALTIME,
AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS
CLOCK
INPUT
DAT A
INPUT
t
SU(H)
OUTPUT
t
REM
3V SET, RESET OR PRESET
trC
L
2.7V
0.3V
t
H(H)
1.3V
1.3V
1.3V
90%
t
PLH
IC
1.3V
t
TLH
tfC
L
1.3V
t
H(L)
1.3V
t
SU(L)
t
THL
90%
1.3V 10%
t
PHL
C
L
50pF
3V
GND
3V
GND
GND
FIGURE 2. HCTSETUPTIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS
6
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