TEXAS INSTRUMENTS CD54HC173 Technical data

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Data sheet acquired from Harris Semiconductor
SCHS158E

February 1998 - Revised October 2003

CD54HC173, CD74HC173,

CD54HCT173, CD74HCT173

High-Speed CMOS Logic

Quad D-Type Flip-Flop, Three-State

/Title
CD74H

173,
D74H

T173)
Subject
High

peed

MOS

ogic

uad D-

ype

Features

• Three-State Buffered Outputs

• Gated Input and Output Enables

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

o

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

C to 125oC

OH

Pinout

CD54HC173, CD54HCT173

(CERDIP)

CD74HC173

(PDIP, SOIC, SOP, TSSOP)

CD74HCT173

(PDIP, SOIC)

TOP VIEW

V

OE

OE2

Q
Q
Q
Q

CP

GND

1
2
3

0

4

1

5

2

6

3

7
8

16

CC

MR

15
14

D0

13

D1

12

D2
D3

11

E2

10

9

E1

Description

The ’HC173 and ’HCT173 high speed three-state quad D­type flip-flops are fabricated with silicon gate CMOS technol­ogy. They possess the low power consumption of standard
CMOS Integrated circuits, and can operate at speeds com­parable to the equivalent low power Schottky devices. The
buffered outputs can drive 15 LSTTL loads. The large output
drive capability and three-state feature make these parts ide­ally suited for interfacing with bus lines in bus oriented sys­tems.

The four D-type flip-flops operate synchronously from a com­mon clock. The outputs are in the three-state mode when
either of the two output disable pins are at the logic “1” level.
The input ENABLES allow the flip-flops to remain in their

CC

present states without having to disrupt the clock If either of
the 2 input ENABLES are taken to a logic “1” level, the Q
outputs are fed back to the inputs, forcing the flip-flops to
remain in the same state. Reset is enabled by taking the
MASTER RESET (MR) input to a logic “1” level. The data
outputs change state on the positive going edge of the clock.

The ’HCT173 logic family is functionally, as well as pin com­patible with the standard LS logic family

.

Ordering Information

TEMP. RANGE

PART NUMBER

CD54HC173F3A -55 to 125 16 Ld CERDIP
CD54HCT173F3A -55 to 125 16 Ld CERDIP
CD74HC173E -55 to 125 16 Ld PDIP
CD74HC173M -55 to 125 16 Ld SOIC
CD74HC173MT -55 to 125 16 Ld SOIC
CD74HC173M96 -55 to 125 16 Ld SOIC
CD74HC173NSR -55 to 125 16 Ld SOP
CD74HC173PW -55 to 125 16 Ld TSSOP
CD74HC173PWR -55 to 125 16 Ld TSSOP
CD74HC173PWT -55 to 125 16 Ld TSSOP

(oC) PACKAGE

CD74HCT173E -55 to 125 16 Ld PDIP
CD74HCT173M -55 to 125 16 Ld SOIC
CD74HCT173MT -55 to 125 16 Ld SOIC
CD74HCT173M96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© 2003, Texas Instruments Incorporated

1

CD54HC173, CD74HC173, CD54HCT173, CD74HCT173

Functional Diagram

E1
E2

14

D0

13

D1

12

D2

11

D3

7

CP

MR

OE1

OE2

TRUTH TABLE

INPUTS

10

9

3

Q

0

4

Q

1

5

Q

2

6

Q

3

2

115

DATA OUTPUT

n

MR CP

DATA ENABLE

E1 E2 D Q

HXXXXL

LLXXXQ
L ↑ HXXQ
L ↑ XHXQ

0

0

0

L ↑ LLLL
L ↑ LLHH

H= High Voltage Level
L = Low Voltage Level
X= Irrelevant
↑= Transition from Low to High Level
Q0= Level Before the Indicated Steady-State Input Conditions Were
Established
NOTE:

1. When either OE1or OE2(or both) is(are) high,the output isdis­abled to the high-impedance state, however, sequential opera­tion of the flip-flops is not affected.

2

Logic Diagram

9

E1

10

E2

14

D0

7

CP

15

MR

1

OE1

2

OE2

CD54HC173, CD74HC173, CD54HCT173, CD74HCT173

DQ

CP Q

R

V

CC

P

3

Q

0

N

D1
D2
D3

13
12

11

3 CIRCUITS IDENTICAL TO ABOVE CIRCUIT

IN DASHED ENCLOSURE

4

Q

1

5

Q

2

6

Q

3

3

CD54HC173, CD74HC173, CD54HCT173, CD74HCT173

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±70mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

2. The package thermal impedance is calculated in accordance with JESD 51-7.

CC

Package Thermal Impedance, θJA(see Note 2):

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67oC/W

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73oC/W

NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64οC/W

PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

V

IH

V

IL

V

OH

V

OL

I

I

I

CC

TEST

CONDITIONS

25oC -40oC TO 85oC -55oC TO 125oC

VCC (V)

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIH or

V

-0.02 2 1.9 - - 1.9 - 1.9 - V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

-6 4.5 3.98 - - 3.84 - 3.7 - V

-7.8 6 5.48 - - 5.34 - 5.2 - V

VIH or

V

0.02 2 - - 0.1 - 0.1 - 0.1 V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V
6 4.5 - - 0.26 - 0.33 - 0.4 V

7.8 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

VCC or

0 6 - - 8 - 80 - 160 µA

GND

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

4

CD54HC173, CD74HC173, CD54HCT173, CD74HCT173

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Three-State Leakage
Current

I

OZ

VIL or

V

IH

VCC (V)

-6--±0.5 - ±0.5 - ±10 µA

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage

V

IH

- - 4.5 to

5.5

V

IL

- - 4.5 to

5.5

V

OH

VIH or

V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

CMOS Loads
High Level Output

-6 4.5 3.98 - - 3.84 - 3.7 - V
Voltage
TTL Loads

Low Level Output
Voltage

V

OL

VIH or

V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

CMOS Loads
Low Level Output

6 4.5 - - 0.26 - 0.33 - 0.4 V
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Additional Quiescent
Device Current Per

I

I

I

CC

∆I

CC

(Note 3)

VCC to

GND

VCC or

GND

V

CC

-2.1

0 5.5 - - ±0.1 - ±1-±1 µA

0 5.5 - - 8 - 80 - 160 µA

- 4.5 to

5.5

Input Pin: 1 Unit Load
Three-State Leakage

Current

I

OZ

VIL or

V

IH

- 5.5 - - ±0.5 - ±5.0 - ±10 µA

NOTE:

3. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

25oC -40oC TO 85oC -55oC TO 125oC

2-- 2 - 2 - V

- - 0.8 - 0.8 - 0.8 V

- 100 360 - 450 - 490 µA

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

D0-D3 0.15

E1 and E2 0.15

CP 0.25

MR 0.2

OE1 and OE2 0.5

NOTE: Unit Load is ∆ICClimit specified in DC Electrical
Specifications table, e.g., 360µA max at 25oC.

5

CD54HC173, CD74HC173, CD54HCT173, CD74HCT173

Switching Specifications Input t

, tf = 6ns

r

TEST

PARAMETER SYMBOL

CONDITIONS V

CC

(V)

HC TYPES

Propagation Delay, Clock to
Output

t

PLH

, t

PHLCL

= 50pF 2 - 200 250 300 ns

4.5 - 40 50 60 ns
CL= 15pF 5 17 - - - ns
CL = 50pF 6 - 34 43 51 ns

Propagation Delay, MR to
Output

t

PHL

CL= 50pF 2 - 175 220 265 ns

4.5 - 35 44 53 ns
CL= 15pF 5 12 - - - ns
CL = 50pF 6 - 30 37 45 ns

Propagation Delay Output
Enable to Q (Figure 6)

t
t

PLZ
PZL

, t
, t

CL = 50pF 2 150 190 225 ns

PHZ
PZH

CL= 50pF 4.5 30 38 45 ns
CL= 15pF 5 12 - - - ns
CL = 50pF 6 26 33 38 ns

Output Transition Times t

TLH

, t

THLCL

= 50pF 2 - 60 75 90 ns

4.5 - 12 15 18 ns

6 - 10 13 15 ns
Maximum Clock Frequency f
Input Capacitance C
Three-State Output

MAX

IN

C

O

CL= 15pF 5 60 - - - MHz

---1010 10pF

---1010 10pF

Capacitance
Power Dissipation

C

PD

- 5 29 - - - pF
Capacitance
(Notes 4, 5)

HCT TYPES

Propagation Delay, Clock to
Output

Propagation Delay, MR to
Output

Propagation Delay Output
Enable to Q (Figure 6)

t

t

PLH

PZL

, t

PHLCL

t

PHL

, t

PZH

= 50pF 4.5 - 40 50 60 ns
CL= 15pF 5 17 - - - ns
CL= 50pF 4.5 - 44 55 66 ns
CL= 15pF 5 18 - - - ns
CL = 50pF 2 150 190 225 ns
CL= 50pF 4.5 30 38 45 ns
CL= 15pF 5 14 - - - ns
CL = 50pF 6 26 33 38 ns

Output Transition Times t
Maximum Clock Frequency f
Input Capacitance C
Power Dissipation

TLH

C

, t

THLCL

MAX

IN

PD

= 50pF 4.5 - 15 19 22 ns
CL= 15pF 5 60 - - - MHz

---1010 10pF

- 5 34 - - - pF
Capacitance
(Notes 4, 5)

NOTES:

4. CPD is used to determine the dynamic power consumption, per package.

5. PD=V

CC

2

fi+∑ (CLV

2

+fO)where fi=Input Frequency,fO=Input Frequency,CL=Output LoadCapacitance, VCC=Supply Voltage.

CC

25oC -40oC TO 85oC -55oC TO 125oC

UNITSTYP MAX MAX MAX

6