Texas Instruments CD74HCT166M96, CD74HCT166M, CD74HCT166E, CD74HC166M96, CD74HC166M Datasheet
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CD74HC166,
/
j
[ /Title
(CD74
HC166
,
CD74
HCT16
6)
Subect
(High
Speed
CMOS
Logic
8-Bit
ParallelIn/Seri
Data sheet acquired from Harris Semiconductor
SCHS157
February 1998
Features
• Buffered Inputs
• Typical f
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
Pinout
= 50MHz at VCC = 5V, CL = 15pF, TA = 25oC
MAX
o
= 30%, NIH = 30% of V
IL
CD74HC166, CD74HCT166 (PDIP, SOIC)
GND
C to 125oC
CC
TOP VIEW
1
DS
2
D0
D1
3
D2
4
D3
5
6
CE
7
CP
8
CD74HCT166
High Speed CMOS Logic
8-Bit Parallel-In/Serial-Out Shift Register
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
= 0.8V (Max), VIH = 2V (Min)
IL
- CMOS Input Compatibility, I
Ordering Information
TEMP. RANGE
PART NUMBER
CD74HC166E -55 to 125 16 Ld PDIP E16.3
CD74HCT166E -55 to 125 16 Ld PDIP E16.3
CD74HC166M -55 to 125 16 Ld SOIC M16.15
CD74HCT166M -55 to 125 16 Ld SOIC M16.15
CD54HC166W -55 to 125 Wafer
NOTES:
1. When ordering,use the entire partnumber.Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die is available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.
V
16
CC
15
PE
14
D7
13
Q7
D6
12
D5
11
D4
10
9
MR
(oC) PACKAGE
≤ 1µA at VOL, V
l
OH
PKG.
NO.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1998
1
File Number 1501.1
Functional Diagram
CD74HC166, CD74HCT166
D0 D1 D2 D3 D4 D5 D6 D7
PE
D
CP
CE
MR
S
P ARALLEL ENABLE CIRCUIT
D0 D7
8 - REGISTERS
Q7
TRUTH TABLE
INPUTS
INTERNAL
MASTER
RESET
PARALLEL
ENABLE
CLOCK
ENABLE CLOCK SERIAL
PARALLEL
D0 D7 Q0 Q1
Q STATES
OUTPUT
Q7
LXXXXXLLL
H X L L X X Q00 Q10 Q0
HLL↑ X a...h a b h
HHL ↑ H X H Q0n Q6n
HHL ↑ L X L Q0n Q6n
HXH↑ X X Q00 Q10 Q70
NOTES:
H = High Voltage Level
L = Low Voltage Level
X = Don’t Care
↑ = Transition from Low to High Level
a...h = The level of steady-state input at inputs D0 thru D7, respectively.
Q00, Q10, Q70 = The level of Q0, Q1, or Q7, respectively, before the indicated steady-state input conditions were established.
Q0n, Q6n = The level of Q0 or Q6, respectively, before the most recent ↑ transition of the clock.
2
CD74HC166, CD74HCT166
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
OK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, I
O
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
DC Output Source or Sink Current per Output Pin, I
O
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, I
CC orIGND
. . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, V
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
CC
Thermal Resistance (Typical, Note 3) θJA (oC/W)
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CC
DC Electrical Specifications
PARAMETER SYMBOL
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
V
IH
V
IL
V
OH
V
OL
I
I
TEST
CONDITIONS
25oC -40oC TO 85oC -55oC TO 125oC
VCC (V)
- - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
- - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
VIH or
V
-0.02 2 1.9 - - 1.9 - 1.9 - V
IL
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
VIH or
V
0.02 2 - - 0.1 - 0.1 - 0.1 V
IL
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
VCC or
-6--±0.1 - ±1-±1 µA
GND
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
3
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