Datasheet CD74HCT14M96, CD74HCT14M, CD74HCT14E, CD74HC14M96, CD74HC14M Datasheet (Texas Instruments)

Data sheet acquired from Harris Semiconductor

/

SCHS129

January 1998

CD74HC14,

CD74HCT14

High Speed CMOS Logic

Hex Inverting Schmitt Trigger

[ /Title
(CD74H
C14,
CD74H
CT14)

Subject
(High
Speed
CMOS
Logic
Hex
Invert-

Features

• Unlimited Input Rise and Fall Times

• Exceptionally High Noise Immunity

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, NIH = 30% of V

IL

o

C to 125oC

Pinout

CD54HC14, CD54HCT14, CD74HC14, CD74HCT14

(PDIP, CERDIP, SOIC)

1A

1
2

1Y

3

2A

4

2Y

5

3A

6

3Y

7

GND

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,
V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

≤ 1µA at VOL, V

l

Description

The Harris CD74HC14, CD74HCT14 each contain 6
inverting Schmitt Triggers in one package.

Ordering Information

TEMP. RANGE

CC

TOP VIEW

PART NUMBER

CD54HCT14F -55 to 125 14 Ld CERDIP F14.3

14

V

CC

6A

13
12

6Y
5A

11

5Y

10

4A

9

4Y

8

(oC) PACKAGE

OH

PKG.

NO.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1998

1

File Number 1781.1

Functional Diagram

CD74HC14, CD74HCT14

INPUT (A) OUTPUT (Y)

NOTE:
H= High Level
L= Low Level

1A

2A

3A

4A

5A

6A

1

3

5

9

11

13

2

1Y

4

2Y

6

3Y

8

4Y

10

5Y

12

6Y

GND = 7

= 14

V

CC

TRUTH TABLE

LH

HL

Logic Diagram

nA nY

2

CD74HC14, CD74HCT14

V

V

O

V

CC

V

I

GND

V

CC

V

O

GND

FIGURE 3. HYSTERESIS DEFINITION, CHARACTERISTIC, AND TEST SETUP

H

VH = VT+ - VT-

V

I

VT-VT+

+V

V

T

-

T

V

H

3

CD74HC14, CD74HCT14

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

For -0.5V < VO < VCC +0.5V . . . . . . . . . . . . . . . . . . . . . . . . . .±25mA

DC Output Source or Sink Current per Output Pin, I

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

IK

OK

O

O

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time, tr, t

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

f

Thermal Resistance (Typical, Note 3) θJA (oC/W) θJC (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . 90 -

CERDIP Package . . . . . . . . . . . . . . . . 130 55

SOIC Package. . . . . . . . . . . . . . . . . . . 120 -

Maximum Junction Temperature (Hermetic P ac kage or Die) . . . 175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

TEST

CONDITIONS

PARAMETER SYMBOL

HC TYPES

Input Switch Points VT+ - - 2 0.7 1.5 0.7 1.5 0.7 1.5 V

VT- - - 2 0.3 1.0 0.3 1.0 0.3 1.0 V

High Level Output
Voltage CMOS Loads

High Level Output
Voltage TTL Loads

V

H

V

OH

- - 2 0.2 1.0 0.2 1.0 0.2 1.0 V

VT- or

VT+

-0.02 2 1.9 - 1.9 - 1.9 - V

-0.02 4.5 4.4 - 4.4 - 4.4 - V

-0.02 6 5.9 - 5.9 - 5.9 - V

VCC (V)

4.5 1.7 3.15 1.7 3.15 1.7 3.15 V
6 2.1 4.2 2.1 4.2 2.1 4.2 V

4.5 0.9 2.2 0.9 2.2 0.9 2.2 V
6 1.2 3.0 1.2 3.0 1.2 3.0 V

4.5 0.4 1.4 0.4 1.4 0.4 1.4 V
6 0.6 1.6 0.6 1.6 0.6 1.6 V

--------V

-4 4.5 3.98 - 3.84 - 3.7 - V

-5.2 6 5.48 - 5.34 - 5.2 - V

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN MAX MIN MAX MIN MAX

4

CD74HC14, CD74HCT14

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

LowLevelOutputVoltage
CMOS Loads

V

OL

VIH or

V

IL

VCC (V)

0.02 2 - 0.1 - 0.1 - 0.1 V

0.02 4.5 - 0.1 - 0.1 - 0.1 V

0.02 6 - 0.1 - 0.1 - 0.1 V

LowLevel Output Voltage
TTL Loads

--------V

4 4.5 - 0.26 - 0.33 - 0.4 V

5.2 6 - 0.26 - 0.33 - 0.4 V

Input Leakage Current I

VCC or

I

-6-±0.1 - ±1-±1 µA

GND

Quiescent Device
Current

I

CC

VCC or

GND

06-2-20-40µA

HCT TYPES

Input Switch Points VT+ - - 4.5 1.2 1.9 1.2 1.9 1.2 1.9 V

5.5 1.4 2.1 1.4 2.1 1.4 2.1 V

VT- 4.5 0.5 1.2 0.5 1.2 0.5 1.2 V

5.5 0.6 1.4 0.6 1.4 0.6 1.4 V

V

H

4.5 0.4 1.4 0.4 1.4 0.4 1.4 V

5.5 0.4 1.5 0.4 1.5 0.4 1.5 V

High Level Output
Voltage CMOS Loads

High Level Output

V

OH

VIH or

V

IL

-0.02 4.5 4.4 - 4.4 - 4.4 - V

-4 4.5 3.98 - 3.84 - 3.7 - V

Voltage TTL Loads
LowLevelOutputVoltage

CMOS Loads
LowLevel Output Voltage

V

OL

VIH or

V

IL

0.02 4.5 - 0.1 - 0.1 - 0.1 V

4 4.5 - 0.26 - 0.33 - 0.4 V

TTL Loads
Input Leakage Current I

I

V

CC

- 5.5 - ±0.1 - ±1-±1 µA

and

GND

Quiescent Device
Current

Additional Quiescent
Device Current Per Input

I

CC

∆I

CC

(Note 4)

VCC or

GND

V

CC

- 2.1

0 5.5 - 2 - 20 - 40 µA

- 4.5 to

5.5

Pin: 1 Unit Load

NOTE:

4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

HCT Input Loading Table

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN MAX MIN MAX MIN MAX

- 360 - 450 - 490 µA

INPUT UNIT LOADS

nA 0.6

NOTE: Unit Load is ∆ICClimit specified in DC Electrical Specifica­tions table, e.g., 360µA max at 25oC.

5

Switching Specifications Input t

PARAMETER SYMBOL

, tf = 6ns

r

TEST

CONDITIONS

V

CC

(V)

HC TYPES

Propagation Delay,
A to Y

t

PLH

, t

PHLCL

= 50pF 2 - - 135 - 170 - 205 ns
CL= 50pF 4.5 - - 27 - 34 - 41 ns
CL= 15pF 5 - 11 - ----ns
CL= 50pF 6 - - 23 - 29 - 35 ns

Output Transition Times t

TLH

, t

THLCL

= 50pF 2 - - 75 - 95 18 110 ns

4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns

Input Capacitance C
Power Dissipation Capacitance

C

I

PD

- - - - 10 - 10 - 10 pF

- 5-20-----pF

(Notes 5, 6)

HCT TYPES

Propagation Delay,
A to Y

Output Transition Times t
Input Capacitance C
Power Dissipation Capacitance

t

PLH

TLH

, t

PHLCL

, t

THLCL

I

C

PD

= 50pF 4.5 - - 38 - 48 - 57 ns

CL= 15pF 5 - 16 - ----ns

= 50pF 4.5 - - 15 - 19 - 22 ns

- - - - 10 - 10 - 10 pF

- 5-20-----pF

(Notes 5, 6)

NOTES:

5. CPD is used to determine the dynamic power consumption, per inverter.

6. PD = V

2

fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

CC

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

Test Circuits and Waveforms

tr = 6ns tf = 6ns

V

t

TLH

CC

GND

t

PHL

90%
50%
10%

t

90%

50%

10%

PLH

INPUT

t

INVERTING

OUTPUT

THL

FIGURE 4. HC TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

= 6ns

t

PLH

t

f

1.3V

10%

90%

t

TLH

3V

GND

tr = 6ns

INPUT

t

INVERTING

OUTPUT

THL

t

PHL

2.7V

1.3V

0.3V

FIGURE 5. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

6

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