TEXAS INSTRUMENTS CD54HC14, CD74HC14, CD54HCT14, CD74HCT14 Technical data

CD54HC14, CD74HC14,

[ ( C C C / ( S C L H I

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CD54HCT14, CD74HCT14

Data sheet acquired from Harris Semiconductor SCHS129C

January 1998 - Revised September 2003

High-Speed CMOS Logic

Hex Inverting Schmitt Trigger

/Title CD74H

14, D74H

T14) Subject High

peed

MOS

ogic

ex nvert-

Features

• Unlimited Input Rise and Fall Times

• Exceptionally High Noise Immunity

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

- CMOS Input Compatibility, I

VIL= 0.8V (Max), VIH = 2V (Min)

= 30%, NIH = 30% of V

≤ 1µA at VOL, V

C to 125oC

Description

The ’HC14 and ’HCT14 each contain six inverting Schmitt triggers in one package.

Ordering Information

TEMP. RANGE

PART NUMBER

CD54HC14F3A -55 to 125 14 Ld CERDIP CD54HCT14F3A -55 to 125 14 Ld CERDIP CD74HC14E -55 to 125 14 Ld PDIP CD74HC14M -55 to 125 14 Ld SOIC CD74HC14MT -55 to 125 14 Ld SOIC

CD74HC14M96 -55 to 125 14 Ld SOIC CD74HCT14E -55 to 125 14 Ld PDIP CD74HCT14M -55 to 125 14 Ld SOIC CD74HCT14MT -55 to 125 14 Ld SOIC CD74HCT14M96 -55 to 125 14 Ld SOIC

NOTE: When ordering, use the entirepart number. The sufﬁx96 denotes tape and reel. The sufﬁx T denotes a small-quantity reel of 250.

(oC) PACKAGE

Pinout

CD54HC14, CD54HCT14

(CERDIP)

CD74HC14, CD74HCT14

(PDIP, SOIC)

TOP VIEW

1 2

1Y 2A

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright

Functional Diagram

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CD54HC14, CD74HC14, CD54HCT14, CD74HCT14

6Y GND = 7 V

= 14

INPUT (A) OUTPUT (Y)

H= High Level L= Low Level

TRUTH TABLE

Logic Diagram

nA nY

GND

VH = VT+ - VT-

VT-VT+

FIGURE 3. HYSTERESIS DEFINITION, CHARACTERISTIC, AND TEST SETUP

CD54HC14, CD74HC14, CD54HCT, CD74HCT14

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Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

For -0.5V < VO < VCC +0.5V . . . . . . . . . . . . . . . . . . . . . . . . . .±25mA

DC Output Source or Sink Current per Output Pin, I

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time, tr, t

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

DC Electrical Speciﬁcations

1. The package thermal impedance is calculated in accordance with JESD 51-7.

PARAMETER SYMBOL

HC TYPES

Input Switch Points V

TEST

CONDITIONS

(V) IO(mA) MIN MAX MIN MAX MIN MAX

+ - - 2 0.7 1.5 0.7 1.5 0.7 1.5 V

- - - 2 0.3 1.0 0.3 1.0 0.3 1.0 V

- - 2 0.2 1.0 0.2 1.0 0.2 1.0 V

High Level Output Voltage CMOS Loads

High Level Output Voltage TTL Loads

VT- or

VT+

-0.02 2 1.9 - 1.9 - 1.9 - V

-0.02 4.5 4.4 - 4.4 - 4.4 - V

-0.02 6 5.9 - 5.9 - 5.9 - V

--------V

-4 4.5 3.98 - 3.84 - 3.7 - V

-5.2 6 5.48 - 5.34 - 5.2 - V

Thermal Resistance (Typical, Note 1) θJA (oC/W)

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Maximum Junction Temperature (Hermetic P ac kage or Die) . . . 175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

C -40oC TO 85oC -55oC TO 125oC

(V)

4.5 1.7 3.15 1.7 3.15 1.7 3.15 V 6 2.1 4.2 2.1 4.2 2.1 4.2 V

4.5 0.9 2.2 0.9 2.2 0.9 2.2 V 6 1.2 3.0 1.2 3.0 1.2 3.0 V

4.5 0.4 1.4 0.4 1.4 0.4 1.4 V 6 0.6 1.6 0.6 1.6 0.6 1.6 V

UNITSV

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