• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
= 0.8V (Max), VIH = 2V (Min)
IL
- CMOS Input Compatibility, I
= 37%, NIH = 51% of V
IL
≤ 1µA at VOL, V
l
CC
= 5V,
o
C to 125oC
OH
Description
The ’HC132 and ’HCT132 each contain four 2-input NAND
Schmitt Triggers in one package. This logic device utilizes
silicon gate CMOS technology to achieve operating speeds
similar to LSTTL gates with the low power consumption of
standard CMOS integrated circuits. All devices have the
ability to drive 10 LSTTL loads. The HCT logic family is
functionally pin compatible with the standard LS logic family.
Ordering Information
TEMP. RANGE
CC
PART NUMBER
CD54HC132F3A-55 to 12514 Ld CERDIP
CD54HCT132F3A-55 to 12514 Ld CERDIP
CD74HC132E-55 to 12514 Ld PDIP
CD74HC132M-55 to 12514 Ld SOIC
CD74HC132MT-55 to 12514 Ld SOIC
CD74HC132M96-55 to 12514 Ld SOIC
CD74HCT132E-55 to 12514 Ld PDIP
CD74HCT132M-55 to 12514 Ld SOIC
CD74HCT132MT-55 to 12514 Ld SOIC
(oC)PACKAGE
Pinout
CD74HCT132M96-55 to 12514 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
CD54HC132, CD54HCT132
(CERDIP)
CD74HC132, CD74HCT132
(PDIP, SOIC)
TOP VIEW
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
14
13
12
11
10
V
CC
4B
4A
4Y
3B
3A
9
3Y
8
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.