TEXAS INSTRUMENTS CD54HC132 Technical data

Data sheet acquired from Harris Semiconductor
[ ( H , C H 2 / j ( S C L Q 2 N S
SCHS145E
August 1997 - Revised March 2004
CD54HC132, CD74HC132,
CD54HCT132, CD74HCT132
High-Speed CMOS Logic
Quad 2-Input NAND Schmitt Trigger
/Title CD74
C132
D74 CT13
) Sub­ect High
peed
MOS
ogic
uad
-Input AND
chmit
Features
• Unlimited Input Rise and Fall Times
• Exceptionally High Noise Immunity
• Typical Propagation Delay: 10ns at V C
= 15pF, TA = 25oC
L
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
= 0.8V (Max), VIH = 2V (Min)
IL
- CMOS Input Compatibility, I
= 37%, NIH = 51% of V
IL
1µA at VOL, V
l
CC
o
C to 125oC
OH
Description
The ’HC132 and ’HCT132 each contain four 2-input NAND Schmitt Triggers in one package. This logic device utilizes silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 LSTTL loads. The HCT logic family is functionally pin compatible with the standard LS logic family.
Ordering Information
TEMP. RANGE
CC
PART NUMBER
CD54HC132F3A -55 to 125 14 Ld CERDIP CD54HCT132F3A -55 to 125 14 Ld CERDIP CD74HC132E -55 to 125 14 Ld PDIP CD74HC132M -55 to 125 14 Ld SOIC CD74HC132MT -55 to 125 14 Ld SOIC CD74HC132M96 -55 to 125 14 Ld SOIC CD74HCT132E -55 to 125 14 Ld PDIP CD74HCT132M -55 to 125 14 Ld SOIC CD74HCT132MT -55 to 125 14 Ld SOIC
(oC) PACKAGE
Pinout
CD74HCT132M96 -55 to 125 14 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
CD54HC132, CD54HCT132
(CERDIP)
CD74HC132, CD74HCT132
(PDIP, SOIC)
TOP VIEW
1A 1B
1Y 2A 2B
2Y
GND
1 2 3 4 5 6 7
14 13 12 11 10
V
CC
4B 4A 4Y 3B 3A
9
3Y
8
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© 2004, Texas Instruments Incorporated
1
CD54HC132, CD74HC132, CD54HCT132, CD74HCT132
Functional Diagram
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
14
V
CC
13
4B
12
4A
11
4Y
10
3B
9
3A
8
3Y
TRUTH TABLE
INPUTS OUTPUT
nA nB nY
LLH LHH HLH
Logic Symbol
HHL
H = High Voltage Level, L = Low Voltage Level
nA
nY
nB
2
CD54HC132, CD74HC132, CD54HCT132, CD74HCT132
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, I
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, I
IK
OK
CC orIGND
O
. . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, V
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
CC
DC Electrical Specifications
Thermal Resistance (Typical, Note 1) θJA (oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 80
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 86
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CC
PARAMETER SYMBOL
HC TYPES
Input Switch Points (Note 2)
High Level Output Voltage CMOS Loads
High Level Output Voltage TTL Loads
Low Level Output Voltage CMOS Loads
Low Level Output Voltage TTL Loads
TEST
CONDITIONS
VCC (V)
VT+ - - 2 0.7 - 1.5 0.7 1.5 0.7 1.5 V
4.5 1.7 - 3.15 1.7 3.15 1.7 3.15 V 6 2.1 - 4.2 2.1 4.2 2.1 4.2 V
VT- - - 2 0.3 - 1 0.3 1 0.3 1 V
4.5 0.9 - 2.2 0.9 2.2 0.9 2.2 V 6 1.2 - 3 1.2 3 1.2 3 V
V
H
V
OH
V
OL
VT+ or
VT-
VT+ or
VT-
-0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
2 0.2 - 1 0.2 1 0.2 1 V
4.5 0.4 - 1.4 0.4 1.4 0.4 1.4 V 6 0.6 - 1.6 0.6 1.6 0.6 1.6 V
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
3
CD54HC132, CD74HC132, CD54HCT132, CD74HCT132
DC Electrical Specifications (Continued)
TEST
CONDITIONS
25oC -40oC TO 85oC -55oC TO 125oC
PARAMETER SYMBOL
Input Leakage Current
Quiescent Device Current
I
I
CC
VCC or
I
GND
VCC or
GND
VCC (V)
-6--±0.1 - ±1-±1 µA
0 6 - - 2 - 20 - 40 µA
HCT TYPES
Input Switch Points (Note 2)
VT+ - - 4.5 1.2 - 1.9 1.2 1.9 1.2 1.9 V
5.5 1.4 - 2.1 1.4 2.1 1.4 2.1 V
VT- - - 4.5 0.5 - 1.2 0.5 1.2 0.5 1.2 V
5.5 0.6 - 1.4 0.6 1.4 0.6 1.4 V
V
H
- - 4.5 0.4 - 1.4 0.4 1.4 0.4 1.4 V
5.5 0.4 - 1.5 0.4 1.5 0.4 1.5 V
High Level Output Voltage
VT+
-
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
or
VT-
CMOS Loads High Level Output
-4 4.5 3.98 - - 3.84 - 3.7 - V Voltage TTL Loads
Low Level Output Voltage CMOS Loads
Low Level Output
V
OL
VT+
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
or
VT-
4 4.5 - - 0.26 - 0.33 - 0.4 V Voltage TTL Loads
Input Leakage Current
I
I
V
CC
- 5.5 - - ±0.1 - ±1-±1 µA
and
GND
Quiescent Device Current
Additional Quiescent Device Current Per
I
CC
I
CC
(Note 3)
VCC or
GND
V
CC
- 2.1
0 5.5 - - 2 - 20 - 40 µA
- 4.5 to
- 100 360 - 450 - 490 µA
5.5
Input Pin: 1 Unit Load
NOTES:
2. Hysteresis definition, characteristic and test setup see Test Circuits and Waveforms
3. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
4
CD54HC132, CD74HC132, CD54HCT132, CD74HCT132
HCT Input Loading Table
INPUT UNIT LOADS
nA, nB 0.6
NOTE: Unit Load is ICClimit specified in DC Electrical Specifica­tions table, e.g. 360µA max at 25oC.
Switching Specifications Input t
PARAMETER SYMBOL
, tf = 6ns
r
TEST
CONDITIONS
V
CC
(V)
HC TYPES
Propagation Delay A, B to Y (Figure 1)
t
PLH
, t
PHLCL
= 50pF 2 - - 125 - 156 - 188 ns
4.5 - - 25 - 31 - 38 ns 6 - - 21 - 27 - 32 ns
Propagation Delay
t
TLH
, t
THLCL
= 15pF 5 - 10 - ----pF
A, B to Y Transition Times (Figure 1) t
TLH
, t
THLCL
= 50pF 2 - - 75 - 95 - 110 ns
4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns
Input Capacitance C Power Dissipation Capacitance
C
I
PD
- - - - 10 - 10 - 10 pF
- 5-30-----pF
(Notes 4, 5)
HCT TYPES
Propagation Delay
t
PHL
, t
PHLCL
= 50pF 4.5 - - 33 - 41 - 50 ns A, B to Y (Figure 2)
Propagation Delay
t
PLH
, t
PHLCL
= 15pF 5 - 13 - ----pF A, B to Y
Transition Times (Figure 2) t Input Capacitance C Power Dissipation Capacitance
TLH
, t
I
C
PD
THLCL
= 50pF 4.5 - - 15 - 19 - 22 ns
- - - - 10 - 10 - 10 pF
- 5-30-----pF
(Notes 4, 5)
NOTES:
4. CPD is used to determine the dynamic power consumption, per gate.
5. PD = V
2
fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
CC
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
5
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