Texas Instruments CD74HCT112E, CD74HC112M96, CD74HC112E, CD54HCT112F3A, CD54HC112F3A Datasheet

Data sheet acquired from Harris Semiconductor

/
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SCHS141

March 1998

CD74HC112,

CD74HCT112

Dual J-K Flip-Flop with Set and Reset

Negative-Edge Trigger

[ /Title
(CD74
HC112
,
CD74
HCT11

2)
Sub­ect

(Dual
J-K
Flip­Flop
with
Setand
Reset
Nega-

Features

• Hysteresis on Clock Inputs for Improved Noise
Immunity and Increased Input Rise and Fall Times

• Asynchronous Set and Reset

• Complementary Outputs

• Buffered Inputs

• Typical f
T

= 25oC

A

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 60MHz at VCC = 5V, CL = 15pF,

MAX

= 30%, NIH = 30% of V

IL

o

C to 125oC

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,
V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

≤ 1µA at VOL, V

l

Description

The Harris CD74HC112 and CD74HCT112 utilize silicon­gate CMOS technology to achieve operating speeds
equivalent to LSTTL parts. They exhibit the low power
consumption of standard CMOS integrated circuits, together
with the ability to drive 10 LSTTL loads.

These flip-flops have independent J, K, Set, Reset, and
Clock inputs and Q and
negative-going transition of the clock pulse. Set and Reset
are accomplished asynchronously by low-level inputs.

The 74HCT logic family is functionally as well as pin­compatible with the standard 74LS logic family.

.

Q outputs. They change state on the

Ordering Information

TEMP. RANGE

CC

PART NUMBER

CD74HC112E -55 to 125 16 Ld PDIP E16.3

(oC) PACKAGE

OH

PKG.

NO.

Pinout

CD74HC112, CD74HCT112

(PDIP)

TOP VIEW

16

1

1CP

2

1K

3

1J

4

1S

5

1Q

6

1Q

7

2Q

8

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1998

1

V

CC

15

1R

14

2R

13

2CP
2K

12

2J

11
10

2S

9

2Q

File Number 1843.1

Functional Diagram

CD74HC112, CD74HCT112

4

1S

1K

1CP

1R

2S

2K

2CP

2R

3

1J

2

1

15

10

11

2J

12

13

14

F/F 1

F/F 2

5

1Q

6

1Q

9

2Q

7

2Q

GND = 8
VCC = 16

TRUTH TABLE

INPUTS OUTPUTS

S R CP J K Q Q

LHXXXHL
H
L
H
H
HH
HH

L

L
H ↓
H ↓

XXXLH
X X X H (Note 3) H (Note 3)

L L No Change
HL

↓
↓

LH
H H Toggle

H H H X X No Change

NOTE:
H = High Level (Steady State)
L = Low Level (Steady State)
X = Don’t Care

↓

= High-to-Low Transition

3. Output states unpredictable if both S and R go High simultaneously after both being low at the same time.

2

CD74HC112, CD74HCT112

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time, tr, t

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

4. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

f

Thermal Resistance (Typical, Note 4) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Maximum Junction Temperature (Hermetic P ac kage or Die) . . . 175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

V

IH

V

IL

V

OH

V

OL

I

I

TEST

CONDITIONS

25oC -40oC TO 85oC -55oC TO 125oC

VCC (V)

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIH or

V

-0.02 2 1.9 - - 1.9 - 1.9 - V

IL

4.5 4.4 - - 4.4 - 4.4 - V
6 5.9 - - 5.9 - 5.9 - V

---------V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIH or

V

0.02 2 - - 0.1 - 0.1 - 0.1 V

IL

4.5 - - 0.1 - 0.1 - 0.1 V
6 - - 0.1 - 0.1 - 0.1 V

---------V

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

3