TEXAS INSTRUMENTS CD54HC112 Technical data

CD54HC112, CD74HC112,

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C
H
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S
R
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CD54HCT112, CD74HCT112

/Title
CD74

C112

D74
CT11

)
Sub­ect
Dual

-K
lip­lop

ith

etand

eset
ega-

Data sheet acquired from Harris Semiconductor
SCHS141H

March 1998 - Revised October 2003

Features

• Hysteresis on Clock Inputs for Improved Noise
Immunity and Increased Input Rise and Fall Times

• Asynchronous Set and Reset

• Complementary Outputs

• Buffered Inputs

• Typical f
T

= 25oC

A

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), VIH = 2V (Min)

V

IL

- CMOS Input Compatibility, I

= 60MHz at VCC = 5V, CL = 15pF,

MAX

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

o

Pinout

CD54HC112, CD54HCT112 (CERDIP)

CD74HC112 (PDIP, SOIC, SOP, TSSOP)

CD74HCT112 (PDIP)

TOP VIEW

C to 125oC

CC

OH

Dual J-K Flip-Flop with Set and Reset

Negative-Edge Trigger

Description

The ’HC112 and ’HCT112 utilize silicon-gate CMOS
technology to achieveoperating speeds equivalent to LSTTL
parts. They exhibit the low power consumption of standard
CMOS integrated circuits, together with the ability to drive 10
LSTTL loads.

These flip-flops have independent J, K, Set, Reset, and
Clock inputs and Q and
negative-going transition of the clock pulse. Set and Reset
are accomplished asynchronously by low-level inputs.

The HCT logic family is functionally as well as pin­compatible with the standard LS logic family.

.

Ordering Information

PART NUMBER

CD54HC112F3A -55 to 125 16 Ld CERDIP
CD54HCT112F3A -55 to 125 16 Ld CERDIP
CD74HC112E -55 to 125 16 Ld PDIP
CD74HC112MT -55 to 125 16 Ld SOIC
CD74HC112M96 -55 to 125 16 Ld SOIC
CD74HC112NSR -55 to 125 16 Ld SOP
CD74HC112PW -55 to 125 16 Ld TSSOP
CD74HC112PWR -55 to 125 16 Ld TSSOP
CD74HC112PWT -55 to 125 16 Ld TSSOP
CD74HCT112E -55 to 125 16 Ld PDIP

NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.

Q outputs. They change state on the

TEMP. RANGE

(oC) PACKAGE

16

1

1CP

2

1K

3

1J

4

1S

5

1Q

6

1Q

7

2Q

8

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© 2003, Texas Instruments Incorporated

V

CC

15

1R

14

2R

13

2CP
2K

12

2J

11
10

2S

9

2Q

1

CD54HC112, CD74HC112, CD54HCT112, CD74HCT112

Functional Diagram

1S

4

1K

1CP

1R

2S

2K

2CP

2R

3

1J

2

1

15

10

11

2J

12

13

14

F/F 1

F/F 2

5

1Q

6

1Q

9

2Q

7

2Q

GND = 8

= 16

V

CC

TRUTH TABLE

INPUTS OUTPUTS

S R CP J K Q Q

LHXXXHL
H
L
H
H
HH
HH

L
L
H ↓
H ↓

XXXLH
X X X H (Note 1) H (Note 1)

L L No Change
HLHL

↓
↓

LHLH
H H Toggle

H H H X X No Change

H= High Level (Steady State)
L= Low Level (Steady State)
X= Don’t Care

↓

= High-to-Low Transition

NOTE:

1. Output states unpredictable if both S and R go High simultaneously after both being low at the same time.

2

CD54HC112, CD74HC112, CD54HCT112, CD74HCT112

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time, tr, t

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

2. The package thermal impedance is calculated in accordance with JESD 51-7.

CC

f

Package Thermal Impedance, θJA(see Note 2):

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67oC/W

NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64oC/W

D (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73oC/W

PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W

Maximum Junction Temperature (Hermetic Package or Die) .175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

V

IH

V

IL

V

OH

V

OL

I

I

TEST

CONDITIONS

25oC -40oC TO 85oC -55oC TO 125oC

VCC (V)

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIH or

V

-0.02 2 1.9 - - 1.9 - 1.9 - V

IL

4.5 4.4 - - 4.4 - 4.4 - V
6 5.9 - - 5.9 - 5.9 - V

---------V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIH or

V

0.02 2 - - 0.1 - 0.1 - 0.1 V

IL

4.5 - - 0.1 - 0.1 - 0.1 V
6 - - 0.1 - 0.1 - 0.1 V

---------V

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

3

CD54HC112, CD74HC112, CD54HCT112, CD74HCT112

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Quiescent Device
Current

I

CC

VCC or

GND

VCC (V)

0 6 - - 4 - 40 - 80 µA

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage

V

IH

- - 4.5 to

5.5

V

IL

- - 4.5 to

5.5

V

OH

VIH or

V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

CMOS Loads
High Level Output

-4 4.5 3.98 - - 3.84 - 3.7 - V
Voltage
TTL Loads

Low Level Output
Voltage CMOS Loads

Low Level Output

V

OL

VIH or

V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

4 4.5 - - 0.26 - 0.33 - 0.4 V
Voltage
TTL Loads

Input Leakage
Current

I

I

V

CC

- 5.5 - ±0.1 - ±1-±1 µA

and

GND

Quiescent Device
Current

Additional Quiescent
Device Current Per

I

CC

∆I

CC

(Note 3)

VCC or

GND

V

CC

- 2.1

0 5.5 - - 4 - 40 - 80 µA

- 4.5 to

5.5

Input Pin: 1 Unit Load

NOTE:

3. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

25oC -40oC TO 85oC -55oC TO 125oC

2-- 2 - 2 - V

- - 0.8 - 0.8 - 0.8 V

- 100 360 - 450 - 490 µA

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

1S, 2S 0.5
1K, 2K 0.6
1R, 2R 0.65

1J, 2J, 1CP, 2CP 1

NOTE: Unit Load is ∆ICClimit specified in DC Electrical Specifica­tions table, e.g., 360µA max at 25oC.

Prerequisite For Switching Specifications

TEST

PARAMETER SYMBOL

HC TYPES

Pulse Width CP t

W

CONDITIONS

- 2 80 - - 100 - 120 - ns

V

CC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns

4

CD54HC112, CD74HC112, CD54HCT112, CD74HCT112

Prerequisite For Switching Specifications (Continued)

TEST

PARAMETER SYMBOL

Pulse Width R, St

Setup Time J, K, to CP t

SU

Hold Time J, K, to CP t

Removal Time R to CP, S to CP t

CP Frequency f

REM

MAX

W

H

CONDITIONS

- 2 80 - - 100 - 120 - ns

- 2 80 - - 100 - 120 - ns

-20--0-0-ns

- 2 80 - - 100 - 120 - ns

- 2 6 - - 5 - 4 - MHz

HCT TYPES

Pulse Width CP t
Pulse Width R, St
Setup Time J, K, to CP t
Hold Time J, K, to CP t
Removal Time R to CP, S to CP t
CP Frequency f

SU

W

H

REM

W

MAX

- 4.5 16 - - 20 - 24 - ns

- 4.5 18 - - 23 - 27 - ns

- 4.5 16 - - 20 - 24 - ns

- 4.5 3 - - 3 - 3 - ns

- 4.5 20 - - 25 - 30 - ns

- 4.5 30 - - 25 - 20 - MHz

V

CC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns

4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns

4.5 0 - - 0 - 0 - ns
60--0-0-ns

4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns

4.5 30 - - 25 - 20 - MHz
6 35 - - 29 - 23 - MHz

Switching Specifications Input t

PARAMETER SYMBOL

HC TYPES

Propagation Delay,
CP to Q, Q

Propagation Delay,
S to Q, Q

Propagation Delay,
R to Q, Q

t

PLH

t

PLH

t

PLH

, tf = 6ns

r

25oC -40oC TO 85oC -55oC TO 125oC

, t

PHLCL

TEST

CONDITIONS

V

CC

(V)

= 50pF 2 - - 175 - 220 - 265 ns
CL= 50pF 4.5 - - 35 - 44 - 53 ns
CL= 15pF 5 - 14 - ----ns
CL= 50pF 6 - - 30 - 37 - 45 ns

, t

PHLCL

= 50pF 2 - - 155 - 195 - 235 ns
CL= 50pF 4.5 - - 31 - 39 - 47 ns
CL= 15pF 5 - 13 - ----ns
CL= 50pF 6 - - 26 - 33 - 40 ns

, t

PHLCL

= 50pF 2 - - 180 - 225 - 270 ns
CL= 50pF 4.5 - - 36 - 45 - 54 ns
CL= 15pF 5 - 15 - ----ns
CL= 50pF 6 - - 31 - 38 - 46 ns

UNITSMIN TYP MAX MIN MAX MIN MAX

5

I

CD54HC112, CD74HC112, CD54HCT112, CD74HCT112

Switching Specifications Input t

PARAMETER SYMBOL

Output Transition Time t

, tf = 6ns (Continued)

r

CONDITIONS

TLH

, t

THLCL

= 50pF 2 - - 75 - 95 - 110 ns

TEST

V

CC

(V)

CL= 50pF 4.5 - - 15 - 19 - 22 ns
CL= 50pF 6 - - 13 - 16 - 19 ns

Input Capacitance C
CP Frequency f
Power Dissipation Capacitance

MAX

C

I

PD

- - - - 10 - 10 - 10 pF

CL = 15pF 5 - 60 - ----MHz

- 5-12-----pF

(Notes 4, 5)

HCT TYPES

Propagation Delay,
CP to Q, Q

Propagation Delay,
S to Q, Q

Propagation Delay,
R to Q, Q

Output Transition Time t
Input Capacitance C
CP Frequency f
Power Dissipation Capacitance

t

PLH

t

PLH

t

PLH

TLH

, t

, t

, t

, t

MAX

C

PD

I

PHLCL

= 50pF 4.5 - - 35 - 44 - 53 ns
CL = 15pF 5 - 14 - ----ns

PHLCL

= 50pF 4.5 - - 32 - 40 - 48 ns
CL = 15pF 5 - 13 - ----ns

PHLCL

= 50pF 4.5 - - 37 - 46 - 56 ns
CL = 15pF 5 - 14 - ----ns

THLCL

= 50pF 4.5 - - 15 - 19 - 22 ns

- - - - 10 - 10 - 10 pF

CL = 15pF 5 - 60 - ----MHz

- 5-20-----pF

(Notes 4, 5)

NOTES:

4. CPD is used to determine the dynamic power consumption, per flip-flop.

5. PD = CPD V

2

fi + Σ CLfowhere fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage.

CC

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

Test Circuits and Waveforms

trC

L

CLOCK

10%

90%

50%

10%

tfC

t

L

WL

tWL+ tWH=

50%

t

WH

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For f

, input duty cycle = 50%.

MAX

FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

f

CL

50%

I

V

CC

GND

+ tWH=

t

t

WH

WL

1.3V

fC

L

3V

GND

trCL= 6ns

CLOCK

0.3V

2.7V

1.3V

0.3V

t

t

fCL

WL

= 6ns

1.3V

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For f

, input duty cycle = 50%.

MAX

FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

6