TEXAS INSTRUMENTS CD54HC109 Technical data

Data sheet acquired from Harris Semiconductor

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SCHS140E

March 1998 - Revised October 2003

CD54HC109, CD74HC109,

CD54HCT109, CD74HCT109

Dual J-K Flip-Flop with Set and Reset

Positive-Edge Trigger

/Title
CD74H

109,
D74H

T109)
Subject
Dual J-

Flip-

lop

ith Set

nd

eset

Features

• Asynchronous Set and Reset

• Schmitt Trigger Clock Inputs

• Typical f
T

= 25oC

A

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 54MHz at VCC = 5V, CL = 15pF,

MAX

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

o

C to 125oC

OH

Pinout

CD54HC109, CD54HCT109

(CERDIP)

CD74HC109, CD74HCT109

(PDIP, SOIC)

TOP VIEW

Description

The ’HC109 and ’HCT109 are dual J-K flip-flops with set and
reset. The flip-flop changes state with the positive transition
of Clock (1CP and 2CP).

The flip-flop is set and reset by active-low
respectively. A low on both the set and reset inputs
simultaneously will force both Q and
However, both set and reset going high simultaneously
results in an unpredictable output condition.

Q outputs high.

Ordering Information

TEMP. RANGE

PART NUMBER

CD54HC109F3A -55 to 125 16 Ld CERDIP
CD54HCT109F3A -55 to 125 16 Ld CERDIP
CD74HC109E -55 to 125 16 Ld PDIP

CC

CD74HC109M -55 to 125 16 Ld SOIC
CD74HC109MT -55 to 125 16 Ld SOIC
CD74HC109M96 -55 to 125 16 Ld SOIC
CD74HCT109E -55 to 125 16 Ld PDIP
CD74HCT109M -55 to 125 16 Ld SOIC
CD74HCT109MT -55 to 125 16 Ld SOIC
CD74HCT109M96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of

250.

(oC) PACKAGE

S and R,

16

1

1R

2

1J

3

1K

4

1CP

5

1S

6

1Q

7

1Q

8

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© 2003, Texas Instruments Incorporated

V

CC

15

2R

14

2J

13

2K
2CP

12
11

2S

10

2Q

9

2Q

1

CD54HC109, CD74HC109, CD54HCT109, CD74HCT109

Functional Diagram

1S

5

1K

1CP

1R

2S

2K

2CP

2R

2

1J

3

4
1

11

14

2J

13

12

15

F/F 1

F/F 2

6

1Q

7

1

Q

10

2Q

9

Q

2

GND = 8
V

= 16

CC

TRUTH TABLE

INPUTS OUTPUTS

S RCPJ KQQ

LHXXXHL
H
L
H
H

L
L
H
H

XXXLH
X X X H (Note 1) H (Note 1)

↑ LLLH
↑ H L Toggle

HH↑ L H No Change
HH↑ HHHL
H H L X X No Change

H= High Level (Steady State)
L= Low Level (Steady State)
X= Don’t Care

↑= Low-to-High Transition

NOTE:

1. Unpredictable and unstable condition if both S and R go high simultaneously

Logic Diagram

CP

V

CC

GND

5(11)
S

2(14)
J

3(13)
K

4(12)

1(15)
R

16

S

J

FF

K

CL

CL R

8

Q

Q

6(10)

Q

7(9)

Q

2

CD54HC109, CD74HC109, CD54HCT109, CD74HCT109

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

CP Input Rise and Fall Time, tr, t

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max)

Input Rise and Fall Time (All Inputs Except CP), tr, t

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

2. The package thermal impedance is calculated in accordance with JESD 51-7

CC

f

f

Thermal Resistance (Typical, Note 2) θJA (oC/W)

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73

Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

V

IH

V

IL

V

OH

TEST

CONDITIONS

25oC -40oC TO 85oC -55oC TO 125oC

VCC (V)

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIH or

V

-0.02 2 1.9 - - 1.9 - 1.9 - V

IL

4.5 4.4 - - 4.4 - 4.4 - V
6 5.9 - - 5.9 - 5.9 - V

---------V

-4 4.5 3.96 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

3

CD54HC109, CD74HC109, CD54HCT109, CD74HCT109

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Low Level Output
Voltage
CMOS Loads

V

OL

VIH or

V

IL

VCC (V)

0.02 2 - - 0.1 - 0.1 - 0.1 V

4.5 - - 0.1 - 0.1 - 0.1 V
6 - - 0.1 - 0.1 - 0.1 V

Low Level Output
Voltage
TTL Loads

---------V

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

Input Leakage
Current

Quiescent Device
Current

I

I

CC

VCC or

I

-6--±0.1 - ±1-±1 µA

GND

VCC or

0 6 - - 4 - 40 - 80 µA

GND

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage

V

IH

- - 4.5 to

5.5

V

IL

- - 4.5 to

5.5

V

OH

VIH or

V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

CMOS Loads
High Level Output

-4 4.5 3.98 - - 3.84 - 3.7 - V
Voltage
TTL Loads

Low Level Output
Voltage CMOS Loads

Low Level Output

V

OL

VIH or

V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

4 4.5 - - 0.26 - 0.33 - 0.4 V
Voltage
TTL Loads

Input Leakage
Current

I

I

V

CC

- 5.5 - ±0.1 - ±1-±1 µA

and

GND

Quiescent Device
Current

Additional Quiescent
Device Current Per

I

CC

∆I

CC

(Note 3)

VCC or

GND

V

CC

- 2.1

0 5.5 - - 4 - 40 - 80 µA

- 4.5 to

5.5

Input Pin: 1 Unit Load

NOTE:

3. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

25oC -40oC TO 85oC -55oC TO 125oC

2-- 2 - 2 - V

- - 0.8 - 0.8 - 0.8 V

- 100 360 - 450 - 490 µA

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

All 0.3

NOTE: Unit Load is ∆ICClimit specified in DC Electrical Specifica­tions table, e.g., 360µA max at 25oC.

4

CD54HC109, CD74HC109, CD54HCT109, CD74HCT109

Prerequisite For Switching Specifications

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

PARAMETER SYMBOL

TEST

CONDITIONS

V

CC

(V)

HC TYPES

Setup Time J, K, to CP t

SU

- 2 80 - - 100 - 120 - ns

4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns

Hold Time J, K, to CP t

H

-25--5-5-ns

4.5 5 - - 5 - 5 - ns
65--5-5-ns

Removal Time R, S, to CP t

REM

- 2 80 - - 100 - 120 - ns

4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns

Pulse Width CP, R, StW- 2 80 - - 100 - 120 - ns

4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns

CP Frequency f

MAX

- 2 6 - - 5 - 4 - MHz

4.5 30 - - 25 - 20 - MHz
6 35 - - 29 - 23 - MHz

HCT TYPES

Setup Time J, K to CP t
Hold Time J, K to CP t
Removal Time R, S, to CP t

SU

H

REM

- 4.5 18 - - 23 - 27 - ns

- 4.5 3 - - 3 - 3 - ns

- 4.5 18 - - 23 - 27 - ns
Pulse Width CP, R, StW- 4.5 18 - - 23 - 27 - ns
CP Frequency f

MAX

- 4.5 27 - - 22 - 18 - MHz

Switching Specifications Input t

PARAMETER SYMBOL

HC TYPES

Propagation Delay,
CP → Q, Q

Propagation Delay,
S → Q

Propagation Delay,
S → Q

t

PLH

t

PLH

t

PLH

, tf = 6ns

r

25oC -40oC TO 85oC -55oC TO 125oC

, t

PHLCL

TEST

CONDITIONS

V

CC

(V)

= 50pF 2 - - 175 - 220 - 265 ns
CL= 50pF 4.5 - - 35 - 44 - 53 ns
CL= 15pF 5 - 14 - ----ns
CL= 50pF 6 - - 30 - 37 - 45 ns

, t

PHLCL

= 50pF 2 - - 120 - 150 - 180 ns
CL= 50pF 4.5 - - 24 - 30 - 36 ns
CL= 15pF 5 - 9 - ----ns
CL= 50pF 6 - - 20 - 26 - 31 ns

, t

PHLCL

= 50pF 2 - - 155 - 195 - 235 ns
CL= 50pF 4.5 - - 31 - 39 - 47 ns
CL= 15pF 5 - 13 - ----ns
CL= 50pF 6 - - 26 - 33 - 40 ns

UNITSMIN TYP MAX MIN MAX MIN MAX

5

CD54HC109, CD74HC109, CD54HCT109, CD74HCT109

Switching Specifications Input t

PARAMETER SYMBOL

Propagation Delay,
R → Q

, tf = 6ns (Continued)

r

CONDITIONS

t

, t

PLH

PHLCL

CL= 50pF 4.5 - - 37 - 46 - 56 ns

TEST

V

CC

(V)

= 50pF 2 - - 185 - 230 - 280 ns

CL= 15pF 5 - 15 - ----ns
CL= 50pF 6 - - 31 - 39 - 48 ns

Propagation Delay,
R → Q

t

PLH

, t

PHLCL

= 50pF 2 - - 170 - 215 - 255 ns
CL= 50pF 4.5 - - 34 - 43 - 51 ns
CL= 15pF 5 - 14 - ----ns
CL= 50pF 6 - - 29 - 37 - 43 ns

Transition Time t

TLH

, t

THLCL

= 50pF 2 - - 75 - 95 - 110 ns
CL= 50pF 4.5 - - 15 - 19 - 22 ns
CL= 50pF 6 - - 13 - 16 - 19 ns

Input Capacitance C
CP Frequency f
Power Dissipation Capacitance

MAX

C

I

PD

- - - - 10 - 10 - 10 pF

CL = 15pF 5 - 60 - ----MHz

- 5-30-----pF

(Notes 4, 5)

HCT TYPES

Propagation Delay,
CP → Q, Q

Propagation Delay,
S → Q

Propagation Delay,
S → Q

Propagation Delay,
R → Q

Propagation Delay,
R → Q

Transition Time (Figure 5) t
Input Capacitance C
CP Frequency f
Power Dissipation Capacitance

t

PLH

t

PLH

t

PLH

t

PLH

t

PLH

TLH

, t

, t

, t

, t

, t

, t

MAX

C

PD

I

PHLCL

= 50pF 4.5 - - 40 - 50 - 60 ns
CL = 15pF 5 - 17 - ----ns

PHLCL

= 50pF 4.5 - - 30 - 38 - 45 ns
CL = 15pF 5 - 12 - ----ns

PHLCL

= 50pF 4.5 - - 45 - 56 - 68 ns
CL = 15pF 5 - 19 - ----ns

PHLCL

= 50pF 4.5 - - 45 - 56 - 68 ns
CL = 15pF 5 - 19 - ----ns

PHLCL

= 50pF 4.5 - - 37 - 46 - 56 ns
CL = 15pF 5 - 15 - ----ns

THLCL

= 50pF 4.5 - - 15 - 19 - 22 ns

- - - - 10 - 10 - 10 pF

CL = 15pF 5 - 54 - ----MHz

- 5-33-----pF

(Notes 4, 5)

NOTES:

4. CPD is used to determine the dynamic power consumption, per flip-flop.

5. PD = CPD V

2

fi + Σ CLfowhere fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage.

CC

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

6

I

CD54HC109, CD74HC109, CD54HCT109, CD74HCT109

Test Circuits and Waveforms

trC

L

CLOCK

10%

90%

50%

10%

tfC

t

L

WL

tWL+ tWH=

50%

t

WH

f

CL

50%

+ tWH=

t

t

WH

WL

1.3V

fC

L

3V

GND

I

V

CC

GND

trCL= 6ns

CLOCK

0.3V

2.7V

1.3V

0.3V

t

t

fCL

WL

= 6ns

1.3V

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For f

, input duty cycle = 50%.

MAX

FIGURE 7. HC CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

tr = 6ns tf = 6ns

V

t

CC

GND

TLH

INPUT

t

90%
50%
10%

THL

90%

t

50%

10%

PLH

INVERTING

OUTPUT

t

PHL

FIGURE 9. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

tfC

L

V

CC

50%

GND

t

H(L)

V

CC

50%

t

SU(L)

GND

CLOCK

INPUT

DAT A

INPUT

t

SU(H)

trC

L

90%

10%

t

H(H)

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For f

, input duty cycle = 50%.

MAX

FIGURE 8. HCT CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

= 6ns

tr = 6ns

INPUT

t

2.7V

1.3V

0.3V

THL

t

f

3V

GND

t

TLH

90%

t

PLH

1.3V

10%

INVERTING

OUTPUT

t

PHL

FIGURE 10. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

CLOCK

INPUT

DAT A

INPUT

t

SU(H)

trC

L

2.7V

0.3V

t

H(H)

1.3V

1.3V

tfC

L

3V

1.3V
GND

t

H(L)

3V

1.3V

t

SU(L)

GND

OUTPUT

t

REM

V

CC

SET, RESET
OR PRESET

50%

90%

t

PLH

IC

t

TLH

t

THL

90%

50%

10%
t

PHL

GND

C

L

50pF

FIGURE 11. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS

OUTPUT

t

REM

3V

SET, RESET

1.3V

90%

1.3V
t

t

PLH

TLH

90%

1.3V
10%

t

t

PHL

THL

OR PRESET

IC

C

L

50pF

FIGURE 12. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS

7

GND

PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device Status

5962-9070101MEA ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type

CD54HC109F3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type

CD54HCT109F3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type

CD74HC109E ACTIVE PDIP N 16 25 Pb-Free

CD74HC109EE4 ACTIVE PDIP N 16 25 Pb-Free

CD74HC109M ACTIVE SOIC D 16 40 Green (RoHS &

CD74HC109M96 ACTIVE SOIC D 16 2500 Green (RoHS &

CD74HC109M96E4 ACTIVE SOIC D 16 2500 Green (RoHS &

CD74HC109M96G4 ACTIVE SOIC D 16 2500 Green (RoHS &

CD74HC109ME4 ACTIVE SOIC D 16 40 Green (RoHS &

CD74HC109MG4 ACTIVE SOIC D 16 40 Green (RoHS &

CD74HC109MT ACTIVE SOIC D 16 250 Green (RoHS &

CD74HC109MTE4 ACTIVE SOIC D 16 250 Green (RoHS &

CD74HC109MTG4 ACTIVE SOIC D 16 250 Green (RoHS &

CD74HCT109E ACTIVE PDIP N 16 25 Pb-Free

CD74HCT109EE4 ACTIVE PDIP N 16 25 Pb-Free

CD74HCT109M ACTIVE SOIC D 16 40 Green(RoHS &

CD74HCT109M96 ACTIVE SOIC D 16 2500 Green (RoHS &

CD74HCT109M96E4 ACTIVE SOIC D 16 2500 Green (RoHS &

CD74HCT109M96G4 ACTIVE SOIC D 16 2500 Green (RoHS &

CD74HCT109ME4 ACTIVE SOIC D 16 40 Green (RoHS &

CD74HCT109MG4 ACTIVE SOIC D 16 40 Green (RoHS &

CD74HCT109MT ACTIVE SOIC D 16 250 Green (RoHS &

CD74HCT109MTE4 ACTIVE SOIC D 16 250 Green (RoHS &

CD74HCT109MTG4 ACTIVE SOIC D 16 250 Green (RoHS &

(1)

The marketing status values are defined as follows:

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU N / A for Pkg Type

CU NIPDAU N / A for Pkg Type

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU N / A for Pkg Type

CU NIPDAU N / A for Pkg Type

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

9-Oct-2007

(3)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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information may not be available for release.

9-Oct-2007

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

TAPE AND REEL INFORMATION

19-Mar-2008

*All dimensions are nominal

Device Package

CD74HC109M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

CD74HCT109M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

Type

Package
Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

19-Mar-2008

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

CD74HC109M96 SOIC D 16 2500 333.2 345.9 28.6

CD74HCT109M96 SOIC D 16 2500 333.2 345.9 28.6

Pack Materials-Page 2

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