TEXAS INSTRUMENTS CD54HC107 Technical data

Data sheet acquired from Harris Semiconductor

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SCHS139D

March 1998 - Revised October 2003

CD54HC107, CD74HC107,

CD74HCT107

Dual J-K Flip-Flop with Reset

Negative-Edge Trigger

/Title
CD74

C107

D74
CT10

)
Sub­ect
Dual

-K
lip­lop

ith
eset
ega-

ive-

Features

• Hysteresis on Clock Inputs for Improved Noise Immu­nity and Increased Input Rise and Fall Times

• Asynchronous Reset

• Complementary Outputs

• Buffered Inputs

• Typical f
T

= 25oC

A

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), VIH = 2V (Min)

V

IL

- CMOS Input Compatibility, I

= 60MHz at VCC = 5V, CL = 15pF,

MAX

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

o

C to 125oC

OH

CC

Description

The ’HC107 and CD74HCT107 utilize silicon gate CMOS
technology to achieveoperating speeds equivalent to LSTTL
parts. They exhibit the low power consumption of standard
CMOS integrated circuits, together with the ability to drive 10
LSTTL loads.

These flip-flops have independent J, K, Reset and Clock
inputs and Q and
negative-going transition of the clock pulse. Reset is
accomplished asynchronously by a low level input.

This device is functionally identical to the HC/HCT73 but
differs in terminal assignment and in some parametric limits.

The HCT logic family is functionally as well as pin compatible
with the standard LS family.

Q outputs. They change state on the

Ordering Information

TEMP. RANGE

PART NUMBER

CD54HC107F3A -55 to 125 14 Ld CERDIP
CD74HC107E -55 to 125 14 Ld PDIP
CD74HC107M -55 to 125 14 Ld SOIC
CD74HC107MT -55 to 125 14 Ld SOIC
CD74HC107M96 -55 to 125 14 Ld SOIC
CD74HCT107E -55 to 125 14 Ld PDIP

NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of

250.

(oC) PACKAGE

Pinout

CD54HC107 (CERDIP)

CD74HC107 (PDIP, SOIC)

CD74HCT107 (PDIP)

TOP VIEW

1J

1

1Q

2
3

1Q
1K

4

2Q

5

2Q

6

GND

7

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© 2003, Texas Instruments Incorporated

14

V

CC

1R

13

1CP

12

2K

11

2R

10

2CP

9
8

2J

1

Functional Diagram

CD54HC107, CD74HC107, CD74HCT107

R CP J K Q Q

LXXXLH

H
H

H
H
H H X X No Change

H= High Level (Steady State)
L= Low Level (Steady State)
X= Irrelevant

↓

= High-to-Low Transition

1K

1CP

1

2K

2CP

2R

1

1J

4

12

13

R

8

2J

11

9

10

FF 1

FF 2

3

1Q

2

Q

1

5

2Q

6

2

Q

GND = 7

= 14

V

CC

TRUTH TABLE

INPUTS OUTPUTS

↓
↓
↓
↓

L L No Change

HLHL

LHLH

H H Toggle

Logic Diagram

CP

R

12 (9)

13 (10)

nA

1 (8)

J

4(11)

K

J
K
CL
CL

R

3 (5)

Q

2 (6)

Q

2

CD54HC107, CD74HC107, CD74HCT107

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

CC

Thermal Resistance (Typical, Note 1) θJA (oC/W)

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 80

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 86

Maximum Junction Temperature (Hermetic P ac kage or Die) . . . 175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

V

IH

V

IL

V

OH

V

OL

I

I

TEST

CONDITIONS

25oC -40oC TO 85oC -55oC TO 125oC

VCC (V)

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIH or

V

-0.02 2 1.9 - - 1.9 - 1.9 - V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

---------V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIH or

V

0.02 2 - - 0.1 - 0.1 - 0.1 V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

---------V

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

3

CD54HC107, CD74HC107, CD74HCT107

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Quiescent Device
Current

I

CC

VCC or

GND

VCC (V)

0 6 - - 4 - 40 - 80 µA

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage

V

IH

- - 4.5 to

5.5

V

IL

- - 4.5 to

5.5

V

OH

VIH or

V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

CMOS Load
High Level Output

-4 4.5 3.98 - - 3.84 - 3.7 - V
Voltage
TTL Loads

Low Level Output
Voltage CMOS Loads

Low Level Output

V

OL

VIH or

V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

4 4.5 - - 0.26 - 0.33 - 0.4 V
Voltage
TTL Loads

Input Leakage
Current

I

I

V

CC

- 5.5 - ±0.1 - ±1-±1 µA

and

GND

Quiescent Device
Current

Additional Quiescent
Device Current Per

I

CC

∆I

CC

(Note 2)

VCC or

GND

V

CC

- 2.1

0 5.5 - - 4 - 40 - 80 µA

- 4.5 to

5.5

Input Pin: 1 Unit Load

NOTE:

2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

25oC -40oC TO 85oC -55oC TO 125oC

2-- 2 - 2 - V

- - 0.8 - 0.8 - 0.8 V

- 100 360 - 450 - 490 µA

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

All 0.3

NOTE: Unit Load is ∆ICClimit specified in DC Electrical Specifica­tions table, e.g., 360µA max at 25oC.

Prerequisite For Switching Specifications

TEST

PARAMETER SYMBOL

HC TYPES

CP Pulse Width t

R Pulse Width t

w

w

CONDITIONS

- 2 80 - - 100 - 120 - ns

- 2 80 - - 100 - 120 - ns

V

CC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns

4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns

4

CD54HC107, CD74HC107, CD74HCT107

Prerequisite For Switching Specifications (Continued)

PARAMETER SYMBOL

Setup Time, J, K to CP t

Hold Time, J, K to CP t

Removal Time t

CP Frequency f

HCT TYPES

CP Pulse Width t
R Pulse Width t
Setup Time, J, K to CP t
Hold Time, J, K to CP t
Removal Time t
CP Frequency f

SU

H

REM

MAX

w
w

SU

H
REM
MAX

TEST

CONDITIONS

- 2 100 - - 125 - 150 - ns

-23--3-3-ns

- 2 60 - - 75 - 90 - ns

- 2 6 - - 5 - 4 - MHz

- 4.5 18 - - 23 - 27 - ns

- 4.5 24 - - 30 - 36 - ns

- 4.5 20 - - 25 - 30 - ns

- 4.5 5 - - 5 - 5 - ns

- 4.5 12 - - 15 - 18 - ns

- 4.5 28 - - 22 - 19 - MHz

V

CC

(V)

4.5 20 - - 25 - 30 - ns
6 17 - - 21 - 26 - ns

4.5 3 - - 3 - 3 - ns
63--3-3-ns

4.5 12 - - 15 - 18 - ns
6 10 - - 13 - 15 - ns

4.5 30 - - 25 - 20 - MHz
6 35 - - 29 - 23 - MHz

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

Switching Specifications Input t

PARAMETER SYMBOL

HC TYPES

Propagation Delay,
CP to Q

Propagation Delay,
CP to Q

Propagation Delay,
R to Q, Q

Output Transition Time t

Input Capacitance C
CP Frequency f

t

PLH

t

PLH

t

PLH

TLH

, tf = 6ns

r

, t

PHL

, t

PHL

, t

PHL

, t

THL

I

MAX

TEST

CONDITIONS

V

CC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

CL= 50pF 2 - - 170 - 215 - 255 ns

4.5 - - 34 - 43 - 51 ns

CL= 15pF 5 - 14 - ----ns
CL= 50pF 6 - - 29 - 37 - 43 ns
CL= 50pF 2 - - 170 - 215 - 255 ns

4.5 - - 34 - 43 - 51 ns

CL= 15pF 5 - 14 - ----ns
CL= 50pF 6 - - 29 - 37 - 43 ns
CL= 50pF 2 - - 155 - 195 - 235 ns

4.5 - - 31 - 39 - 47 ns

CL= 15pF 5 - 13 - ----ns
CL= 50pF 6 - - 26 - 33 - 40 ns
CL= 50pF 2 - - 75 - 95 18 110 ns

4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns

- - - - 10 - 10 - 10 pF

CL= 15pF 5 - 60 - ----MHz

5

I

CD54HC107, CD74HC107, CD74HCT107

Switching Specifications Input t

PARAMETER SYMBOL

Power Dissipation Capacitance

, tf = 6ns (Continued)

r

TEST

CONDITIONS

C

PD

- 5-31-----pF

V

CC

(V)

(Notes 3, 4)

HCT TYPES

Propagation Delay,
CP to Q

Propagation Delay,
CP to Q

Propagation Delay,
R to Q, Q

Output Transition Time t
Input Capacitance C
CP Frequency f
Power Dissipation Capacitance

t

PLH

t

PLH

t

PLH

TLH

, t

, t

, t

, t

MAX

C

PD

PHL

PHL

PHL

THL

I

CL= 50pF 4.5 - - 43 - 54 - 65 ns
CL= 15pF 5 - 18 - ----ns
CL = 50pF 4.5 - - 40 - 50 - 60 ns
CL= 15pF 5 - 17 - ----ns
CL = 50pF 4.5 - - 38 - 48 - 57 ns
CL= 15pF 5 - 16 - ----ns
CL= 50pF 4.5 - - 15 - 19 - 22 ns

- - - - 10 - 10 - 10 pF

CL= 15pF 5 - 56 - ----MHz

- 5-30-----pF

(Notes 3, 4)

NOTES:

3. CPD is used to determine the dynamic power consumption, per flip-flop.

4. PD=CPDV

CC

2

fi+ Σ CLV

2

fowhere fi= input frequency, fo= output frequency, CL= output load capacitance, VCC= supply voltage.

CC

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

Test Circuits and Waveforms

t

TLH

f

CL

50%

V

CC

GND

I

V

CC

GND

trC

L

CLOCK

10%

90%

50%

10%

tfC

t

L

WL

tWL+ tWH=

50%

t

WH

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For f

, input duty cycle = 50%.

MAX

FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

tr = 6ns tf = 6ns

t

PHL

90%
50%
10%

t

PLH

90%

50%

10%

INPUT

t

INVERTING

OUTPUT

THL

+ tWH=

t

t

WH

WL

1.3V

fC

L

3V

GND

trCL= 6ns

CLOCK

0.3V

2.7V

1.3V

0.3V

t

t

fCL

WL

= 6ns

1.3V

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For f

, input duty cycle = 50%.

MAX

FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

= 6ns

t

PLH

t

f

1.3V

10%

90%

t

3V

GND

TLH

tr = 6ns

INPUT

t

INVERTING

OUTPUT

THL

t

PHL

2.7V

1.3V

0.3V

FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

6

CD54HC107, CD74HC107, CD74HCT107

Test Circuits and Waveforms (Continued)

90%

t

PLH

IC

t

TLH

tfC

L

V

CC

50%

GND

t

H(L)

V

CC

50%

t

SU(L)

90%

t

THL

GND

50%

10%
t

PHL

GND

C

L

CLOCK

INPUT

DAT A

INPUT

t

SU(H)

OUTPUT

t

REM

V

CC

SET, RESET
OR PRESET

trC

L

90%

10%

t

H(H)

50%

50pF

FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS

CLOCK

INPUT

DAT A

INPUT

t

SU(H)

OUTPUT

t

REM

3V
SET, RESET
OR PRESET

trC

L

2.7V

0.3V

t

H(H)

1.3V

1.3V

1.3V

90%

t

PLH

IC

1.3V

t

TLH

tfC

L

3V

1.3V
GND

t

H(L)

3V

1.3V

t

SU(L)

90%

1.3V
10%

t

t

PHL

THL

GND

GND

C

L

50pF

FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVALTIME,

AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS

7

PACKAGE OPTION ADDENDUM

www.ti.com

9-Oct-2007

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

5962-8515401CA ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type

9084901MCA OBSOLETE CDIP J 14 TBD Call TI Call TI

CD54HC107F3A ACTIVE CDIP J 14 1 TBD A42SNPB N / A for Pkg Type

CD74HC107E ACTIVE PDIP N 14 25 Pb-Free

CD74HC107EE4 ACTIVE PDIP N 14 25 Pb-Free

CD74HC107M ACTIVE SOIC D 14 50 Green (RoHS &

no Sb/Br)

CD74HC107M96 ACTIVE SOIC D 14 2500 Green (RoHS &

no Sb/Br)

CD74HC107M96E4 ACTIVE SOIC D 14 2500 Green (RoHS &

no Sb/Br)

CD74HC107M96G4 ACTIVE SOIC D 14 2500 Green (RoHS &

no Sb/Br)

CD74HC107ME4 ACTIVE SOIC D 14 50 Green (RoHS &

no Sb/Br)

CD74HC107MG4 ACTIVE SOIC D 14 50 Green (RoHS &

no Sb/Br)

CD74HC107MT ACTIVE SOIC D 14 250 Green (RoHS &

no Sb/Br)

CD74HC107MTE4 ACTIVE SOIC D 14 250 Green (RoHS &

no Sb/Br)

CD74HC107MTG4 ACTIVE SOIC D 14 250 Green (RoHS &

no Sb/Br)

CD74HCT107E ACTIVE PDIP N 14 25 Pb-Free

CD74HCT107EE4 ACTIVE PDIP N 14 25 Pb-Free

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU N / A for Pkg Type

CU NIPDAU N / A for Pkg Type

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU N / A for Pkg Type

CU NIPDAU N / A for Pkg Type

(3)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

9-Oct-2007

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

TAPE AND REEL INFORMATION

11-Mar-2008

*All dimensions are nominal

Device Package

Type

CD74HC107M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

Package
Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Mar-2008

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

CD74HC107M96 SOIC D 14 2500 346.0 346.0 33.0

Pack Materials-Page 2

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