Texas Instruments CD74HCT00M96, CD74HCT00M, CD74HCT00E, CD74HC00E, CD74HC00M96 Datasheet

CD54HC00, CD54HCT00,

/

[ /Title
(CD54
HC00,
CD54
HCT00
,
CD74
HC00,
CD74
HCT00
)

Sub-

Data sheet acquired from Harris Semiconductor
SCHS116

January 1998

Features

• Buffered Inputs

• Typical Propagation Delay: 7ns at V
C

= 15pF, TA = 25oC

L

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• Alternate Source is Philips/Signetics

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

• Related Literature

- CD54HC00F3A and CD54HCT00F3A Military

Data Sheet, Document Number 3753

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

CC

= 5V,

o

C to 125oC

CC

OH

CD74HC00, CD74HCT00

High Speed CMOS Logic

Quad 2-Input NAND Gate

Description

The Harris CD54HC00, CD54HCT00, CD74HC00 and
CD74HCT00 logic gates utilize silicon gate CMOS
technology to achieve operating speeds similar to LSTTL
gates with the low power consumption of standard CMOS
integrated circuits. All devices have the ability to drive 10
LSTTL loads. The 74HCT logic family is functionally pin
compatible with the standard 74LS logic family.

Ordering Information

TEMP.RANGE

PART NUMBER

CD74HC00E -55 to 125 14 Ld PDIP E14.3
CD74HCT00E -55 to 125 14 Ld PDIP E14.3
CD74HC00M -55 to 125 14 Ld SOIC M14.15
CD74HCT00M -55 to 125 14 Ld SOIC M14.15
CD54HC00F -55 to 125 14 Ld CERDIP F14.3
CD54HCT00F -55 to 125 14 Ld CERDIP F14.3
CD54HC00W -55 to 125 Wafer
CD54HCT00W -55 to 125 Wafer
CD54HC00H -55 to 125 Die
CD54HCT00H -55 to 125 Die

NOTE: When ordering, usethe entire partnumber.Add the suffix 96
to obtain the variant in the tape and reel.

(oC) PACKAGE

PKG.

NO.

Pinout

CD54HC00, CD54HCT00, CD74HC00, CD74HCT00

(PDIP, CERDIP, SOIC)

TOP VIEW

1A

1
2

1B

1Y

3

2A

4

2B

5

2Y

6

GND

7

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1998

1

V

14

CC

4B

13

4A

12

4Y

11

3B

10

3A

9

3Y

8

File Number 1464.2

Functional Diagram

CD54HC00, CD54HCT00, CD74HC00, CD74HCT00

1A

1B

1Y

2A

2B

2Y

GND

1

2

3

4

5

6

7

14

V

CC

13

4B

12

4A

11

4Y

10

3B

9

3A

8

3Y

TRUTH TABLE

INPUTS OUTPUT

nA nB nY

LLH
LHH
HLH

Logic Symbol

HHL

nA

nY

nB

2

CD54HC00, CD54HCT00, CD74HC00, CD74HCT00

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, I

CC orIGND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . 100 N/A

CERDIP Package . . . . . . . . . . . . . . . .

SOIC Package. . . . . . . . . . . . . . . . . . . 180 N/A

Maximum Junction Temperature (Hermetic Pac kage or Die) . . .175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

V

IH

V

IL

V

OH

V

OL

I

I

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

VCC (V)

o

25

C -40oC TO 85oC -55oC TO 125oC

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIH or

V

-0.02 2 1.9 - - 1.9 - 1.9 - V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

---------V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIH or

V

0.02 2 - - 0.1 - 0.1 - 0.1 V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

---------V

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1µA

GND

UNITSV

3

CD54HC00, CD54HCT00, CD74HC00, CD74HCT00

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Quiescent Device
Current

I

CC

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

VCC or

GND

HCT TYPES

High Level Input

V

IH

- - 4.5 to

Voltage
Low Level Input

V

IL

- - 4.5 to

Voltage
High Level Output

Voltage

V

OH

VIH or

V

IL

CMOS Loads
High Level Output

-0.02 4.5 3.98 - - 3.84 - 3.7 - V
Voltage
TTL Loads

Low Level Output
Voltage CMOS Loads

Low Level Output

V

OL

VIH or

V

IL

0.02 4.5 - - 0.26 - 0.33 - 0.4 V
Voltage
TTL Loads

Input Leakage
Current

I

I

V

CC

and

GND

Quiescent Device
Current

Additional Quiescent
Device Current Per

I

CC

VCC or

GND

∆I

CC

V

CC

- 2.1

Input Pin: 1 Unit Load

NOTE:

2. For dual-supply systems theorectical worst case (V

o

25

C -40oC TO 85oC -55oC TO 125oC

V

CC

(V)

UNITSV

0 6 - - 2 - 20 - 40 µA

2-- 2 - 2 - V

5.5

- - 0.8 - 0.8 - 0.8 V

5.5

- 4.5 4.4 - - 4.4 - 4.4 - V

-4 4.5 - - 0.1 - 0.1 - 0.1 V

4 5.5 - ±0.1 - ±1-±1µA

0 5.5 - - 2 - 20 - 40 µA

- 4.5 to

- 100 360 - 450 - 490 µA

5.5

= 2.4V, VCC = 5.5V) specification is 1.8mA.

I

HCT Input Loading Table

INPUT UNIT LOADS

nA 1.8
nB 1.1

NOTE: Unit Load is ∆I

limit specified in DC Electrical Specifica-

CC

tions table, e.g. 360µA max at 25oC.

Switching Specifications Input t

PARAMETER SYMBOL

HC TYPES

Propagation Delay,
Input to Output (Figure 1)

PropagationDelay,DataInputto
Output Y

t

PLH

t

PLH

, tf = 6ns

r

, t

PHLCL

, t

PHLCL

o

C -40oC TO 85oC -55oCTO125oC

TEST

CONDITIONS

V

CC

(V)

25

UNITSMIN TYP MAX MIN MAX MIN MAX

= 50pF 2 - - 90 - 115 - 135 ns

4.5 - - 18 - 23 - 27 ns
6 - - 15 - 20 - 23 ns

= 15pF 5 - 7 - ----pF

4

CD54HC00, CD54HCT00, CD74HC00, CD74HCT00

Switching Specifications Input t

PARAMETER SYMBOL

Transition Times (Figure 1) t

Input Capacitance C
Power Dissipation Capacitance

(Notes 3, 4)

HCT TYPES

Propagation Delay, Input to
Output (Figure 2)

PropagationDelay,DataInputto
Output Y

Transition Times (Figure 2) t
Input Capacitance C
Power Dissipation Capacitance

(Notes 3, 4)

NOTES:

3. C

is used to determine the dynamic power consumption, per gate.

PD

4. PD = V

2

fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

CC

TLH

t

PLH

t

PLH

TLH

, tf = 6ns (Continued)

r

TEST

CONDITIONS

, t

I

C

PD

, t

, t

, t

I

C

PD

THLCL

PHLCL

PHLCL

THLCL

= 50pF 2 - - 75 - 95 18 110 ns

- - - - 10 - 10 - 10 pF

- 5-25-----pF

= 50pF 4.5 - - 20 - 25 - 30 ns

= 15pF 5 - 8 - ----pF

= 50pF 4.5 - - 15 - 19 - 22 ns

- - - - 10 - 10 - 10 pF

- 5-25-----pF

o

25

V

CC

(V)

C -40oC TO 85oC -55oCTO125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns

Test Circuits and Waveforms

tr = 6ns tf = 6ns

V

t

CC

GND

TLH

3V

1.3V

t

PHL

90%
50%
10%

t

90%

50%

10%

PLH

INPUT

t

INVERTING

OUTPUT

THL

FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

INPUT LEVEL HC TYPES HCT TYPES

V

CC

V

S

50% V

CC

NOTE: Transition times and propagation delay times.

= 6ns

t

PLH

t

f

1.3V

10%

90%

t

3V

GND

TLH

tr = 6ns

INPUT

t

INVERTING

OUTPUT

THL

t

2.7V

1.3V

0.3V

PHL

FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

5

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