Texas Instruments CD74HCT00M96, CD74HCT00M, CD74HCT00E, CD74HC00E, CD74HC00M96 Datasheet

CD54HC00, CD54HCT00,

/

[ /Title
(CD54
HC00,
CD54
HCT00
,
CD74
HC00,
CD74
HCT00
)

Sub-

Data sheet acquired from Harris Semiconductor
SCHS116

January 1998

Features

• Buffered Inputs

• Typical Propagation Delay: 7ns at V
C

= 15pF, TA = 25oC

L

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• Alternate Source is Philips/Signetics

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

• Related Literature

- CD54HC00F3A and CD54HCT00F3A Military

Data Sheet, Document Number 3753

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

CC

= 5V,

o

C to 125oC

CC

OH

CD74HC00, CD74HCT00

High Speed CMOS Logic

Quad 2-Input NAND Gate

Description

The Harris CD54HC00, CD54HCT00, CD74HC00 and
CD74HCT00 logic gates utilize silicon gate CMOS
technology to achieve operating speeds similar to LSTTL
gates with the low power consumption of standard CMOS
integrated circuits. All devices have the ability to drive 10
LSTTL loads. The 74HCT logic family is functionally pin
compatible with the standard 74LS logic family.

Ordering Information

TEMP.RANGE

PART NUMBER

CD74HC00E -55 to 125 14 Ld PDIP E14.3
CD74HCT00E -55 to 125 14 Ld PDIP E14.3
CD74HC00M -55 to 125 14 Ld SOIC M14.15
CD74HCT00M -55 to 125 14 Ld SOIC M14.15
CD54HC00F -55 to 125 14 Ld CERDIP F14.3
CD54HCT00F -55 to 125 14 Ld CERDIP F14.3
CD54HC00W -55 to 125 Wafer
CD54HCT00W -55 to 125 Wafer
CD54HC00H -55 to 125 Die
CD54HCT00H -55 to 125 Die

NOTE: When ordering, usethe entire partnumber.Add the suffix 96
to obtain the variant in the tape and reel.

(oC) PACKAGE

PKG.

NO.

Pinout

CD54HC00, CD54HCT00, CD74HC00, CD74HCT00

(PDIP, CERDIP, SOIC)

TOP VIEW

1A

1
2

1B

1Y

3

2A

4

2B

5

2Y

6

GND

7

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1998

1

V

14

CC

4B

13

4A

12

4Y

11

3B

10

3A

9

3Y

8

File Number 1464.2

Functional Diagram

CD54HC00, CD54HCT00, CD74HC00, CD74HCT00

1A

1B

1Y

2A

2B

2Y

GND

1

2

3

4

5

6

7

14

V

CC

13

4B

12

4A

11

4Y

10

3B

9

3A

8

3Y

TRUTH TABLE

INPUTS OUTPUT

nA nB nY

LLH
LHH
HLH

Logic Symbol

HHL

nA

nY

nB

2