TEXAS INSTRUMENTS CD54ACT20 Technical data

55°C to 125°C

SOIC

ACT20M

CD54ACT20, CD74ACT20

DUAL 4-INPUT POSITIVE-NAND GATES

SCHS320 – NOVEMBER 2002

Inputs Are TTL-Voltage Compatible

Speed of Bipolar F, AS, and S, With

CD54ACT20 ...F PACKAGE

CD74ACT20 ...E OR M PACKAGE

(TOP VIEW)

Significantly Reduced Power Consumption

Balanced Propagation Delays

±24-mA Output Drive Current – Fanout to 15 F Devices

SCR-Latchup-Resistant CMOS Process and Circuit Design

Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015

1A 1B

1C 1D 1Y

GND

1 2 3 4 5 6 7

14 13 12 11 10

2D 2C NC 2B

description/ordering information

The ’ACT20 devices contain two independent 4-input NAND gates. They perform the Boolean function Y = A

• B • C • D or Y = A + B + C + D in positive logic.

ORDERING INFORMA TION

PDIP – E Tube CD74ACT20E CD74ACT20E

–

CDIP – F Tube CD54ACT20F3A CD54ACT20F3A

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

PACKAGE

–

†

Tube CD74ACT20M Tape and reel CD74ACT20M96

ORDERABLE

PART NUMBER

TOP-SIDE MARKING

logic diagram (positive logic)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

FUNCTION TABLE

(each gate)

INPUTS

A B C D

H H H H L

L XXX H X LXX H X XLX H X X X L H

2A 2B 2C 2D

OUTPUT

9 10 12 13

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

CD54ACT20, CD74ACT20 DUAL 4-INPUT POSITIVE-NAND GATES

SCHS320 – NOVEMBER 2002

absolute maximum ratings over operating free-air temperature range

Supply voltage range, V Input clamp current, I Output clamp current, I Continuous output current, I Continuous current through V Package thermal impedance, θ

–0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(VO < 0 or VO > VCC) (see Note 1) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2): E package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

M package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions (see Note 3)

CC CC

–55°C to

125°C

0 V 0 V

TA = 25°C MIN MAX MIN MAX MIN MAX

V V V V V I

∆t/∆v Input transition rise or fall rate 10 10 10 ns/V

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 4.5 5.5 4.5 5.5 4.5 5.5 V

High-level input voltage 2 2 2 V

Low-level input voltage 0.8 0.8 0.8 V

Input voltage 0 V

Output voltage 0 V

High-level output current –24 –24 –24 mA Low-level output current 24 24 24 mA

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

CC CC

–40°C to

85°C

0 V 0 V

CC CC

UNIT

V V

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CD54ACT20, CD74ACT20

or V

(INPUT)

(OUTPUT)

A, B, C, or D

DUAL 4-INPUT POSITIVE-NAND GATES

SCHS320 – NOVEMBER 2002

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS V

IOH = –50 µA 4.5 V 4.4 4.4 4.4

‡

†

‡

T est one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize power dissipation. T est verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C. Additional quiescent supply current per input pin, TTL inputs high, 1 unit load

VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA VI = VCC or GND, IO = 0 5.5 V 4 80 40 µA

VI = VCC – 2.1 V 4.5 V to 5.5 V 2.4 3 2.8 mA

IOH = –24 mA 4.5 V 3.94 3.7 3.8 IOH = –50 mA IOH = –75 mA IOL = 50 µA 4.5 V 0.1 0.1 0.1 IOL = 24 mA 4.5 V 0.36 0.5 0.44 IOL = 50 mA IOL = 75 mA

† †

5.5 V 3.85

5.5 V 1.65

TA = 25°C MIN MAX MIN MAX MIN MAX

–55°C to

125°C

10 10 10 pF

–40°C to

85°C

UNIT

ACT INPUT LOAD TABLE

INPUT

All 0.27

Unit Load is ∆ICC limit specified in electrical characteristics table (e.g., 2.4 mA at 25°C).

UNIT LOAD

switching characteristics over recommended operating free-air temperature range, V

= 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1)

PARAMETER

PLH

PHL

FROM

–55°C to

125°C

MIN MAX MIN MAX

3.4 13.5 3.5 12.3

–40°C to

operating characteristics, TA = 25°C

PARAMETER TYP UNIT

Power dissipation capacitance 48 pF

85°C

UNIT

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CD54ACT20, CD74ACT20 DUAL 4-INPUT POSITIVE-NAND GATES

SCHS320 – NOVEMBER 2002

PARAMETER MEASUREMENT INFORMATION

1.5 V

PHL

PLH

rec

50%

From Output

Under Test

CL = 50 pF

(see Note A)

CLR

Input

CLK

VOLTAGE WAVEFORMS

RECOVERY TIME

Input

In-Phase

Output

Out-of-Phase

Output

PROPAGATION DELAY AND OUTPUT TRANSITION TIMES

1.5 V 1.5 V

PLH

50%

PHL

VOLTAGE WAVEFORMS

R1 = 500 Ω Open

R2 = 500 Ω

LOAD CIRCUIT

1.5 V

90% 90%

50% V

10% 10%

2 × V

GND

3 V

0 V

3 V

0 V

50% V

10%10%

90%90%

TEST S1

1.5 V

Open

2 × V

GND

20% V

80% V

1.5 V 10%10%

PLZ

20% V

PHZ

80% V

3 V

0 V

3 V

0 V

≈V

≈0 V

3 V

0 V

3 V

0 V

PLH/tPHL

PLZ/tPZL

PHZ/tPZH

Input

Reference

Input

Data

1.5 V

Input

SETUP AND HOLD AND INPUT RISE AND FALL TIMES

3 V

0 V

Output

Control

Output

Waveform 1

S1 at 2 × V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

OUTPUT ENABLE AND DISABLE TIMES

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

90% 90%

VOLTAGE WAVEFORMS

1.5 V 1.5 V

PZL

PZH

VOLTAGE WAVEFORMS

NOTES: A. CL includes probe and test-fixture capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.

Phase relationships between waveforms are arbitrary. D. For clock inputs, f E. The outputs are measured one at a time with one input transition per measurement.

F. t G. t H. t

PLH PZL PLZ

and t and t and t

PHL PZH PHZ

is measured with the input duty cycle at 50%.

max

are the same as tpd. are the same as ten. are the same as t

dis

Figure 1. Load Circuit and Voltage Waveforms

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