TEXAS INSTRUMENTS CD54ACT20 Technical data

55°C to 125°C

SOIC

M

ACT20M

CD54ACT20, CD74ACT20

DUAL 4-INPUT POSITIVE-NAND GATES

SCHS320 – NOVEMBER 2002

D

Inputs Are TTL-Voltage Compatible

D

Speed of Bipolar F, AS, and S, With

CD54ACT20 ...F PACKAGE

CD74ACT20 ...E OR M PACKAGE

(TOP VIEW)

Significantly Reduced Power Consumption

D

Balanced Propagation Delays

D

±24-mA Output Drive Current
– Fanout to 15 F Devices

D

SCR-Latchup-Resistant CMOS Process and
Circuit Design

D

Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015

1A
1B

NC

1C
1D
1Y

GND

1
2
3
4
5
6
7

14
13
12
11
10

V

CC

2D
2C
NC
2B

9

2A

8

2Y

description/ordering information

The ’ACT20 devices contain two independent 4-input NAND gates. They perform the Boolean function
Y = A

• B • C • D or Y = A + B + C + D in positive logic.

ORDERING INFORMA TION

T

A

PDIP – E Tube CD74ACT20E CD74ACT20E

–

CDIP – F Tube CD54ACT20F3A CD54ACT20F3A

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.

PACKAGE

–

†

Tube CD74ACT20M
Tape and reel CD74ACT20M96

ORDERABLE

PART NUMBER

TOP-SIDE
MARKING

logic diagram (positive logic)

1

1A

2

1B

4

1C

5

1D

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

FUNCTION TABLE

(each gate)

INPUTS

A B C D

H H H H L

L XXX H
X LXX H
X XLX H
X X X L H

68

1Y

2A
2B
2C
2D

OUTPUT

Y

9
10
12
13

2Y

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2002, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

1

CD54ACT20, CD74ACT20
DUAL 4-INPUT POSITIVE-NAND GATES

SCHS320 – NOVEMBER 2002

absolute maximum ratings over operating free-air temperature range

Supply voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ

–0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

(VO < 0 or VO > VCC) (see Note 1) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

(VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 2): E package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

†

M package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions (see Note 3)

CC
CC

–55°C to

125°C

0 V
0 V

TA = 25°C
MIN MAX MIN MAX MIN MAX

V
V
V
V
V
I

OH

I

OL

∆t/∆v Input transition rise or fall rate 10 10 10 ns/V

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 4.5 5.5 4.5 5.5 4.5 5.5 V

CC

High-level input voltage 2 2 2 V

IH

Low-level input voltage 0.8 0.8 0.8 V

IL

Input voltage 0 V

I

Output voltage 0 V

O

High-level output current –24 –24 –24 mA
Low-level output current 24 24 24 mA

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

CC
CC

–40°C to

85°C

0 V
0 V

CC
CC

UNIT

V
V

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CD54ACT20, CD74ACT20

CC

V

V

V

or V

V

V

V

V

or V

V

(INPUT)

(OUTPUT)

A, B, C, or D

Y

ns

DUAL 4-INPUT POSITIVE-NAND GATES

SCHS320 – NOVEMBER 2002

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS V

IOH = –50 µA 4.5 V 4.4 4.4 4.4

=

OH

OL

I

I

I

CC

‡

D

I

CC

C

†

‡

i

T est one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize
power dissipation. T est verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.
Additional quiescent supply current per input pin, TTL inputs high, 1 unit load

I

IH

IL

=

I

IH

IL

VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA
VI = VCC or GND, IO = 0 5.5 V 4 80 40 µA

VI = VCC – 2.1 V 4.5 V to 5.5 V 2.4 3 2.8 mA

IOH = –24 mA 4.5 V 3.94 3.7 3.8
IOH = –50 mA
IOH = –75 mA
IOL = 50 µA 4.5 V 0.1 0.1 0.1
IOL = 24 mA 4.5 V 0.36 0.5 0.44
IOL = 50 mA
IOL = 75 mA

†
†

†
†

5.5 V 3.85

5.5 V 3.85

5.5 V 1.65

5.5 V 1.65

TA = 25°C
MIN MAX MIN MAX MIN MAX

–55°C to

125°C

10 10 10 pF

–40°C to

85°C

UNIT

ACT INPUT LOAD TABLE

INPUT

All 0.27

Unit Load is ∆ICC limit specified in
electrical characteristics table
(e.g., 2.4 mA at 25°C).

UNIT LOAD

switching characteristics over recommended operating free-air temperature range,
V

= 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1)

CC

PARAMETER

t

PLH

t

PHL

FROM

TO

–55°C to

125°C

MIN MAX MIN MAX

3.4 13.5 3.5 12.3

3.4 13.5 3.5 12.3

–40°C to

operating characteristics, TA = 25°C

PARAMETER TYP UNIT

C

Power dissipation capacitance 48 pF

pd

85°C

UNIT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

CD54ACT20, CD74ACT20
DUAL 4-INPUT POSITIVE-NAND GATES

SCHS320 – NOVEMBER 2002

PARAMETER MEASUREMENT INFORMATION

CC

1.5 V

S1

t

PHL

t

PLH

t

rec

50%

From Output

Under Test

CL = 50 pF

(see Note A)

CLR

Input

CLK

VOLTAGE WAVEFORMS

RECOVERY TIME

Input

In-Phase

Output

Out-of-Phase

Output

PROPAGATION DELAY AND OUTPUT TRANSITION TIMES

1.5 V 1.5 V

t

PLH

50%

t

PHL

VOLTAGE WAVEFORMS

R1 = 500 Ω Open

R2 = 500 Ω

LOAD CIRCUIT

1.5 V

90% 90%

t

r

50% V

10% 10%

t

f

2 × V

GND

CC

3 V

0 V

3 V

0 V

50% V

10%10%

90%90%

TEST S1

t

w

1.5 V

Open

2 × V

GND

t

h

20% V

80% V

CC

CC

CC

1.5 V
10%10%

t

PLZ

20% V

t

PHZ

80% V

t

f

CC

CC

3 V

0 V

3 V

0 V

≈V

V

V

≈0 V

3 V

0 V

3 V

0 V

CC

OL

OH

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Input

Reference

Input

Data

1.5 V

Input

SETUP AND HOLD AND INPUT RISE AND FALL TIMES

3 V

0 V

V

OH

CC

V

OL

t

f

V

OH

V

OL

t

r

Output

Control

Output

Waveform 1

S1 at 2 × V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

OUTPUT ENABLE AND DISABLE TIMES

CC

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

t

su

90% 90%

t

r

VOLTAGE WAVEFORMS

1.5 V 1.5 V

t

PZL

t

PZH

VOLTAGE WAVEFORMS

NOTES: A. CL includes probe and test-fixture capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.

Phase relationships between waveforms are arbitrary.
D. For clock inputs, f
E. The outputs are measured one at a time with one input transition per measurement.

F. t
G. t
H. t

PLH
PZL
PLZ

and t
and t
and t

PHL
PZH
PHZ

is measured with the input duty cycle at 50%.

max

are the same as tpd.
are the same as ten.
are the same as t

dis

.

Figure 1. Load Circuit and Voltage Waveforms

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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Copyright © 2007, Texas Instruments Incorporated

PACKAGE OPTION ADDENDUM

www.ti.com

9-Oct-2007

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

5962-0051301QCA ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type

CD54ACT20F3A ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type

CD74ACT20E ACTIVE PDIP N 14 25 Pb-Free

CD74ACT20EE4 ACTIVE PDIP N 14 25 Pb-Free

CD74ACT20M ACTIVE SOIC D 14 50 Green (RoHS &

no Sb/Br)

CD74ACT20M96 ACTIVE SOIC D 14 2500 Green (RoHS &

no Sb/Br)

CD74ACT20M96E4 ACTIVE SOIC D 14 2500 Green (RoHS &

no Sb/Br)

CD74ACT20M96G4 ACTIVE SOIC D 14 2500 Green (RoHS &

no Sb/Br)

CD74ACT20ME4 ACTIVE SOIC D 14 50 Green (RoHS &

no Sb/Br)

CD74ACT20MG4 ACTIVE SOIC D 14 50 Green (RoHS &

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(RoHS)

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU N / A for Pkg Type

CU NIPDAU N / A for Pkg Type

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

(3)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

TAPE AND REEL INFORMATION

11-Mar-2008

*All dimensions are nominal

Device Package

CD74ACT20M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

Type

Package

Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Mar-2008

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

CD74ACT20M96 SOIC D 14 2500 346.0 346.0 33.0

Pack Materials-Page 2