Texas Instruments CD54ACT191F3A Datasheet

Data sheet acquired from Harris Semiconductor
SCHS243A

October 1998 - Revised May 2000

CD54AC191,

CD54ACT191

Presettable Synchronous 4-Bit Binary

Up/Down Counter

Features

• Buffered Inputs

• Typical Propagation Delay

- 12.8ns at V

= 5V, TA = 25oC, CL = 50pF

CC

• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015

• SCR-Latchup-Resistant CMOS Process and Circuit
Design

• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption

• Balanced Propagation Delays

• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply

• ±24mA Output Drive Current

- Fanout to 15 FAST™ ICs

- Drives 50Ω Transmission Lines

Ordering Information

PART

NUMBER

CD54AC191F3A -55 to 125 16 Ld CERDIP
CD54ACT191F3A -55 to 125 16 Ld CERDIP

NOTES:

1. When ordering, use the entire part number. Add thesuffix96to
obtain the variant in the tape and reel.

2. Waf erand die for this partnumber is availablewhich meets all elec­trical specifications. Please contactyour local TI sales office or cus­tomer service for ordering information.

TEMP.

RANGE (oC) PACKAGE

Description

The CD54AC191 and CD54ACT191 are asynchronously
presettable binary up/down synchronous counters that utilize
Advanced CMOS Logic technology.Presetting the counter to
the number on preset data inputs (P0-P3) is accomplished
by setting LOW the asynchronous parallel load input (
Counting occurs when PL is HIGH, Count Enable (
LOW, and the Up/Down (

U/D) input is either LOW for up-

PL).

CE) is

counting or HIGH for down-counting. The counter is incre­mented or decremented synchronously with the LOW-to­HIGH transition of the clock.

When an overflow or underflow of the counter occurs, the
Terminal Count (TC) output, which is LOW during counting,
goes HIGH and remains HIGH for one clock cycle. This out­put can be used for look-ahead carry in high-speed cascad­ing (see Figure 12). The TC output also initiates the Ripple
Clock (

RC) output which, normally HIGH, goes LOW and
remains LOW for the low-level cascaded using the Ripple
Count output.

Pinout

CD54AC191, CD54ACT191

(CERDIP)

TOP VIEW

V

P1
Q1
Q0
CE

U/D

Q2
Q3

GND

1
2
3
4
5
6
7
8

16

CC

15

P0

14

CP

13

RC

12

TC

11

PL

10

P2

9

P3

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.

Copyright

© 2000, Texas Instruments Incorporated

1

CD54AC191, CD54ACT191

Functional Diagram

BINARY

PRESET

P0 P1 P2 P3

15 1 10 9

ASYN. PARALLEL

LOAD ENABLE

CLOCK

UP/DOWN

COUNT

ENABLE

11

14

5

4

TRUTH TABLE

INPUTS

HLL ↑ Count Up
HLH ↑ Count Down
L X X X Asynchronous Preset
H H X X No Change

U/D or CE should be changed only when clock is high.
X = Don’t Care
↑ = Low-to-High clock transition.

3

Q0

2

Q1

6

Q2

7

Q3

TERMINAL

12

COUNT

13

RIPPLE CLOCK

FUNCTIONPL CE U/D CP

BINARY
OUTPUTS

2

CD54AC191, CD54ACT191

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC VCC or Ground Current, I

CC orIGND

(Note 3) . . . . . . . . .±100mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC (Note 4)

AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V

ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Slew Rate, dt/dv

AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)

AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)

ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

3. For up to 4 outputs per device, add ±25mA for each additional output.

4. Unless otherwise specified, all voltages are referenced to ground.

5. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 5) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ___

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ___

Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

CC

DC Electrical Specifications

PARAMETER SYMBOL

AC TYPES

High Level Input Voltage V

Low Level Input Voltage V

High Level Output Voltage V

IH

IL

OH

TEST

CONDITIONS

(V) IO(mA) MIN MAX MIN MAX MIN MAX

I

V

CC

(V)

25

o

C

-40oC TO
85oC

-55oC TO
125oC

- - 1.5 1.2 - 1.2 - 1.2 - V
3 2.1 - 2.1 - 2.1 - V

5.5 3.85 - 3.85 - 3.85 - V

- - 1.5 - 0.3 - 0.3 - 0.3 V
3 - 0.9 - 0.9 - 0.9 V

5.5 - 1.65 - 1.65 - 1.65 V

VIH or V

-0.05 1.5 1.4 - 1.4 - 1.4 - V

IL

-0.05 3 2.9 - 2.9 - 2.9 - V

-0.05 4.5 4.4 - 4.4 - 4.4 - V

-4 3 2.58 - 2.48 - 2.4 - V

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

5.5 - - 3.85 - - - V

(Note 6, 7)

-50

5.5----3.85 - V

(Note 6, 7)

UNITSV

3

CD54AC191, CD54ACT191

DC Electrical Specifications (Continued)

PARAMETER SYMBOL

Low Level Output Voltage V

OL

TEST

CONDITIONS

(V) IO(mA) MIN MAX MIN MAX MIN MAX

I

VIH or V

0.05 1.5 - 0.1 - 0.1 - 0.1 V

IL

V

CC

(V)

25

o

C

0.05 3 - 0.1 - 0.1 - 0.1 V

0.05 4.5 - 0.1 - 0.1 - 0.1 V
12 3 - 0.36 - 0.44 - 0.5 V
24 4.5 - 0.36 - 0.44 - 0.5 V
75

5.5 - - - 1.65 - - V

(Note 6, 7)

50

5.5-----1.65 V

(Note 6, 7)

Input Leakage Current I

I

VCC or

- 5.5 - ±0.1 - ±1-±1 µA

GND

Quiescent Supply Current
MSI

I

CC

VCC or

GND

0 5.5 - 8 - 80 - 160 µA

ACT TYPES

High Level Input Voltage V

IH

- - 4.5 to

2-2-2-V

5.5

Low Level Input Voltage V

IL

- - 4.5 to

- 0.8 - 0.8 - 0.8 V

5.5

High Level Output Voltage V

OH

VIH or V

-0.05 4.5 4.4 - 4.4 - 4.4 - V

IL

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

5.5 - - 3.85 - - - V

(Note 6, 7)

-50

5.5----3.85 - V

(Note 6, 7)

Low Level Output Voltage V

OL

VIH or V

0.05 4.5 - 0.1 - 0.1 - 0.1 V

IL

24 4.5 - 0.36 - 0.44 - 0.5 V
75

5.5 - - - 1.65 - - V

(Note 6, 7)

50

5.5-----1.65 V

(Note 6, 7)

Input Leakage Current I

I

VCC or

- 5.5 - ±0.1 - ±1-±1 µA

GND

Quiescent Supply Current
MSI

AdditionalSupply Current per
Input Pin TTL Inputs High

I

CC

VCC or

GND

∆I

CC

V

CC

-2.1

0 5.5 - 8 - 80 - 160 µA

- 4.5 to

- 2.4 - 2.8 - 3 mA

5.5

1 Unit Load

NOTES:

6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.

7. Test verifies a minimum 50Ω transmission-line-drive capability at 85

o

C, 75Ω at 125oC.

-40oC TO
85oC

-55oC TO
125oC

UNITSV

ACT Input Load Table

INPUT UNIT LOAD

P0-P3, PL 0.75

CL, U/D, CE 0.85

NOTE: Unit load is ∆ICClimit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25oC.

4

CD54AC191, CD54ACT191

Prerequisite For Switching Function

PARAMETER SYMBOL VCC (V)

AC TYPES

Max. Frequency f

(Note 10)

CP Pulse Width t

PL Pulse Width t

Recovery Time t

Set-Up Time, Pn to PL t

Set-Up Time, CE to CP t

Set-Up Time, U/D to CP t

Hold Time, Pn to PL t

Hold Time, CE to CP t

Hold Time, U/D to CP t

ACT TYPES

Max. Frequency f

(Note 10)5(Note 9)
CP Pulse Width t
PL Pulse Width t
Recovery Time t
Set-Up Time, Pn to PL t

MAX

W

W

REC

SU

SU

SU

H

H

H

MAX

W
W

REC

SU

-40oC TO 85oC -55oC TO 125oC
UNITSMIN MAX MIN MAX

1.5 5.5 - 4.8 - MHz

3.3

49 - 43 - MHz

(Note 8)

5

68 - 60 - MHz

(Note 9)

1.5 91 - 104 - ns

3.3 10.5 - 11.6 - ns
5 7.3 - 8.3 - ns

1.5 66 - 75 - ns

3.3 7.4 - 8.4 - ns
5 5.3 - 6 - ns

1.5 71 - 81 - ns

3.3 8 - 9.1 - ns
5 5.7 - 6.5 - ns

1.5 44 - 50 - ns

3.3 4.9 - 5.6 - ns
5 3.5 - 4 - ns

1.5 115 - 131 - ns

3.3 12.9 - 14.7 - ns
5 9.2 - 10.5 - ns

1.5 132 - 150 - ns

3.3 14.7 - 16.8 - ns
5 10.5 - 12 - ns

1.5 22 - 25 - ns

3.3 2.5 - 2.8 - ns
52-2-ns

1.5 0 - 0 - ns

3.3 0 - 0 - ns
50-0-ns

1.5 0 - 0 - ns

3.3 0 - 0 - ns
50-0-ns

68 - 60 - MHz

5 7.3 - 8.3 - ns
5 5.3 - 6 - ns
5 5.7 - 6.5 - ns
5 3.5 - 4 - ns

5

CD54AC191, CD54ACT191

Prerequisite For Switching Function (Continued)

-40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL VCC (V)

Set-Up Time, CE to CP t
Set-Up Time, U/D to CP t
Hold Time, Pn to PL t
Hold Time, CE to CP t
Hold Time, U/D to CP t

SU
SU

H
H
H

5 9.2 - 10.5 - ns
5 10.5 - 12 - ns
52-2-ns
50-0-ns
50-0-ns

NOTES:

8. 3.3V Min is at 3V.

9. 5V Min is at 4.5V.

10. Applies to non-cascaded operation only. Withcascaded counters clock-to-terminal count propagation delays, countenable (CE)-to-clock
set-up times, and count enable (CE)-to-clock hold times determine max clock frequency. For example, with these AC devices at 85oC
and VCC = 5V:.

f

MAX

------------------------------------------------------------------------------------------------------------------------------------------------------- -

CP()

CP-to-TC prop. delay + CE-to-CP setup + CE-to-CP Hold

1

1

----------------------------------- -

18.2 9.2 0++

36MHz≈==

UNITSMIN MAX MIN MAX

Switching Specifications Input t

PARAMETER SYMBOL VCC (V)

AC TYPES

Propagation Delay
PL to Qn

Propagation Delay
Pn to Qn

Propagation Delay
CP to Qn

Propagation Delay
CP to RC

Propagation Delay
CP to TC

Propagation Delay
U/D to RC

Propagation Delay
U/D to TC

t

PLH

t

PLH

t

PLH

t

PLH

t

PLH

t

PLH

t

PLH

, tf = 3ns, CL= 50pF (Worst Case)

r

, t

PHL

1.5 - - 171 - - 188 ns

3.3

5.4 - 19.1 5.3 - 21 ns

(Note 12)

5

3.9 - 13.6 3.8 - 15 ns

(Note 13)

, t

PHL

1.5 - - 173 - - 190 ns

3.3 5.4 - 19.4 5.3 - 21.3 ns
5 3.9 - 13.8 3.8 - 15.2 ns

, t

PHL

1.5 - - 182 - - 200 ns

3.3 5.8 - 20.4 5.6 - 22.4 ns
5 4.1 - 14.5 4 - 16 ns

, t

PHL

1.5 - - 136 - - 150 ns

3.3 4.3 - 15.3 4.2 - 16.8 ns
5 3.1 -113 -12ns

, t

PHL

1.5 - - 227 - - 250 ns

3.3 7.2 - 25.5 7 - 28 ns
5 5.2 - 18.2 5 - 20 ns

, t

PHL

1.5 - - 246 - - 271 ns

3.3 7.8 - 27.6 7.6 - 30.4 ns
5 5.6 - 19.7 5.4 - 21.7 ns

, t

PHL

1.5 - - 160 - - 176 ns

3.3 5.1 - 17.9 4.9 - 19.7 ns
5 3.6 - 12.8 3.5 - 14.1 ns

-40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN TYP MAX

6

CD54AC191, CD54ACT191

Switching Specifications Input t

, tf = 3ns, CL= 50pF (Worst Case) (Continued)

r

-40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL VCC (V)

Propagation Delay
CE to RC

t

PLH

, t

PHL

1.5 - - 137 - - 151 ns

3.3 4.4 - 15.4 4.2 - 16.9 ns
5 3.1 - 11 3 - 12.1 ns

Input Capacitance C
Power Dissipation Capacitance C

I

PD

- - -10- -10pF

- - 96 - - 96 - pF

(Note 14)

ACT TYPES

Propagation Delay
PL to Qn

Propagation Delay

t

PLH

t

PLH

, t

PHL

5

4.2 - 14.8 4.1 - 16.3 ns

(Note 13)

, t

PHL

5 3.9 - 13.8 3.8 - 15.2 ns

Pn to Qn
Propagation Delay

t

PLH

, t

PHL

5 4.1 - 14.5 4 - 16 ns

CP to Qn
Propagation Delay

t

PLH

, t

PHL

5 3.1 - 10.9 3 - 12 ns

CP to RC
Propagation Delay

t

PLH

, t

PHL

5 5.2 - 18.2 5 - 20 ns

CP to TC
Propagation Delay

t

PLH

, t

PHL

5 5.6 - 19.7 5.4 - 21.7 ns

U/D to RC
Propagation Delay

t

PLH

, t

PHL

5 3.8 - 13.5 3.7 - 14.9 ns

U/D to TC
Propagation Delay

t

PLH

, t

PHL

5 3.3 - 11.5 3.2 - 12.7 ns

CE to RC
Input Capacitance C
Power Dissipation Capacitance C

I

PD

- - -10- -10pF

- - 96 - - 96 - pF

(Note 14)

NOTES:

11. Limits tested 100%.

12. 3.3V Min is at 3.6V, Max is at 3V.

13. 5V Min is at 5.5V, Max is at 4.5V

14. CPD is used to determine the dynamic power consumption per package.
PD=CPDV

2

fi+(CL+VCC2fo) where fi= input frequency, fo= output frequency, CL= output load capacitance, VCC= supply voltage.

CC

UNITSMIN TYP MAX MIN TYP MAX

CP

Qn OR TC

1/f

MAX

t

V

S

t

PHL

V

S

W

t

PLH

V

S

V

INPUT LEVEL

S

CP OR CE

RC

V

S

t

PHL

V

S

INPUT LEVEL

V

S

t

PLH

V

S

FIGURE 1. FIGURE 2.

7

CD54AC191, CD54ACT191

PL

CP

Qn

Pn

Qn

Pn

PL

t

t

V

PLH

V

S

t

PHL

V

S

V

S

t

INPUT LEVEL

PLH

V

S

Qn

FIGURE 3. FIGURE 4.

Pn

V

INPUT LEVEL

S

t

W

t

REC

INPUT LEVEL

PL

t

Qn

SU

V

(H)

The shaded areas indicate when the input is permitted to change for
predictable output performance.

FIGURE 5.

W

S

S

V

S

INPUT LEVEL

V

S

tH(H)

t

SU

FIGURE 6.

V

S

(L)

INPUT LEVEL

t

PHL

V

S

V

S

tH(L)

V

S

INPUT LEVEL

INPUT LEVEL

U/D

TC

RC

t

t

PLH

PHL

V

S

V

S

V

V

S

S

t

PHL

V

INPUT LEVEL

S

t

PLH

V

S

FIGURE 7. FIGURE 8.

OUTPUT

R

(NOTE)

L

500Ω

DUT

OUTPUT

LOAD

C

L

50pF

NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.

AC ACT

Input Level V
Input Switching Voltage, V
Output Switching Voltage, V

S

S

0.5 V

0.5 V

CC

CC
CC

FIGURE 9. PROPAGATION DELAY TIMES

3V

1.5V

0.5 V

CC

CP

CE

V

S

CE MAY

CHANGE

t

SU

(H-L)

ONLY

(L)

V

S

t

(L)

H

CE MAY

CHANGE

tSU(H)

V

S

V

INPUT

S

LEVEL

INPUT
LEVEL

8

CD54AC191, CD54ACT191

LOAD

P0

PRESET

INPUTS

TERMINAL COUNT

RIPPLE CLOCK

Sequence:

1. Load (preset) to binary thirteen.

2. Count up to fourteen, fifteen, zero, one, and two.

3. Inhibit.

4. Count down to one, zero, fifteen, fourteen, and thirteen.

FIGURE 10. CD54AC191 DECODE COUNTERS TYPICAL LOAD, COUNT, AND INHIBIT SEQUENCES

P1
P2
P3

CLOCK

DOWN/UP

ENABLE

Q0
Q1
Q2
Q3

H

L

H

H

L
L

H

13 14 15 0 1 2

COUNT UP INHIBIT COUNT DOWN

LOAD

H
L

H
L

2 2 1 0 15 14 13

H

L

DIRECTION

CONTROL

ENABLE

CLOCK

DIRECTION

U/D
CE
CP TC

U/D
CE
CP TC

U/D
CE
CP TC

FIGURE 11. SYNCHRONOUS N-STAGE COUNTER WITH PARALLEL GATED TC/RC

CONTROL

U/D

RC
CE
CP

ENABLE

CLOCK

U/D
CE
CP

RC

U/D
CE
CP

RC

FIGURE 12. SYNCHRONOUS N-STAGE COUNTER USING RIPPLE TC/RC

9

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pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating

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Copyright  2000, Texas Instruments Incorporated