Texas Instruments CD54ACT191F3A Datasheet

Data sheet acquired from Harris Semiconductor
SCHS243A

October 1998 - Revised May 2000

CD54AC191,

CD54ACT191

Presettable Synchronous 4-Bit Binary

Up/Down Counter

Features

• Buffered Inputs

• Typical Propagation Delay

- 12.8ns at V

= 5V, TA = 25oC, CL = 50pF

CC

• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015

• SCR-Latchup-Resistant CMOS Process and Circuit
Design

• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption

• Balanced Propagation Delays

• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply

• ±24mA Output Drive Current

- Fanout to 15 FAST™ ICs

- Drives 50Ω Transmission Lines

Ordering Information

PART

NUMBER

CD54AC191F3A -55 to 125 16 Ld CERDIP
CD54ACT191F3A -55 to 125 16 Ld CERDIP

NOTES:

1. When ordering, use the entire part number. Add thesuffix96to
obtain the variant in the tape and reel.

2. Waf erand die for this partnumber is availablewhich meets all elec­trical specifications. Please contactyour local TI sales office or cus­tomer service for ordering information.

TEMP.

RANGE (oC) PACKAGE

Description

The CD54AC191 and CD54ACT191 are asynchronously
presettable binary up/down synchronous counters that utilize
Advanced CMOS Logic technology.Presetting the counter to
the number on preset data inputs (P0-P3) is accomplished
by setting LOW the asynchronous parallel load input (
Counting occurs when PL is HIGH, Count Enable (
LOW, and the Up/Down (

U/D) input is either LOW for up-

PL).

CE) is

counting or HIGH for down-counting. The counter is incre­mented or decremented synchronously with the LOW-to­HIGH transition of the clock.

When an overflow or underflow of the counter occurs, the
Terminal Count (TC) output, which is LOW during counting,
goes HIGH and remains HIGH for one clock cycle. This out­put can be used for look-ahead carry in high-speed cascad­ing (see Figure 12). The TC output also initiates the Ripple
Clock (

RC) output which, normally HIGH, goes LOW and
remains LOW for the low-level cascaded using the Ripple
Count output.

Pinout

CD54AC191, CD54ACT191

(CERDIP)

TOP VIEW

V

P1
Q1
Q0
CE

U/D

Q2
Q3

GND

1
2
3
4
5
6
7
8

16

CC

15

P0

14

CP

13

RC

12

TC

11

PL

10

P2

9

P3

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.

Copyright

© 2000, Texas Instruments Incorporated

1

CD54AC191, CD54ACT191

Functional Diagram

BINARY

PRESET

P0 P1 P2 P3

15 1 10 9

ASYN. PARALLEL

LOAD ENABLE

CLOCK

UP/DOWN

COUNT

ENABLE

11

14

5

4

TRUTH TABLE

INPUTS

HLL ↑ Count Up
HLH ↑ Count Down
L X X X Asynchronous Preset
H H X X No Change

U/D or CE should be changed only when clock is high.
X = Don’t Care
↑ = Low-to-High clock transition.

3

Q0

2

Q1

6

Q2

7

Q3

TERMINAL

12

COUNT

13

RIPPLE CLOCK

FUNCTIONPL CE U/D CP

BINARY
OUTPUTS

2

CD54AC191, CD54ACT191

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC VCC or Ground Current, I

CC orIGND

(Note 3) . . . . . . . . .±100mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC (Note 4)

AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V

ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Slew Rate, dt/dv

AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)

AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)

ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

3. For up to 4 outputs per device, add ±25mA for each additional output.

4. Unless otherwise specified, all voltages are referenced to ground.

5. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 5) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ___

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ___

Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

CC

DC Electrical Specifications

PARAMETER SYMBOL

AC TYPES

High Level Input Voltage V

Low Level Input Voltage V

High Level Output Voltage V

IH

IL

OH

TEST

CONDITIONS

(V) IO(mA) MIN MAX MIN MAX MIN MAX

I

V

CC

(V)

25

o

C

-40oC TO
85oC

-55oC TO
125oC

- - 1.5 1.2 - 1.2 - 1.2 - V
3 2.1 - 2.1 - 2.1 - V

5.5 3.85 - 3.85 - 3.85 - V

- - 1.5 - 0.3 - 0.3 - 0.3 V
3 - 0.9 - 0.9 - 0.9 V

5.5 - 1.65 - 1.65 - 1.65 V

VIH or V

-0.05 1.5 1.4 - 1.4 - 1.4 - V

IL

-0.05 3 2.9 - 2.9 - 2.9 - V

-0.05 4.5 4.4 - 4.4 - 4.4 - V

-4 3 2.58 - 2.48 - 2.4 - V

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

5.5 - - 3.85 - - - V

(Note 6, 7)

-50

5.5----3.85 - V

(Note 6, 7)

UNITSV

3