TEXAS INSTRUMENTS CD54ACT109 Technical data
55°C to 125°C
SOIC
M
ACT109M
DUAL J-K
POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
CD54ACT109, CD74ACT109
WITH CLEAR AND PRESET
SCHS327 – JANUARY 2003
D
Inputs Are TTL-Voltage Compatible
D
Speed of Bipolar F, AS, and S, With
CD54ACT109 ...F PACKAGE
CD74ACT109 ...E OR M PACKAGE
(TOP VIEW)
Significantly Reduced Power Consumption
D
Balanced Propagation Delays
D
±24-mA Output Drive Current
– Fanout to 15 F Devices
D
SCR-Latchup-Resistant CMOS Process and
Circuit Design
D
Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
1CLR
1J
1K
1CLK
1PRE
1Q
1Q
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
2CLR
2J
2K
2CLK
2PRE
2Q
2Q
description/ordering information
The ’ACT109 devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset
(PRE
) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE
and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to
the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and
is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K
can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle
flip-flops by grounding K
T
–
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
and tying J high. They also can perform as D-type flip-flops if J and K are tied together.
ORDERING INFORMATION
A
PDIP – E Tube CD74ACT109E CD74ACT109E
CDIP – F Tube CD54ACT109F3A CD54ACT109F3A
PACKAGE
–
†
Tube CD74ACT109M
Tape and reel CD74ACT109M96
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
inputs
PRE CLR CLK J K Q Q
L H X X X H L
H LXXXLH
L LXXXH†H
H H ↑ LLLH
H H ↑ H L Toggle
H H ↑ LHQ0Q0
H H ↑ HHHL
H H L X X Q0 Q0
‡
Unpredictable and unstable condition if both PRE
go high simultaneously after both being low at the same
time
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUTS
and CLR
†
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
CD54ACT109, CD74ACT109
DUAL J-K
POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS327 – JANUARY 2003
logic diagram, each flip-flop (positive logic)
PRE
J
K
CLK
CLR
C
TG
C
C
C
TG
C
C
C
TG
C
C
TG
C
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
(VI < 0 V or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0 V or VO > VCC) (see Note 1) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
(VO > 0 V or VO < VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 2): E package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
M package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
Q
Q
†
recommended operating conditions (see Note 3)
CC
CC
–55°C to
125°C
0 V
0 V
TA = 25°C
MIN MAX MIN MAX MIN MAX
V
V
V
V
V
I
OH
I
OL
∆t/∆v Input transition rise or fall rate 10 10 10 ns/V
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
2
Supply voltage 4.5 5.5 4.5 5.5 4.5 5.5 V
CC
High-level input voltage 2 2 2 V
IH
Low-level input voltage 0.8 0.8 0.8 V
IL
Input voltage 0 V
I
Output voltage 0 V
O
High-level output current –24 –24 –24 mA
Low-level output current 24 24 24 mA
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CC
CC
–40°C to
85°C
0 V
0 V
CC
CC
UNIT
V
V
CC
V
V
V
or V
V
V
V
V
or V
V
twPulse duration
ns
DUAL J-K
POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
CD54ACT109, CD74ACT109
WITH CLEAR AND PRESET
SCHS327 – JANUARY 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS V
IOH = –50 µA 4.5 V 4.4 4.4 4.4
=
OH
OL
I
I
I
CC
‡
D
I
CC
C
†
‡
i
T est one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize
power dissipation. T est verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.
Additional quiescent supply current per input pin, TTL inputs high, 1 unit load
I
IH
IL
=
I
IH
IL
VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA
VI = VCC or GND, IO = 0 5.5 V 4 80 40 µA
VI = VCC –2.1 V
IOH = –24 mA 4.5 V 3.94 3.7 3.8
IOH = –50 mA
IOH = –75 mA
IOL = 50 µA 4.5 V 0.1 0.1 0.1
IOL = 24 mA 4.5 V 0.36 0.5 0.44
IOL = 50 mA
IOL = 75 mA
†
5.5 V 3.85
†
5.5 V 3.85
†
†
5.5 V 1.65
5.5 V 1.65
4.5 V to
5.5 V
TA = 25°C
MIN MAX MIN MAX MIN MAX
–55°C to
125°C
2.4 3 2.8 mA
10 10 10 pF
–40°C to
85°C
UNIT
ACT INPUT LOAD TABLE
INPUT
J or CLK 1
K 0.53
CLR or PRE 0.58
Unit Load is ∆ICC limit specified in
electrical characteristics table
(e.g., 2.4 mA at 25°C).
UNIT LOAD
timing requirements over recommended operating conditions (unless otherwise noted)
f
clock
t
su
t
h
t
rec
–55°C to
125°C
MIN MAX MIN MAX
Clock frequency 100 114 MHz
CLK high or low 5 4.4
CLR or PRE low 5.5 4.8
Setup time, before CLK↑ J or K 5.5 4.8 ns
Hold time, after CLK↑ J or K 0 0 ns
Recovery time, before CLK↑ CLR↑ or PRE↑ 2.5 2.2 ns
–40°C to
85°C
UNIT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
CD54ACT109, CD74ACT109
(INPUT)
(OUTPUT)
t
Q
Q
ns
t
Q
Q
ns
DUAL J-K
POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS327 – JANUARY 2003
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1)
CC
PARAMETER
f
max
PLH
PHL
FROM
CLK
CLR or PRE
CLK
CLR or PRE
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TYP UNIT
C
pd
Power dissipation capacitance 56 pF
TO
or
or
–55°C to
125°C
MIN MAX MIN MAX
100 114 MHz
2.6 10.3 2.7 9.4
3.1 12.2 3.2 11.1
2.6 10.3 2.7 9.4
3.1 12.2 3.2 11.1
–40°C to
85°C
UNIT
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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