±24-mA Output Drive Current
– Fanout to 15 F Devices
D
SCR-Latchup-Resistant CMOS Process and
Circuit Design
D
Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
1CLR
1J
1K
1CLK
1PRE
1Q
1Q
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
2CLR
2J
2K
2CLK
2PRE
2Q
2Q
description/ordering information
The ’ACT109 devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset
(PRE
) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE
and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to
the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and
is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K
can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle
flip-flops by grounding K
T
–
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
and tying J high. They also can perform as D-type flip-flops if J and K are tied together.
Unpredictable and unstable condition if both PRE
go high simultaneously after both being low at the same
time
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUTS
and CLR
†
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
CD54ACT109, CD74ACT109
DUAL J-K
POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS327 – JANUARY 2003
logic diagram, each flip-flop (positive logic)
PRE
J
K
CLK
CLR
C
TG
C
C
C
TG
C
C
C
TG
C
C
TG
C
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CC
CC
–40°C to
85°C
0V
0V
CC
CC
UNIT
V
V
CC
V
V
V
or V
V
V
V
V
or V
V
twPulse duration
ns
DUAL J-K
POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
CD54ACT109, CD74ACT109
WITH CLEAR AND PRESET
SCHS327 – JANUARY 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETERTEST CONDITIONSV
IOH = –50 µA4.5 V4.44.44.4
=
OH
OL
I
I
I
CC
‡
D
I
CC
C
†
‡
i
T est one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize
power dissipation. T est verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.
Additional quiescent supply current per input pin, TTL inputs high, 1 unit load
I
IH
IL
=
I
IH
IL
VI = VCC or GND5.5 V±0.1±1±1µA
VI = VCC or GND,IO = 05.5 V48040µA
VI = VCC –2.1 V
IOH = –24 mA4.5 V3.943.73.8
IOH = –50 mA
IOH = –75 mA
IOL = 50 µA4.5 V0.10.10.1
IOL = 24 mA4.5 V0.360.50.44
IOL = 50 mA
IOL = 75 mA
†
5.5 V3.85
†
5.5 V3.85
†
†
5.5 V1.65
5.5 V1.65
4.5 V to
5.5 V
TA = 25°C
MINMAXMINMAXMINMAX
–55°C to
125°C
2.432.8mA
101010pF
–40°C to
85°C
UNIT
ACT INPUT LOAD TABLE
INPUT
J or CLK1
K0.53
CLR or PRE0.58
Unit Load is ∆ICC limit specified in
electrical characteristics table
(e.g., 2.4 mA at 25°C).
UNIT LOAD
timing requirements over recommended operating conditions (unless otherwise noted)
f
clock
t
su
t
h
t
rec
–55°C to
125°C
MINMAXMINMAX
Clock frequency100114MHz
CLK high or low54.4
CLR or PRE low5.54.8
Setup time, before CLK↑J or K5.54.8ns
Hold time, after CLK↑J or K00ns
Recovery time, before CLK↑CLR↑ or PRE↑2.52.2ns
–40°C to
85°C
UNIT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
CD54ACT109, CD74ACT109
(INPUT)
(OUTPUT)
t
Q
Q
ns
t
Q
Q
ns
DUAL J-K
POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS327 – JANUARY 2003
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1)
CC
PARAMETER
f
max
PLH
PHL
FROM
CLK
CLR or PRE
CLK
CLR or PRE
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETERTYPUNIT
C
pd
Power dissipation capacitance56pF
TO
or
or
–55°C to
125°C
MINMAXMINMAX
100114MHz
2.610.32.79.4
3.112.23.211.1
2.610.32.79.4
3.112.23.211.1
–40°C to
85°C
UNIT
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DUAL J-K
POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
CD54ACT109, CD74ACT109
WITH CLEAR AND PRESET
SCHS327 – JANUARY 2003
PARAMETER MEASUREMENT INFORMATION
CC
1.5 V
S1
t
t
PHL
t
PLH
rec
50%
From Output
Under Test
CL = 50 pF
(see Note A)
CLR
Input
CLK
VOLTAGE WA VEFORMS
RECOVERY TIME
Input
In-Phase
Output
Out-of-Phase
Output
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
1.5 V1.5 V
t
PLH
50%
t
PHL
VOLTAGE WAVEFORMS
R1 = 500 ΩOpen
R2 = 500 Ω
LOAD CIRCUIT
1.5 V
90%90%
t
r
50% V
10%10%
t
f
2 × V
GND
CC
3 V
0 V
3 V
0 V
50% V
10%10%
90%90%
t
t
CC
f
r
3 V
0 V
V
V
V
V
OH
OL
OH
OL
TESTS1
t
w
1.5 V
Open
2 × V
GND
t
h
20% V
80% V
CC
CC
CC
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Input
Reference
Input
Data
1.5 V
Input
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
Output
Control
Output
Waveform 1
S1 at 2 × V
(see Note B)
Waveform 2
(see Note B)
CC
Output
S1 at GND
OUTPUT ENABLE AND DISABLE TIMES
1.5 V1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
90%90%
t
r
VOLTAGE WA VEFORMS
1.5 V1.5 V
t
PZL
t
PZH
VOLTAGE WAVEFORMS
1.5 V
10%10%
t
PLZ
20% V
t
PHZ
80% V
t
CC
CC
3 V
0 V
f
3 V
0 V
3 V
0 V
3 V
0 V
≈V
V
OL
V
OH
≈0 V
CC
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
Phase relationships between waveforms are arbitrary.
D. For clock inputs, f
E. The outputs are measured one at a time with one input transition per measurement.
F. t
G. t
H. t
and t
PLH
PZL
PLZ
I. All parameters and waveforms are not applicable to all devices.
and t
and t
PHL
PZH
PHZ
is measured with the input duty cycle at 50%.
max
are the same as tpd.
are the same as ten.
are the same as t
CD54ACT109F3AACTIVECDIPJ161TBDA42 SNPBN / A for Pkg Type
CD74ACT109EACTIVEPDIPN1625Pb-Free
CD74ACT109EE4ACTIVEPDIPN1625Pb-Free
CD74ACT109MACTIVESOICD1640Green (RoHS &
no Sb/Br)
CD74ACT109M96ACTIVESOICD162500 Green (RoHS &
no Sb/Br)
CD74ACT109M96E4ACTIVESOICD162500 Green (RoHS &
no Sb/Br)
CD74ACT109M96G4ACTIVESOICD162500 Green (RoHS &
no Sb/Br)
CD74ACT109ME4ACTIVESOICD1640Green (RoHS &
no Sb/Br)
CD74ACT109MG4ACTIVESOICD1640Green (RoHS &
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(RoHS)
(RoHS)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAUN / A for Pkg Type
CU NIPDAUN / A for Pkg Type
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
(3)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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