TEXAS INSTRUMENTS CD54AC163 Technical data

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CD54AC163, CD74AC163

4-BIT SYNCHRONOUS BINARY COUNTERS

SCHS299 – APRIL 2000

D

Internal Look-Ahead for Fast Counting

D

Carry Output for n-Bit Cascading

D

Synchronous Counting

D

Synchronously Programmable

D

Package Options Include Plastic
Small-Outline (M), Standard Plastic (E) and
Ceramic (F) DIPs

description

The CD54AC163 and CD74AC163 devices are

CD54AC163 ...F PACKAGE

CD74AC163 . . . E OR M PACKAGE

CLR
CLK

ENP

GND

(TOP VIEW)

1
2

A

3

B

4

C

5

D

6
7
8

16
15
14
13
12
11
10

9

V

CC

RCO
Q

A

Q

B

Q

C

Q

D

ENT
LOAD

4-bit binary counters. These synchronous,
presettable counters feature an internal carry
look-ahead for application in high-speed counting
designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs
change coincident with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating.
This mode of operation eliminates the output counting spikes normally associated with synchronous
(ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge
of the clock waveform.

The counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15.
Presetting is synchronous; therefore, setting up a low level at the load input disables the counter and causes
the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.

The clear function is synchronous. A low level at the clear (CLR

) input sets all four of the flip-flop outputs low
after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear
allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The
active-low output of the gate used for decoding is connected to CLR to synchronously clear the counter to 0000
(LLLL).

The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function.
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a
high-level pulse while the count is maximum (9 or 15 with Q

high). This high-level overflow ripple-carry pulse

A

can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the
level of CLK.

These devices feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.

The CD54AC163 is characterized for operation over the full military temperature range of –55°C to 125°C.
The CD74AC163 is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2000, Texas Instruments Incorporated

1

CD54AC163, CD74AC163

FUNCTION

Parallel load

Inhibit

4-BIT SYNCHRONOUS BINARY COUNTERS

SCHS299 – APRIL 2000

FUNCTION TABLE

INPUTS

CLR CLK ENP ENT LOAD A,B,C,D Q

L ↑ X X X X L L Reset (clear)
h ↑ X X l l L L
h ↑ XX l h HNote 1
h ↑ h h h X Count Note 1 Count
h X l X h X q
h X X l h X q

H = high level, L = low level, X = don’t care, h = high level one setup time prior to the CLK
low-to-high transition, l = low level one setup time prior to the CLK low-to-high transition, q = the
state of the referenced output prior to the CLK low-to-high transition, ↑ = CLK low-to-high
transition.

NOTE 1: The RCO output is high when ENT is high and the counter is at terminal count (HHHH).

OUTPUTS

RCO

n

Note 1

n
n

L

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

†

CTRDIV16

5CT=0
M1

M2
G3

G4

C5/2,3,4+

1,5D

3CT=15

[1]
[2]
[4]
[8]

CLR

LOAD

ENT
ENP

CLK

1
9

10
7

2

3

A

4

B

5

C

6

D

15

14
13
12
11

RCO

Q

A

Q

B

Q

C

Q

D

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

CD54AC163, CD74AC163

4-BIT SYNCHRONOUS BINARY COUNTERS

SCHS299 – APRIL 2000

LOAD

ENT

ENP

CLK
CLR

9
10

†

7

2
1

3

A

4

B

LD

†

CK

CK

R

LD

M1
G2

1

, 2T/1C3
G4
3D
4R

M1
G2

1

, 2T/1C3
G4
3D
4R

14

13

15

RCO

Q

A

Q

B

M1
G2

1, 2T/1C3

5

C

6

D

†

For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown
on the logic diagram of the D/T flip-flops.

G4
3D
4R

M1
G2

1

, 2T/1C3
G4
3D
4R

12

11

Q

C

Q

D

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

CD54AC163, CD74AC163
4-BIT SYNCHRONOUS BINARY COUNTERS

SCHS299 – APRIL 2000

logic symbol, each D/T flip-flop

M1LD (Load)

G2TE (Toggle Enable)

CK (Clock)

(Inverted Data)

D

R

(Inverted Reset)

1, 2T/1C3

G4

3D

4R

logic diagram, each D/T flip-flop (positive logic)

CK

LD
TE

†

LD

LD

D

R

TG

TG

†

TG

†

CK

TG

CK

Q (Output)

TG

†

CK

†

TG

CK

†

Q

†

The origins of LD

4

and CK are shown in the logic diagram of the overall device.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265