Texas Instruments CD4066BPW, CD4066BNSR, CD4066BM96, CD4066BM, CD4066BF3A Datasheet

SOIC

M

CD4066BM

TSSOP

PW

CM066B

D

15-V Digital or ±7.5-V Peak-to-Peak
Switching

D

125-Ω Typical On-State Resistance for 15-V
Operation

D

Switch On-State Resistance Matched to
Within 5 Ω Over 15-V Signal-Input Range

D

On-State Resistance Flat Over Full
Peak-to-Peak Signal Range

D

High On/Off Output-Voltage Ratio: 80 dB
Typical at f

D

High Degree of Linearity: <0.5% Distortion
Typical at f
V

– VSS ≥ 10 V, RL = 10 kΩ

DD

D

Extremely Low Off-State Switch Leakage,

= 10 kHz, RL = 1 kΩ

is

= 1 kHz, Vis = 5 V p-p,

is

Resulting in Very Low Offset Current and
High Effective Off-State Resistance: 10 pA
Typical at V

D

Extremely High Control Input Impedance

– VSS = 10 V, TA = 25°C

DD

(Control Circuit Isolated From Signal
Circuit): 10

D

Low Crosstalk Between Switches: –50 dB
Typical at f

12

Ω Typical

= 8 MHz, RL = 1 kΩ

is

CMOS QUAD BILATERAL SWITCH

SCHS051C – REVISED FEBRUARY 2003

D

Matched Control-Input to Signal-Output
Capacitance: Reduces Output Signal
Transients

D

Frequency Response, Switch On = 40 MHz
Typical

D

100% Tested for Quiescent Current at 20 V

D

5-V, 10-V, and 15-V Parametric Ratings

D

Meets All Requirements of JEDEC Tentative
Standard No. 13B, Standard Specifications
for Description of B-Series CMOS Devices

D

Applications:
– Analog Signal Switching/Multiplexing:

Signal Gating, Modulator, Squelch
Control, Demodulator, Chopper,

Commutating Switch
– Digital Signal Switching/Multiplexing
– Transmission-Gate Logic Implementation
– Analog-to-Digital and Digital-to-Analog

Conversion
– Digital Control of Frequency, Impedance,

Phase, and Analog-Signal Gain

CD4066B

description/ordering information

T

A

CDIP – F Tube CD4066BF3A CD4066BF3A
PDIP – E Tube CD4066BE CD4066BE

–55°C to 125°C

SOP – NS Tape and reel CD4066BNSR CD4066B

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

E, F, M, NS, OR PW PACKAGE

SIG A IN/OUT
SIG A OUT/IN
SIG B OUT/IN
SIG B IN/OUT

CONTROL B

CONTROL C

V

SS

(TOP VIEW)

1

14

2

13

3

12

4

11

5

10
6
7

ORDERING INFORMATION

PACKAGE

–

–

†

Tube CD4066BM
Tape and reel CD4066BM96

Tube CD4066BPW
Tape and reel CD4066BPWR

V

DD

CONTROL A
CONTROL D
SIG D IN/OUT
SIG D OUT/IN
SIG C OUT/IN

9

SIG C IN/OUT

8

ORDERABLE

PART NUMBER

TOP-SIDE
MARKING

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2003, Texas Instruments Incorporated

1

CD4066B
CMOS QUAD BILATERAL SWITCH

SCHS051C – REVISED FEBRUARY 2003

description/ordering information (continued)

CD4066B is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. It
is pin-for-pin compatible with the CD4016B, but exhibits a much lower on-state resistance. In addition, the
on-state resistance is relatively constant over the full input-signal range.

The CD4066B consists of four bilateral switches, each with independent controls. Both the p and the n devices
in a given switch are biased on or off simultaneously by the control signal. As shown in Figure 1, the well of the
n-channel device on each switch is tied to either the input, when the switch is on, or to V
off. This configuration eliminates the variation of the switch-transistor threshold voltage with input signal and,
thus, keeps the on-state resistance low over the full operating-signal range.

The advantages over single-channel switches include peak input-signal voltage swings equal to the full supply
voltage and more constant on-state impedance over the input-signal range. However, for sample-and-hold
applications, the CD4016B is recommended.

Switch

Control

IN

V

is

when the switch is

SS

p

n

p

OUT

V

os

n

CONTROL

†

V

C

†

All control inputs are protected by CMOS protection network.

NOTES: A. All p substrates are connected to VDD.

B. Normal operation control-line biasing: Switch on (logic 1), VC = VDD; Switch off (logic 0), VC = V
C. Signal-level range: VSS ≤ Vis ≤ V

DD

n

V

SS

V

DD

V

SS

SS

Figure 1. Schematic Diagram of One-of-Four Identical Switches and Associated Control Circuitry

92CS - 29113

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

VDDSupply voltage

318V

CD4066B

CMOS QUAD BILATERAL SWITCH

SCHS051C – REVISED FEBRUARY 2003

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

DC supply-voltage range, (V
Input voltage range, V
DC input current, I

, all inputs –0.5 V to VDD + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

is

, any one input ±10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IN

Package thermal impedance, θ

) (voltages referenced to VSS terminal) –0.5 V to 20 V. . . . . . . . . . . . . . . . . .

DD

(see Note 1): E package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

†

M package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature (during soldering):

At distance 1/16 ± 1/32 inch (1,59 ± 0,79 mm) from case for 10 s max 265°C. . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions

MIN MAX UNIT

pp

T

Operating free-air temperature

A

–55

125 °C

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

CD4066B

IN

55°C–40°C

85°C

125°C

I

A

(

)

R

L

returned

()
On state resistance

Pro agation delay

V

SS

GND, C

L

t)

(

V

C

V

SS

V

CMOS QUAD BILATERAL SWITCH

SCHS051C – REVISED FEBRUARY 2003

electrical characteristics

PARAMETER TEST CONDITIONS

Quiescent device

DD

current

Signal Inputs (Vis) and Output (Vos)

VC = V

DD

On-state resistance

r

on

max

∆r

on

THD

I

is

t

pd

C

is

C

os

C

ios

­difference between
any two switches

Total harmonic
distortion

–3-dB cutoff
frequency (switch
on)

–50-dB feed-through
frequency (switch off)

Input/output leakage
current (switch off)
(max)

–50-dB crosstalk
frequency

p
(signal input to signal
outpu

Input capacitance
Output
Feed through

= 10 kΩ

to VDD – V

Vis = VSS to V

RL = 10 kΩ, VC = V

VC = VDD = 5 V, VSS = –5 V,
V

is(p-p)

(sine wave centered on 0 V),
RL = 10 kΩ,
fis = 1-kHz sine wave

VC = VDD = 5 V , VSS = –5 V , V
(sine wave centered on 0 V),
RL = 1 kΩ

VC = VSS = –5 V, V
(sine wave centered on 0 V),
RL = 1 kΩ

VC = 0 V, Vis = 18 V, Vos = 0 V;
and
VC = 0 V, Vis = 0 V, Vos = 18 V

VC(A) = VDD = 5 V,
VC(B) = VSS = –5 V,
Vis(A) = 5 V
RL = 1 kΩ

RL = 200 kΩ, VC = VDD,

Vis = 10 V

square wave centered on 5 V),

tr, tf = 20 ns

VDD = 5 V

=

=

SS

2

= 5 V

p-p

= –5

DD

, 50-Ω source,

= 50 F,

–

DD

is(p-p)

p

LIMITS AT INDICATED TEMPERATURES

V

V

(V)DD(V)

0, 5 5 0.25 0.25 7.5 7.5 0.01 0.25
0, 10 10 0.5 0.5 15 15 0.01 0.5
0, 15 15 1 1 30 30 0.01 1
0, 20 20 5 5 150 150 0.02 5

is(p-p)

= 5 V

–

5 800 850 1200 1300 470 1050
10 310 330 500 550 180 400
15 200 210 300 320 125 240

5 15
10 10
15 5

= 5 V

18 ±0.1 ±0.1 ±1 ±1 ±10

5 20 40
10 10 20
15 7 15

°

25°C

TYP MAX

0.4 %

40 MHz

1 MHz

–5

8 MHz

8
8

0.5

UNIT

µ

Ω

Ω

±0.1 µA

ns

pF

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265