Datasheet CD4066BPW, CD4066BNSR, CD4066BM96, CD4066BM, CD4066BF3A Datasheet (Texas Instruments)

SOIC

M

CD4066BM

TSSOP

PW

CM066B

D

15-V Digital or ±7.5-V Peak-to-Peak
Switching

D

125-Ω Typical On-State Resistance for 15-V
Operation

D

Switch On-State Resistance Matched to
Within 5 Ω Over 15-V Signal-Input Range

D

On-State Resistance Flat Over Full
Peak-to-Peak Signal Range

D

High On/Off Output-Voltage Ratio: 80 dB
Typical at f

D

High Degree of Linearity: <0.5% Distortion
Typical at f
V

– VSS ≥ 10 V, RL = 10 kΩ

DD

D

Extremely Low Off-State Switch Leakage,

= 10 kHz, RL = 1 kΩ

is

= 1 kHz, Vis = 5 V p-p,

is

Resulting in Very Low Offset Current and
High Effective Off-State Resistance: 10 pA
Typical at V

D

Extremely High Control Input Impedance

– VSS = 10 V, TA = 25°C

DD

(Control Circuit Isolated From Signal
Circuit): 10

D

Low Crosstalk Between Switches: –50 dB
Typical at f

12

Ω Typical

= 8 MHz, RL = 1 kΩ

is

CMOS QUAD BILATERAL SWITCH

SCHS051C – REVISED FEBRUARY 2003

D

Matched Control-Input to Signal-Output
Capacitance: Reduces Output Signal
Transients

D

Frequency Response, Switch On = 40 MHz
Typical

D

100% Tested for Quiescent Current at 20 V

D

5-V, 10-V, and 15-V Parametric Ratings

D

Meets All Requirements of JEDEC Tentative
Standard No. 13B, Standard Specifications
for Description of B-Series CMOS Devices

D

Applications:
– Analog Signal Switching/Multiplexing:

Signal Gating, Modulator, Squelch
Control, Demodulator, Chopper,

Commutating Switch
– Digital Signal Switching/Multiplexing
– Transmission-Gate Logic Implementation
– Analog-to-Digital and Digital-to-Analog

Conversion
– Digital Control of Frequency, Impedance,

Phase, and Analog-Signal Gain

CD4066B

description/ordering information

T

A

CDIP – F Tube CD4066BF3A CD4066BF3A
PDIP – E Tube CD4066BE CD4066BE

–55°C to 125°C

SOP – NS Tape and reel CD4066BNSR CD4066B

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

E, F, M, NS, OR PW PACKAGE

SIG A IN/OUT
SIG A OUT/IN
SIG B OUT/IN
SIG B IN/OUT

CONTROL B

CONTROL C

V

SS

(TOP VIEW)

1

14

2

13

3

12

4

11

5

10
6
7

ORDERING INFORMATION

PACKAGE

–

–

†

Tube CD4066BM
Tape and reel CD4066BM96

Tube CD4066BPW
Tape and reel CD4066BPWR

V

DD

CONTROL A
CONTROL D
SIG D IN/OUT
SIG D OUT/IN
SIG C OUT/IN

9

SIG C IN/OUT

8

ORDERABLE

PART NUMBER

TOP-SIDE
MARKING

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2003, Texas Instruments Incorporated

1

CD4066B
CMOS QUAD BILATERAL SWITCH

SCHS051C – REVISED FEBRUARY 2003

description/ordering information (continued)

CD4066B is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. It
is pin-for-pin compatible with the CD4016B, but exhibits a much lower on-state resistance. In addition, the
on-state resistance is relatively constant over the full input-signal range.

The CD4066B consists of four bilateral switches, each with independent controls. Both the p and the n devices
in a given switch are biased on or off simultaneously by the control signal. As shown in Figure 1, the well of the
n-channel device on each switch is tied to either the input, when the switch is on, or to V
off. This configuration eliminates the variation of the switch-transistor threshold voltage with input signal and,
thus, keeps the on-state resistance low over the full operating-signal range.

The advantages over single-channel switches include peak input-signal voltage swings equal to the full supply
voltage and more constant on-state impedance over the input-signal range. However, for sample-and-hold
applications, the CD4016B is recommended.

Switch

Control

IN

V

is

when the switch is

SS

p

n

p

OUT

V

os

n

CONTROL

†

V

C

†

All control inputs are protected by CMOS protection network.

NOTES: A. All p substrates are connected to VDD.

B. Normal operation control-line biasing: Switch on (logic 1), VC = VDD; Switch off (logic 0), VC = V
C. Signal-level range: VSS ≤ Vis ≤ V

DD

n

V

SS

V

DD

V

SS

SS

Figure 1. Schematic Diagram of One-of-Four Identical Switches and Associated Control Circuitry

92CS - 29113

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

VDDSupply voltage

318V

CD4066B

CMOS QUAD BILATERAL SWITCH

SCHS051C – REVISED FEBRUARY 2003

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

DC supply-voltage range, (V
Input voltage range, V
DC input current, I

, all inputs –0.5 V to VDD + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

is

, any one input ±10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IN

Package thermal impedance, θ

) (voltages referenced to VSS terminal) –0.5 V to 20 V. . . . . . . . . . . . . . . . . .

DD

(see Note 1): E package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

†

M package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature (during soldering):

At distance 1/16 ± 1/32 inch (1,59 ± 0,79 mm) from case for 10 s max 265°C. . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions

MIN MAX UNIT

pp

T

Operating free-air temperature

A

–55

125 °C

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

CD4066B

IN

55°C–40°C

85°C

125°C

I

A

(

)

R

L

returned

()
On state resistance

Pro agation delay

V

SS

GND, C

L

t)

(

V

C

V

SS

V

CMOS QUAD BILATERAL SWITCH

SCHS051C – REVISED FEBRUARY 2003

electrical characteristics

PARAMETER TEST CONDITIONS

Quiescent device

DD

current

Signal Inputs (Vis) and Output (Vos)

VC = V

DD

On-state resistance

r

on

max

∆r

on

THD

I

is

t

pd

C

is

C

os

C

ios

­difference between
any two switches

Total harmonic
distortion

–3-dB cutoff
frequency (switch
on)

–50-dB feed-through
frequency (switch off)

Input/output leakage
current (switch off)
(max)

–50-dB crosstalk
frequency

p
(signal input to signal
outpu

Input capacitance
Output
Feed through

= 10 kΩ

to VDD – V

Vis = VSS to V

RL = 10 kΩ, VC = V

VC = VDD = 5 V, VSS = –5 V,
V

is(p-p)

(sine wave centered on 0 V),
RL = 10 kΩ,
fis = 1-kHz sine wave

VC = VDD = 5 V , VSS = –5 V , V
(sine wave centered on 0 V),
RL = 1 kΩ

VC = VSS = –5 V, V
(sine wave centered on 0 V),
RL = 1 kΩ

VC = 0 V, Vis = 18 V, Vos = 0 V;
and
VC = 0 V, Vis = 0 V, Vos = 18 V

VC(A) = VDD = 5 V,
VC(B) = VSS = –5 V,
Vis(A) = 5 V
RL = 1 kΩ

RL = 200 kΩ, VC = VDD,

Vis = 10 V

square wave centered on 5 V),

tr, tf = 20 ns

VDD = 5 V

=

=

SS

2

= 5 V

p-p

= –5

DD

, 50-Ω source,

= 50 F,

–

DD

is(p-p)

p

LIMITS AT INDICATED TEMPERATURES

V

V

(V)DD(V)

0, 5 5 0.25 0.25 7.5 7.5 0.01 0.25
0, 10 10 0.5 0.5 15 15 0.01 0.5
0, 15 15 1 1 30 30 0.01 1
0, 20 20 5 5 150 150 0.02 5

is(p-p)

= 5 V

–

5 800 850 1200 1300 470 1050
10 310 330 500 550 180 400
15 200 210 300 320 125 240

5 15
10 10
15 5

= 5 V

18 ±0.1 ±0.1 ±1 ±1 ±10

5 20 40
10 10 20
15 7 15

°

25°C

TYP MAX

0.4 %

40 MHz

1 MHz

–5

8 MHz

8
8

0.5

UNIT

µ

Ω

Ω

±0.1 µA

ns

pF

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DD

55°C–40°C

85°C

125°C

|Iis| < 10 µA

low voltage (max)

high voltage

ro agation delay

C

L

R

L

kΩ

R

L

GND, C

L

t

t

20

OUTPUT, V

()

CD4066B

CMOS QUAD BILATERAL SWITCH

SCHS051C – REVISED FEBRUARY 2003

electrical characteristics (continued)

LIMITS AT INDICATED TEMPERATURES

CHARACTERISTIC TEST CONDITIONS

Control (VC)

Control input,

V

ILC

Control input,

V

IHC

I

Input current (MAX)

IN

Crosstalk (control input
to signal output)

Turn-on and turn-off
p

p

Maximum control input
repetition rate

CIInput capacitance 5 7.5 pF

Vis = VSS, VOS = VDD, and
Vis = VDD, VOS = V

See Figure 6

Vis ≤ VDD, VDD – VSS = 18 V,
VCC ≤ VDD – V

VC = 10 V (square wave),
tr, tf = 20 ns, RL = 10 kΩ

VIN = VDD, tr, tf = 20 ns,

= 50 F,

Vis = VDD, VSS = GND,

= 1 kΩ to
VC = 10 V (square wave
centered on 5 V),
Vos = 1/2 Vos at 1 kHz

,

SS

SS

p

= 1

= 50 F,

ns,

,

=

r

f

V

–

(V)

5 1 1 1 1 1
10 2 2 2 2 2
15 2 2 2 2 2

5 3.5 (MIN)
10 7 (MIN)
15 11 (MIN)

18 ±0.1 ±0.1 ±1 ±1 ±10

10 50 mV

5 35 70
10 20 40
15 15 30

p

5 6
10 9
15 9.5

°

25°C

TYP MAX

–5

±0.1 µA

UNIT

V

V

ns

MHz

switching characteristics

V

DD

(V)

5 0 0.64 0.61 0.51 0.42 0.36

5 5 –0.64 –0.61 –0.51 –0.42 –0.36 4.6
10 0 1.6 1.5 1.3 1.1 0.9
10 10 –1.6 –1.5 –1.3 –1.1 –0.9 9.5
15 0 4.2 4 3.4 2.8 2.4
15 15 –4.2 –4 –3.4 –2.8 –2.4 13.5

V
(V)

SWITCH INPUT

is

–55°C –40°C 25°C 85°C 125°C MIN MAX

Iis (mA)

SWITCH

(V)

os

0.4

0.5

1.5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

CD4066B
CMOS QUAD BILATERAL SWITCH

SCHS051C – REVISED FEBRUARY 2003

TYPICAL CHARACTERISTICS

TYPICAL ON-STATE RESISTANCE

vs

INPUT SIGNAL VOLTAGE (ALL TYPES)

Supply Voltage (VDD – VSS) = 5 V

600

Ω

500

400

300

200

100

– Channel On-State Resistance –

0

on

r

–4 –3 –2 –101 234

Vis – Input Signal Voltage – V

TA = 125°C

+25°C

Figure 2

TYPICAL ON-STATE RESISTANCE

vs

INPUT SIGNAL VOLTAGE (ALL TYPES)

Ω

Supply Voltage (VDD – VSS) = 15 V

300

–55°C

92CS-27326RI

TYPICAL ON-STATE

vs

INPUT SIGNAL VOLTAGE (ALL TYPES)

300

Supply Voltage (VDD – VSS) = 10 V

Ω

250

200

150

100

50

– Channel On-State Resistance –

0

on

r

–10 –7.5 –5 –2.5 0 2.5 5 7.5 10

Vis – Input Signal Voltage – V

TA = 125°C

+25°C

–55°C

Figure 3

ON-STATE RESISTANCE

vs

INPUT SIGNAL VOLTAGE (ALL TYPES)

Ω

TA = 125°C

600

92CS-27327RI

250

200

TA = 125°C

150

100

50

– Channel On-State Resistance –

0

on

–10 –7.5 –5 –2.5 0 2.5 5 7.5 10

r

Vis – Input Signal Voltage – V

Figure 4

+25°C
–55°C

92CS-27329RI

500

400

300

200

100

– Channel On-State Resistance –

0

on

r

–10 –7.5 –5 –2.5 0 2.5 5 7.5 10

Supply Voltage (VDD – VSS) = 5 V

Vis – Input Signal Voltage – V

Figure 5

10 V

–15 V

92CS-27330RI

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CD4066B

CMOS QUAD BILATERAL SWITCH

SCHS051C – REVISED FEBRUARY 2003

TYPICAL CHARACTERISTICS

I

V

is

is

CD4066B

1 of 4 Switches

|Vis – Vos|

ron =

|Iis|

V

os

92CS - 30966

Figure 6. Determination of ron as a Test Condition for Control-Input High-Voltage (V

Keithley

160 Digital

Multimeter

1-kΩ

Range

Y

X–Y

Plotter

H. P.
Moseley
7030A

X

10 kΩ

V

DD

TG
on

V

SS

Figure 7. Channel On-State Resistance Measurement Circuit

POWER DISSIPATION PER PACKAGE

TYPICAL ON CHARACTERISTICS

FOR 1 OF 4 CHANNELS

3

2

1

0

Output Voltage – V

–1

O

V –

VC = V

V

is

–2

All unused terminals are

–3

–3 –2 –101234

connected to V

DD

CD4066B

1 of 4

Switches

V

SS

SS

V

DD

V

os

VI – Input Voltage – V

92CS - 30919

Figure 8

SWITCHING FREQUENCY

4

10

6

TA = 25°C

4

µ

2

3

10

6
4

2

2

10

6
4

2

1

Power Dissipation Per Package – W

D

P –

10

10

6
4

2

10

R

L

Supply Voltage

(VDD) = 15 V

f – Switching Frequency – kHz

vs

10 V

5 V

10

Figure 9

) Specification

IHC

246246

2

92CS - 22716

14

5
6

CD4066B

12
13

7

92CS -30920

V

DD

V

SS

3

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

CD4066B
CMOS QUAD BILATERAL SWITCH

SCHS051C – REVISED FEBRUARY 2003

TYPICAL CHARACTERISTICS

C

ios

CD4066B

1 of 4

Switches

VDD = 5 V

V

C

os

92CS -30921

VC = –5 V

C

is

Measured on Boonton capacitance bridge, model 75a (1 MHz);
test-fixture capacitance nulled out.

VSS = –5

Figure 10. T ypical On Characteristics

for One of Four Channels

V

VC = V

DD

V

is

V

V

DD

tr = tf = 20 ns

All unused terminals are connected to VSS.

DD

CD4066B

1 of 4

Switches

50 pF

SS

V

os

200 kΩ

92CS-30923

V

VC = V

SS

Vis = V

DD

All unused terminals are connected to VSS.

DD

CD4066B

1 of 4

Switches

V

SS

V

os

I

92CS-30922

Figure 11. Off-Switch Input or Output Leakage

+10 V

tr = tf = 20 ns

All unused terminals are connected to VSS.

1 kΩ

V

C

V

is

V

DD

CD4066B

1 of 4

Switches

V

SS

V

os

10 kΩ

92CS-30924

Figure 12. Propagation Delay-Time Signal Input

) to Signal Output (Vos)

(V

is

Figure 13. Crosstalk-Control Input to Signal

Output

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CD4066B

CMOS QUAD BILATERAL SWITCH

SCHS051C – REVISED FEBRUARY 2003

TYPICAL CHARACTERISTICS

V

C

tr = tf = 20 ns

V

os

V

DD

tr = tf = 20 ns

NOTES: A. All unused terminals are connected to VSS.

B. Delay is measured at Vos level of +10% from ground

(turn-on) or on-state output level (turn-off).

Figure 14. Propagation Delay, t

t

r

90%

10%

50%

Rep Rate

VC = V

t

f

DD
DD

CD4066B

Switches

V

PLH

1 of 4

SS

, t

V

V

DD

V

os

50 pF

Control-Signal Output

PHL

1 kΩ

VOS+

10 V

0 V

V

@1kHz

OS

92CS-30925

2

VDD = 10 V

V

C

Vis = 10 V

All unused terminals are connected to V

CD4066B

Switches

V

SS

Figure 15. Maximum Allowable Control-Input Repetition Rate

1 of 4

SS

V

OS

50 pF

+

V

OS

@1kHz

2

1 kΩ

92CS-30925

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9

CD4066B
CMOS QUAD BILATERAL SWITCH

SCHS051C – REVISED FEBRUARY 2003

TYPICAL CHARACTERISTICS

V

DD

V

SS

V

DD

Inputs

I

Clock

Reset

3

1/3 CD4049B

5

Signal
Inputs

Package Count

2 - CD4001B
1 - CD4049B
3 - CD4066B
2 - CD4018B

10237912

14

PEJ1J2J3J4J

Q

2Q1

54

2

4

CD4018B

15

1

Channel 1
Channel 2
Channel 3
Channel 4

V

SS

Measure inputs sequentially, to both VDD and
inputs to either VDD or VSS. Measure control inputs only.

Figure 16. Input Leakage-Current Test Circuit

Clock

5

1
2

5
6

8

9

12
13

Maximum
Allowable

Signal Level

1

3

4

CD4001B

10

11
12

1
4
8

11

Clock

External

13

1/4 CD4066B

513

6

CD4066B

Chan 1 Chan 2 Chan 3 Chan 4

Reset

2

2
3
9

10

10 kΩ

14
15

1

7

1/3 CD4049B

9

11 12

1/6 CD4049B

1/4 CD4066B

4

V

DD

30% (VDD – VSS)
V

SS

92CS-27555

. Connect all unused

VSS

10 2 3 7 9 12

PEJ1J2J3J4J

CD4018B

Q

2Q1

54

6

10

5

1
4

3

8

11

5

13 12 9 8 6 5 2 1

CD4001B

10 4

11

12 6 5 11

Channel 1

LPF

2

Ω

10 k

LPF

10 kΩ

LPF

10 kΩ

LPF

10 kΩ

Channel 2

Channel 3

Channel 4

3

CD4066B

9

10

3

Signal
Outputs

10

92CM - 30928

Figure 17. Four-Channel PAM Multiplex System Diagram

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CD4066B

CMOS QUAD BILATERAL SWITCH

SCHS051C – REVISED FEBRUARY 2003

TYPICAL CHARACTERISTICS

5 V

O

IN

5 V

–5 V

VDD = 5 V

CD4054B

Digital
Control
Inputs

VSS = 0 V

VEE = –5 V

Analog Inputs (±5 V)

0

SW

A

Analog Outputs (±5 V)

CD4066B

SW

B

SW

VDD = 5 V

C

SW

D

VSS = –5 V

Figure 18. Bidirectional Signal Transmission Via Digital Control Logic

92CS - 30927

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

11

CD4066B
CMOS QUAD BILATERAL SWITCH

SCHS051C – REVISED FEBRUARY 2003

APPLICATION INFORMATION

In applications that employ separate power sources to drive VDD and the signal inputs, the VDD current capability
should exceed V

DD/RL

avoids any permanent current flow or clamp action on the V
the CD4066B.

(R

= effective external load of the four CD4066B bilateral switches). This provision

L

supply when power is applied or removed from

DD

In certain applications, the external load-resistor current can include both V
avoid drawing V
bidirectional switch must not exceed 0.8 V (calculated from r

No V

current will flow through RL if the switch current flows into terminals 2, 3, 9, or 10.

DD

current when switch current flows into terminals 1, 4, 8, or 1 1, the voltage drop across the

DD

values shown).

on

and signal-line components. T o

DD

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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accordance with TI’s standard warranty . Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty . Except where mandated by government requirements, testing of all
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Copyright  2003, Texas Instruments Incorporated