Texas instruments CD4066B User Manual

E, F, M, NS, OR PW PACKAGE

D

15-V Digital or ±7.5-V Peak-to-Peak
Switching

D

125-Ω Typical On-State Resistance for 15-V
Operation

D

Switch On-State Resistance Matched to
Within 5 Ω Over 15-V Signal-Input Range

D

On-State Resistance Flat Over Full
Peak-to-Peak Signal Range

D

High On/Off Output-Voltage Ratio: 80 dB
Typical at f

D

High Degree of Linearity: <0.5% Distortion
Typical at f
V

– VSS ≥ 10 V, RL = 10 kΩ

DD

D

Extremely Low Off-State Switch Leakage,
Resulting in Very Low Offset Current and
High Effective Off-State Resistance: 10 pA
Typical at V

D

Extremely High Control Input Impedance
(Control Circuit Isolated From Signal
Circuit): 10

D

Low Crosstalk Between Switches: –50 dB
Typical at f

= 10 kHz, RL = 1 kΩ

is

= 1 kHz, Vis = 5 V p-p,

is

– VSS = 10 V, TA = 25°C

DD

12

Ω Typical

= 8 MHz, RL = 1 kΩ

is

CMOS QUAD BILATERAL SWITCH

SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003

D

Matched Control-Input to Signal-Output
Capacitance: Reduces Output Signal
Transients

D

Frequency Response, Switch On = 40 MHz
Typical

D

100% Tested for Quiescent Current at 20 V

D

5-V, 10-V, and 15-V Parametric Ratings

D

Meets All Requirements of JEDEC Tentative
Standard No. 13-B, Standard Specifications

for Description of “B” Series CMOS
Devices

D

Applications:
– Analog Signal Switching/Multiplexing:

Signal Gating, Modulator, Squelch
Control, Demodulator, Chopper,

Commutating Switch
– Digital Signal Switching/Multiplexing
– Transmission-Gate Logic Implementation
– Analog-to-Digital and Digital-to-Analog

Conversion
– Digital Control of Frequency, Impedance,

Phase, and Analog-Signal Gain

CD4066B

(TOP VIEW)

1

SIG A IN/OUT
SIG A OUT/IN
SIG B OUT/IN
SIG B IN/OUT

CONTROL B
CONTROL C

V

SS

14

V

2
3
4
5
6
7

DD

13

CONTROL A

12

CONTROL D

11

SIG D IN/OUT

10

SIG D OUT/IN
SIG C OUT/IN

9

SIG C IN/OUT

8

description/ordering information

The CD4066B is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals.
It is pin-for-pin compatible with the CD4016B, but exhibits a much lower on-state resistance. In addition, the
on-state resistance is relatively constant over the full signal-input range.

The CD4066B consists of four bilateral switches, each with independent controls. Both the p and the n devices
in a given switch are biased on or off simultaneously by the control signal. As shown in Figure 1, the well of the
n-channel device on each switch is tied to either the input (when the switch is on) or to V
is off). This configuration eliminates the variation of the switch-transistor threshold voltage with input signal and,
thus, keeps the on-state resistance low over the full operating-signal range.

The advantages over single-channel switches include peak input-signal voltage swings equal to the full supply
voltage and more constant on-state impedance over the input-signal range. However, for sample-and-hold
applications, the CD4016B is recommended.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

(when the switch

SS

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2003, Texas Instruments Incorporated

1

CD4066B

SOIC – M

CD4066BM

–55°C to 125°C

TSSOP – PW

CM066B

SS

DD

Switch

CMOS QUAD BILATERAL SWITCH

SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003

description/ordering information (continued)

ORDERING INFORMATION

T

A

CDIP – F Tube of 25 CD4066BF3A CD4066BF3A
PDIP – E Tube of 25 CD4066BE CD4066BE

SOP – NS Reel of 2000 CD4066BNSR CD4066B

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.

PACKAGE

Tube of 50 CD4066BM
Reel of 2500 CD4066BM96
Reel of 250 CD4066BMT

Tube of 90 CD4066BPW
Reel of 2000 CD4066BPWR

†

ORDERABLE

PART NUMBER

TOP-SIDE
MARKING

Control

Control

†

V

C

†

All control inputs are protected by the CMOS protection network.

NOTES: A. All p substrates are connected to VDD.

B. Normal operation control-line biasing: switch on (logic 1), VC = VDD; switch off (logic 0), VC = V
C. Signal-level range: V

≤ Vis ≤ V

In
V

is

p

n

p

Out
V

n

n

V

SS

os

V

DD

V

SS

SS

92CS-29113

2

Figure 1. Schematic Diagram of One-of-Four Identical Switches and Associated Control Circuitry

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CD4066B

CMOS QUAD BILATERAL SWITCH

SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

DC supply-voltage range, V
Input voltage range, V
DC input current, I

(all inputs) –0.5 V to VDD + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

is

(any one input) ±10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IN

Package thermal impedance, θ

(voltages referenced to VSS terminal) –0.5 V to 20 V. . . . . . . . . . . . . . . . . . . .

DD

(see Note 1): E package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

†

M package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature (during soldering):

At distance 1/16 ± 1/32 inch (1,59 ± 0,79 mm) from case for 10 s max 265°C. . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions

MIN MAX UNIT

V
T

Supply voltage 3 18 V

DD

Operating free-air temperature

A

–55

125 °C

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

CD4066B

PARAMETER

TEST CONDITIONS

V

V

UNIT

V

IN

V

DD

–55°C

–40°C

85°C

125°C

Quiescent device

I

DD

Quiescent device

A

VC = VDD,
R

= 10 kΩ returned

r

On-state resistance

RL = 10 k returned

to ,

2

r

on

On-state resistance
RL = 10 kΩ, VC = V

DD

on

L CDD

RL = 200 k

VC = VDD,

t

Propagation delay

VSS = GND, CL = 50 pF,

ns

signal output)

(square wave centered on 5 V),

CMOS QUAD BILATERAL SWITCH

SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003

electrical characteristics

current

Signal Inputs (Vis) and Outputs (Vos)

on

(max)

∆

difference between
any two switches

Total harmonic

THD

distortion
–3-dB cutoff

frequency
(switch on)

–50-dB feedthrough
frequency (switch off)

Input/output leakage
current (switch off)

I

is

(max)

–50-dB crosstalk
frequency

ǒ

VDD*

to ,
Vis = VSS to V

VC = VDD = 5 V, VSS = –5 V,
V

is(p-p)

RL = 10 kΩ, fis = 1-kHz sine wave
VC = VDD = 5 V , VSS = –5 V , V

(sine wave centered on 0 V), RL = 1 kΩ
VC = VSS = –5 V, V

(sine wave centered on 0 V), RL = 1 kΩ
VC = 0 V, Vis = 18 V, Vos = 0 V;

and
VC = 0 V, Vis = 0 V, Vos = 18 V

VC(A) = VDD = 5 V,
VC(B) = VSS = –5 V,
Vis(A) = 5 V
RL = 1 kΩ

Ǔ

V

SS

DD

= 5 V (sine wave centered on 0 V),

is(p-p)

, 50-Ω source,

p-p

Ω,

LIMITS AT INDICATED TEMPERATURES

(V)

(V)

0, 5 5 0.25 0.25 7.5 7.5 0.01 0.25
0, 10 10 0.5 0.5 15 15 0.01 0.5
0, 15 15 1 1 30 30 0.01 1
0, 20 20 5 5 150 150 0.02 5

5 800 850 1200 1300 470 1050

10 310 330 500 550 180 400

15 200 210 300 320 125 240

5 15
10 10
15 5

= 5 V

is(p-p)

= 5 V

18 ±0.1 ±0.1 ±1 ±1 ±10

5 20 40

°

25°C

TYP MAX

0.4 %

40 MHz

1 MHz

–5

8 MHz

µ

Ω

Ω

±0.1 µA

(signal input to

pd

C

Input capacitance VDD = 5 V, VC = VSS = –5 V 8 pF

is

C

Output capacitance VDD = 5 V, VC = VSS = –5 V 8 pF

os

C

Feedthrough VDD = 5 V, VC = VSS = –5 V 0.5 pF

ios

4

Vis = 10 V

tr, tf = 20 ns

10 10 20
15 7 15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics (continued)

CHARACTERISTIC

TEST CONDITIONS

V

UNIT

V

DD

–55°C

–40°C

85°C

125°C

V

ILC

Control input,

|Iis| < 10 µA,

V

ILC

low voltage (max)

is SS OS DD

V

IHC

Control input,
See Figure 6

V

IHC

high voltage

Turn-on and turn-off

VIN = VDD, tr, tf = 20 ns,

ns

propagation delay

CL = 50 pF, RL = 1 kΩ

Vis = VDD, VSS = GND,

Maximum control input
repetition rate

RL = 1 kΩ to GND, CL = 50 pF,

MHz

repetition rate
centered on 5 V), tr, tf = 20 ns,

SWITCH

V

V

is

OUTPUT, V

os

(V)

is

(V)

Control (VC)

Vis = VSS, VOS = VDD, and
Vis = VDD, VOS = V

I

Input current (max)

IN

Crosstalk (control input
to signal output)

Vis ≤ VDD, VDD – VSS = 18 V,
VCC ≤ VDD – V

VC = 10 V (square wave),
tr, tf = 20 ns, RL = 10 kΩ

SS

SS

CD4066B

CMOS QUAD BILATERAL SWITCH

SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003

LIMITS AT INDICATED TEMPERATURES

(V)

5 1 1 1 1 1
10 2 2 2 2 2
15 2 2 2 2 2

5 3.5 (MIN)
10 7 (MIN)
15 11 (MIN)

18 ±0.1 ±0.1 ±1 ±1 ±10

10 50 mV

5 35 70
10 20 40
15 15 30

5 6

°

25°C

TYP MAX

–5

±0.1 µA

VC = 10 V (square wave

Vos = 1/2 Vos at 1 kHz

CIInput capacitance 5 7.5 pF

10 9
15 9.5

switching characteristics

SWITCH INPUT

DD

(V)

–55°C –40°C 25°C 85°C 125°C MIN MAX

5 0 0.64 0.61 0.51 0.42 0.36

5 5 –0.64 –0.61 –0.51 –0.42 –0.36 4.6
10 0 1.6 1.5 1.3 1.1 0.9
10 10 –1.6 –1.5 –1.3 –1.1 –0.9 9.5
15 0 4.2 4 3.4 2.8 2.4
15 15 –4.2 –4 –3.4 –2.8 –2.4 13.5

Iis (mA)

(V)

0.4

0.5

1.5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

CD4066B
CMOS QUAD BILATERAL SWITCH

SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003

TYPICAL CHARACTERISTICS

TYPICAL ON-STATE RESISTANCE

vs

INPUT SIGNAL VOLTAGE (ALL TYPES)

Supply Voltage (VDD – VSS) = 5 V

600

Ω

500

400

300

200

100

– Channel On-State Resistance –

0

on

r

–4 –3 –2 –1 0 1 2 3 4

Vis – Input Signal Voltage – V

TA = 125°C

Figure 2

TYPICAL ON-STATE RESISTANCE

vs

INPUT SIGNAL VOLTAGE (ALL TYPES)

Ω

Supply Voltage (VDD – VSS) = 15 V

300

+25°C

–55°C

92CS-27326RI

TYPICAL ON-STATE RESISTANCE

vs

INPUT SIGNAL VOLTAGE (ALL TYPES)

300

Supply Voltage (VDD – VSS) = 10 V

Ω

250

200

150

100

50

– Channel On-State Resistance –

0

on

r

–10 –7.5 –5 –2.5 0 2.5 5 7.5 10

Vis – Input Signal Voltage – V

TA = 125°C

+25°C

–55°C

Figure 3

TYPICAL ON-STATE RESISTANCE

vs

INPUT SIGNAL VOLTAGE (ALL TYPES)

Ω

TA = 125°C

600

92CS-27327RI

250

200

TA = 125°C

150

100

50

– Channel On-State Resistance –

0

on

–10 –7.5 –5 –2.5 0 2.5 5 7.5 10

r

Vis – Input Signal Voltage – V

Figure 4

+25°C
–55°C

92CS-27329RI

500

400

300

200

100

– Channel On-State Resistance –

0

on

r

–10 –7.5 –5 –2.5 0 2.5 5 7.5 10

Supply Voltage (VDD – VSS) = 5 V

Vis – Input Signal Voltage – V

Figure 5

10 V

–15 V

92CS-27330RI

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CD4066B

3

POWER DISSIPATION PER PACKAGE

Power Dissipation Per Package – W

P –

CMOS QUAD BILATERAL SWITCH

SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003

TYPICAL CHARACTERISTICS

I

V

is

is

CD4066B

1 of 4 Switches

|Vis – Vos|

ron =

|Iis|

V

os

92CS-30966

Figure 6. Determination of ron as a Test Condition for Control-Input High-Voltage (V

Keithley

160 Digital

Multimeter

1-kΩ

Range

Y

X-Y

Plotter

X

10 kΩ

V

DD

TG
On

V

SS

Figure 7. Channel On-State Resistance Measurement Circuit

TYPICAL ON CHARACTERISTICS

FOR 1 OF 4 CHANNELS

3

2

1

0

Output Voltage – V

–1

O

V –

–2

–3

–3 –2 –1 0 1 2 3 4

VI – Input Voltage – V

DD

CD4066B

1 of 4

Switches

V

SS

SS

V

DD

V

92CS-30919

VC = V

V

is

All unused terminals are
connected to V

4

10

6

TA = 25°C

4

µ

2

3

10

6
4

2

2

10

6
4

os

R

L

2

1

10

6
4

2

D

10

10

SWITCHING FREQUENCY

Supply Voltage

(VDD) = 15 V

f – Switching Frequency – kHz

Figure 8

H. P.
Moseley
7030A

vs

10 V

10

Figure 9

5 V

) Specification

IHC

246246

2

92CS-22716

14

5
6

CD4066B

12
13

V

DD

7

V

SS

92C-30920

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

CD4066B

C

V

2

V

is

+10 V

CMOS QUAD BILATERAL SWITCH

SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003

TYPICAL CHARACTERISTICS

ios

CD4066B

1 of 4

Switches

VDD = 5 V

V

C

os

92CS-30921

VC = –5 V

C

is

Measured on Boonton capacitance bridge, model 75a (1 MHz);
test-fixture capacitance nulled out.

VSS = –5

Figure 10. T ypical On Characteristics

for One of Four Channels

VC = V

DD

V

is

V

V

DD

tr = tf = 20 ns

All unused terminals are connected to VSS.

DD

CD4066B

1 of 4

Switches

50 pF

SS

V

os

200 kΩ

92CS-30923

VC = V

SS

Vis = V

DD

All unused terminals are connected to VSS.

DD

CD4066B

1 of 4

Switches

V

SS

V

os

I

92CS-3092

Figure 11. Off-Switch Input or Output Leakage

V

C

1 kΩ

V

is

tr = tf = 20 ns

All unused terminals are connected to VSS.

V

DD

CD4066B

1 of 4

Switches

V

SS

V

os

10 kΩ

92CS-30924

Figure 12. Propagation Delay Time Signal Input

) to Signal Output (Vos)

(V

Figure 13. Crosstalk-Control Input

to Signal Output

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CMOS QUAD BILATERAL SWITCH

os

SS

SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003

TYPICAL CHARACTERISTICS

CD4066B

V

DD

tr = tf = 20 ns

NOTES: A. All unused terminals are connected to VSS.

B. Delay is measured at V

level of +10% from ground (turn-on) or on-state output level (turn-off).

Figure 14. Propagation Delay, t

t

r

V

C

tr = tf = 20 ns

V

os

10%

90%

50%

Repetition

Rate

VC = V

t

f

V

CD4066B

1 of 4

Switches

V

SS

, t

PHL

DD

V

os

50 pF

1 kΩ

Control-Signal Output

10 V

0 V

V

VOS+

OS

92CS-30925

at 1 kHz

2

DD

V

DD

PLH

All unused terminals are connected to V

Figure 15. Maximum Allowable Control-Input Repetition Rate

V

Vis = 10 V

.

C

VDD = 10 V

CD4066B

1 of 4

Switches

V

SS

V

50 pF

OS

V

at 1 kHz

OS

+

2

1 kΩ

92CS-30925

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9

CD4066B
CMOS QUAD BILATERAL SWITCH

SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003

TYPICAL CHARACTERISTICS

V

DD

I

V

SS

Inputs

V

DD

V

SS

92CS-27555

Measure inputs sequentially to both VDD and VSS. Connect all unused inputs to either VDD or VSS. Measure control inputs only.

Figure 16. Input Leakage-Current Test Circuit

10 2 3 7 9 12

14

PEJ1J2J3J4J

15

Q

1

54

7

1/3 CD4049B

9

5

1/4 CD4066B

V

DD

30% (VDD – VSS)
V

SS

CD4018B

2Q1

6

10

3

11

5

13 12 9 8 6 5 2 1

CD4001B

10 4

11

12 6 5 11

LPF

2

10 k

Ω

1

3

4

8

CD4066B

LPF

10 kΩ

9

LPF

10 kΩ

LPF

10

10 kΩ

Channel 1

Channel 2

Channel 3

Channel 4

Clock

Reset

3

1/3 CD4049B

5

Signal
Inputs

Package Count

2 - CD4001B
1 - CD4049B
3 - CD4066B
2 - CD4018B

10237912

14

PEJ1J2J3J4J

Q

2Q1

54

2

4

CD4018B

15

1

Channel 1
Channel 2
Channel 3
Channel 4

5

1
2

5
6

8

9

12
13

Maximum

Allowable

Signal Level

1

3

4

CD4001B

10

11
12

1
4
8

11

Clock

External

13

1/4 CD4066B

513

6

CD4066B

Chan 1 Chan 2 Chan 3 Chan 4

Reset

2

2
3
9

10

10 kΩ

Clock

11 12

1/6 CD4049B

4

3

Signal
Outputs

10

92CM-30928

Figure 17. Four-Channel PAM Multiplex System Diagram

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CMOS QUAD BILATERAL SWITCH

SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003

TYPICAL CHARACTERISTICS

CD4066B

5 V

0

IN

5 V

–5 V

VDD = 5 V

CD4054B

Digital
Control
Inputs

VSS = 0 V

VEE = –5 V

Analog Inputs (±5 V)

0

SW

A

Analog Outputs (±5 V)

CD4066B

SW

B

SW

VDD = 5 V

C

SW

D

VSS = –5 V

Figure 18. Bidirectional Signal Transmission Via Digital Control Logic

92CS-30927

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

11

CD4066B
CMOS QUAD BILATERAL SWITCH

SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003

APPLICATION INFORMATION

In applications that employ separate power sources to drive VDD and the signal inputs, the VDD current capability
should exceed V

DD/RL

any permanent current flow or clamp action on the V
In certain applications, the external load-resistor current can include both V

drawing V

current when switch current flows into terminals 1, 4, 8, or 1 1, the voltage drop across the bidirectional

DD

switch must not exceed 0.8 V (calculated from r
No V

current will flow through RL if the switch current flows into terminals 2, 3, 9, or 10.

DD

(R

= effective external load of the four CD4066B bilateral switches). This provision avoids

L

supply when power is applied or removed from the CD4066B.

DD

and signal-line components. T o avoid

DD

values shown).

on

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

28-Feb-2005

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

CD4066BE ACTIVE PDIP N 14 25 Pb-Free

CD4066BF ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC

CD4066BF3A ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC

CD4066BM ACTIVE SOIC D 14 50 Pb-Free

CD4066BM96 ACTIVE SOIC D 14 2500 Pb-Free

CD4066BMT ACTIVE SOIC D 14 250 Pb-Free

CD4066BNSR ACTIVE SO NS 14 2000 Pb-Free

CD4066BPW ACTIVE TSSOP PW 14 90 Pb-Free

CD4066BPWR ACTIVE TSSOP PW 14 2000 Pb-Free

JM38510/05852BCA ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-NC-NC-NC

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

CU NIPDAU Level-1-250C-UNLIM

CU NIPDAU Level-1-250C-UNLIM

(3)

(2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional

product content details.

None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65

1,20 MAX

14

0,30
0,19

8

4,50
4,30

PINS **

7

Seating Plane

0,15

0,05

8

1

A

DIM

6,60
6,20

14

0,10

M

0,10

0,15 NOM

2016

0°–8°

Gage Plane

24

0,25

0,75
0,50

28

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

4040064/F 01/97

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