Texas instruments CD4066B User Manual

E, F, M, NS, OR PW PACKAGE

D

15-V Digital or ±7.5-V Peak-to-Peak
Switching

D

125-Ω Typical On-State Resistance for 15-V
Operation

D

Switch On-State Resistance Matched to
Within 5 Ω Over 15-V Signal-Input Range

D

On-State Resistance Flat Over Full
Peak-to-Peak Signal Range

D

High On/Off Output-Voltage Ratio: 80 dB
Typical at f

D

High Degree of Linearity: <0.5% Distortion
Typical at f
V

– VSS ≥ 10 V, RL = 10 kΩ

DD

D

Extremely Low Off-State Switch Leakage,
Resulting in Very Low Offset Current and
High Effective Off-State Resistance: 10 pA
Typical at V

D

Extremely High Control Input Impedance
(Control Circuit Isolated From Signal
Circuit): 10

D

Low Crosstalk Between Switches: –50 dB
Typical at f

= 10 kHz, RL = 1 kΩ

is

= 1 kHz, Vis = 5 V p-p,

is

– VSS = 10 V, TA = 25°C

DD

12

Ω Typical

= 8 MHz, RL = 1 kΩ

is

CMOS QUAD BILATERAL SWITCH

SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003

D

Matched Control-Input to Signal-Output
Capacitance: Reduces Output Signal
Transients

D

Frequency Response, Switch On = 40 MHz
Typical

D

100% Tested for Quiescent Current at 20 V

D

5-V, 10-V, and 15-V Parametric Ratings

D

Meets All Requirements of JEDEC Tentative
Standard No. 13-B, Standard Specifications

for Description of “B” Series CMOS
Devices

D

Applications:
– Analog Signal Switching/Multiplexing:

Signal Gating, Modulator, Squelch
Control, Demodulator, Chopper,

Commutating Switch
– Digital Signal Switching/Multiplexing
– Transmission-Gate Logic Implementation
– Analog-to-Digital and Digital-to-Analog

Conversion
– Digital Control of Frequency, Impedance,

Phase, and Analog-Signal Gain

CD4066B

(TOP VIEW)

1

SIG A IN/OUT
SIG A OUT/IN
SIG B OUT/IN
SIG B IN/OUT

CONTROL B
CONTROL C

V

SS

14

V

2
3
4
5
6
7

DD

13

CONTROL A

12

CONTROL D

11

SIG D IN/OUT

10

SIG D OUT/IN
SIG C OUT/IN

9

SIG C IN/OUT

8

description/ordering information

The CD4066B is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals.
It is pin-for-pin compatible with the CD4016B, but exhibits a much lower on-state resistance. In addition, the
on-state resistance is relatively constant over the full signal-input range.

The CD4066B consists of four bilateral switches, each with independent controls. Both the p and the n devices
in a given switch are biased on or off simultaneously by the control signal. As shown in Figure 1, the well of the
n-channel device on each switch is tied to either the input (when the switch is on) or to V
is off). This configuration eliminates the variation of the switch-transistor threshold voltage with input signal and,
thus, keeps the on-state resistance low over the full operating-signal range.

The advantages over single-channel switches include peak input-signal voltage swings equal to the full supply
voltage and more constant on-state impedance over the input-signal range. However, for sample-and-hold
applications, the CD4016B is recommended.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

(when the switch

SS

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2003, Texas Instruments Incorporated

1

CD4066B

SOIC – M

CD4066BM

–55°C to 125°C

TSSOP – PW

CM066B

SS

DD

Switch

CMOS QUAD BILATERAL SWITCH

SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003

description/ordering information (continued)

ORDERING INFORMATION

T

A

CDIP – F Tube of 25 CD4066BF3A CD4066BF3A
PDIP – E Tube of 25 CD4066BE CD4066BE

SOP – NS Reel of 2000 CD4066BNSR CD4066B

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.

PACKAGE

Tube of 50 CD4066BM
Reel of 2500 CD4066BM96
Reel of 250 CD4066BMT

Tube of 90 CD4066BPW
Reel of 2000 CD4066BPWR

†

ORDERABLE

PART NUMBER

TOP-SIDE
MARKING

Control

Control

†

V

C

†

All control inputs are protected by the CMOS protection network.

NOTES: A. All p substrates are connected to VDD.

B. Normal operation control-line biasing: switch on (logic 1), VC = VDD; switch off (logic 0), VC = V
C. Signal-level range: V

≤ Vis ≤ V

In
V

is

p

n

p

Out
V

n

n

V

SS

os

V

DD

V

SS

SS

92CS-29113

2

Figure 1. Schematic Diagram of One-of-Four Identical Switches and Associated Control Circuitry

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CD4066B

CMOS QUAD BILATERAL SWITCH

SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

DC supply-voltage range, V
Input voltage range, V
DC input current, I

(all inputs) –0.5 V to VDD + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

is

(any one input) ±10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IN

Package thermal impedance, θ

(voltages referenced to VSS terminal) –0.5 V to 20 V. . . . . . . . . . . . . . . . . . . .

DD

(see Note 1): E package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

†

M package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature (during soldering):

At distance 1/16 ± 1/32 inch (1,59 ± 0,79 mm) from case for 10 s max 265°C. . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions

MIN MAX UNIT

V
T

Supply voltage 3 18 V

DD

Operating free-air temperature

A

–55

125 °C

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

CD4066B

PARAMETER

TEST CONDITIONS

V

V

UNIT

V

IN

V

DD

–55°C

–40°C

85°C

125°C

Quiescent device

I

DD

Quiescent device

A

VC = VDD,
R

= 10 kΩ returned

r

On-state resistance

RL = 10 k returned

to ,

2

r

on

On-state resistance
RL = 10 kΩ, VC = V

DD

on

L CDD

RL = 200 k

VC = VDD,

t

Propagation delay

VSS = GND, CL = 50 pF,

ns

signal output)

(square wave centered on 5 V),

CMOS QUAD BILATERAL SWITCH

SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003

electrical characteristics

current

Signal Inputs (Vis) and Outputs (Vos)

on

(max)

∆

difference between
any two switches

Total harmonic

THD

distortion
–3-dB cutoff

frequency
(switch on)

–50-dB feedthrough
frequency (switch off)

Input/output leakage
current (switch off)

I

is

(max)

–50-dB crosstalk
frequency

ǒ

VDD*

to ,
Vis = VSS to V

VC = VDD = 5 V, VSS = –5 V,
V

is(p-p)

RL = 10 kΩ, fis = 1-kHz sine wave
VC = VDD = 5 V , VSS = –5 V , V

(sine wave centered on 0 V), RL = 1 kΩ
VC = VSS = –5 V, V

(sine wave centered on 0 V), RL = 1 kΩ
VC = 0 V, Vis = 18 V, Vos = 0 V;

and
VC = 0 V, Vis = 0 V, Vos = 18 V

VC(A) = VDD = 5 V,
VC(B) = VSS = –5 V,
Vis(A) = 5 V
RL = 1 kΩ

Ǔ

V

SS

DD

= 5 V (sine wave centered on 0 V),

is(p-p)

, 50-Ω source,

p-p

Ω,

LIMITS AT INDICATED TEMPERATURES

(V)

(V)

0, 5 5 0.25 0.25 7.5 7.5 0.01 0.25
0, 10 10 0.5 0.5 15 15 0.01 0.5
0, 15 15 1 1 30 30 0.01 1
0, 20 20 5 5 150 150 0.02 5

5 800 850 1200 1300 470 1050

10 310 330 500 550 180 400

15 200 210 300 320 125 240

5 15
10 10
15 5

= 5 V

is(p-p)

= 5 V

18 ±0.1 ±0.1 ±1 ±1 ±10

5 20 40

°

25°C

TYP MAX

0.4 %

40 MHz

1 MHz

–5

8 MHz

µ

Ω

Ω

±0.1 µA

(signal input to

pd

C

Input capacitance VDD = 5 V, VC = VSS = –5 V 8 pF

is

C

Output capacitance VDD = 5 V, VC = VSS = –5 V 8 pF

os

C

Feedthrough VDD = 5 V, VC = VSS = –5 V 0.5 pF

ios

4

Vis = 10 V

tr, tf = 20 ns

10 10 20
15 7 15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics (continued)

CHARACTERISTIC

TEST CONDITIONS

V

UNIT

V

DD

–55°C

–40°C

85°C

125°C

V

ILC

Control input,

|Iis| < 10 µA,

V

ILC

low voltage (max)

is SS OS DD

V

IHC

Control input,
See Figure 6

V

IHC

high voltage

Turn-on and turn-off

VIN = VDD, tr, tf = 20 ns,

ns

propagation delay

CL = 50 pF, RL = 1 kΩ

Vis = VDD, VSS = GND,

Maximum control input
repetition rate

RL = 1 kΩ to GND, CL = 50 pF,

MHz

repetition rate
centered on 5 V), tr, tf = 20 ns,

SWITCH

V

V

is

OUTPUT, V

os

(V)

is

(V)

Control (VC)

Vis = VSS, VOS = VDD, and
Vis = VDD, VOS = V

I

Input current (max)

IN

Crosstalk (control input
to signal output)

Vis ≤ VDD, VDD – VSS = 18 V,
VCC ≤ VDD – V

VC = 10 V (square wave),
tr, tf = 20 ns, RL = 10 kΩ

SS

SS

CD4066B

CMOS QUAD BILATERAL SWITCH

SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003

LIMITS AT INDICATED TEMPERATURES

(V)

5 1 1 1 1 1
10 2 2 2 2 2
15 2 2 2 2 2

5 3.5 (MIN)
10 7 (MIN)
15 11 (MIN)

18 ±0.1 ±0.1 ±1 ±1 ±10

10 50 mV

5 35 70
10 20 40
15 15 30

5 6

°

25°C

TYP MAX

–5

±0.1 µA

VC = 10 V (square wave

Vos = 1/2 Vos at 1 kHz

CIInput capacitance 5 7.5 pF

10 9
15 9.5

switching characteristics

SWITCH INPUT

DD

(V)

–55°C –40°C 25°C 85°C 125°C MIN MAX

5 0 0.64 0.61 0.51 0.42 0.36

5 5 –0.64 –0.61 –0.51 –0.42 –0.36 4.6
10 0 1.6 1.5 1.3 1.1 0.9
10 10 –1.6 –1.5 –1.3 –1.1 –0.9 9.5
15 0 4.2 4 3.4 2.8 2.4
15 15 –4.2 –4 –3.4 –2.8 –2.4 13.5

Iis (mA)

(V)

0.4

0.5

1.5

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5

CD4066B
CMOS QUAD BILATERAL SWITCH

SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003

TYPICAL CHARACTERISTICS

TYPICAL ON-STATE RESISTANCE

vs

INPUT SIGNAL VOLTAGE (ALL TYPES)

Supply Voltage (VDD – VSS) = 5 V

600

Ω

500

400

300

200

100

– Channel On-State Resistance –

0

on

r

–4 –3 –2 –1 0 1 2 3 4

Vis – Input Signal Voltage – V

TA = 125°C

Figure 2

TYPICAL ON-STATE RESISTANCE

vs

INPUT SIGNAL VOLTAGE (ALL TYPES)

Ω

Supply Voltage (VDD – VSS) = 15 V

300

+25°C

–55°C

92CS-27326RI

TYPICAL ON-STATE RESISTANCE

vs

INPUT SIGNAL VOLTAGE (ALL TYPES)

300

Supply Voltage (VDD – VSS) = 10 V

Ω

250

200

150

100

50

– Channel On-State Resistance –

0

on

r

–10 –7.5 –5 –2.5 0 2.5 5 7.5 10

Vis – Input Signal Voltage – V

TA = 125°C

+25°C

–55°C

Figure 3

TYPICAL ON-STATE RESISTANCE

vs

INPUT SIGNAL VOLTAGE (ALL TYPES)

Ω

TA = 125°C

600

92CS-27327RI

250

200

TA = 125°C

150

100

50

– Channel On-State Resistance –

0

on

–10 –7.5 –5 –2.5 0 2.5 5 7.5 10

r

Vis – Input Signal Voltage – V

Figure 4

+25°C
–55°C

92CS-27329RI

500

400

300

200

100

– Channel On-State Resistance –

0

on

r

–10 –7.5 –5 –2.5 0 2.5 5 7.5 10

Supply Voltage (VDD – VSS) = 5 V

Vis – Input Signal Voltage – V

Figure 5

10 V

–15 V

92CS-27330RI

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265