Texas Instruments CD4049UB, CD4050B Specifications

CD4049UB, CD4050B

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CD40

9UB,

D405

B)
Sub­ect
CMO

Hex

uffer/
on-

erters)
Autho
()
Key-

ords

Harris

emi-

on-

uctor,

D400

,

etal

ate,

MOS

Data sheet acquired from Harris Semiconductor
SCHS046I

CMOS Hex Buffer/Converters

The CD4049UB and CD4050B devices are inverting and
non-inverting hex buffers, respectively, and feature logic­level conversion using only one supply voltage (V
input-signal high level (V

) can exceed the VCC supply

IH

CC

). The

voltage when these devices are used for logic-level
conversions.These devices are intended for use as CMOS
to DTL/TTL converters and can drive directly two DTL/TTL
loads. (V

= 5V, VOL≤ 0.4V, and IOL≥ 3.3mA.)

CC

The CD4049UB and CD4050B are designated as
replacements for CD4009UB and CD4010B, respectively.
Because the CD4049UB and CD4050B require only one
power supply, they are preferred over the CD4009UB and
CD4010B and should be used in place of the CD4009UB
and CD4010B in all inverter, current driver, or logic-level
conversion applications. In these applications the
CD4049UB and CD4050B are pin compatible with the
CD4009UB and CD4010B respectively, and can be
substituted for these devices in existing as well as in new
designs. Terminal No. 16 is not connected internally on the
CD4049UB or CD4050B, therefore, connection to this
terminal is of no consequence to circuit operation. For
applications not requiring high sink-current or voltage
conversion, the CD4069UB Hex Inverter is recommended.

Features

• CD4049UB Inverting

• CD4050B Non-Inverting

• High Sink Current for Driving 2 TTL Loads

• High-To-Low Level Logic Conversion

• 100% Tested for Quiescent Current at 20V

• Maximum Input Current of 1µA at 18V Over Full P ac kage
Temperature Range; 100nA at 18V and 25

• 5V, 10V and 15V Parametric Ratings

o

C

August 1998 - Revised May 2004

Applications

• CMOS to DTL/TTL Hex Converter

• CMOS Current “Sink” or “Source” Driver

• CMOS High-To-Low Logic Level Converter

Ordering Information

TEMP.

PART NUMBER

CD4049UBF3A -55 to 125 16 Ld CERDIP
CD4050BF3A -55 to 125 16 Ld CERDIP
CD4049UBD -55 to 125 16 Ld SOIC
CD4049UBDR -55 to 125 16 Ld SOIC
CD4049UBDT -55 to 125 16 Ld SOIC
CD4049UBDW -55 to 125 16 Ld SOIC
CD4049UBDWR -55 to 125 16 Ld SOIC
CD4049UBE -55 to 125 16 Ld PDIP
CD4049UBNSR -55 to 125 16 Ld SOP
CD4049UBPW -55 to 125 16 Ld TSSOP
CD4049UBPWR -55 to 125 16 Ld TSSOP
CD4050BD -55 to 125 16 Ld SOIC
CD4050BDR -55 to 125 16 Ld SOIC
CD4050UBDT -55 to 125 16 Ld SOIC
CD4050BDW -55 to 125 16 Ld SOIC
CD4050BDWR -55 to 125 16 Ld SOIC
CD4050BE -55 to 125 16 Ld PDIP
CD4050NSR -55 to 125 16 Ld SOP
CD4050BPW -55 to 125 16 Ld TSSOP
CD4050BPWR -55 to 125 16 Ld TSSOP

NOTE: When ordering, use the entire part number. The suffixRdenotestape
and reel. The suffix T denotes a small-quantity reel of 250.

RANGE (oC) PACKAGE

Pinouts

CD4049UB (PDIP, CERDIP, SOIC, SOP, TSSOP)

V

CC

G = A

H =

I =

V

SS

A
B
B
C
C

1
2
3
4
5
6
7
8

TOP VIEW

1

CD4050B (PDIP, CERDIP, SOIC, SOP)

TOP VIEW

16

NC

15

F

L =

14

F

13

NC

12

E

K =
E

11

J =

10

D

9

D

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

V

CC

G = A

H = B

I = C

V

SS

1
2
3

A

4
5

B

6
7

C

8

Copyright

© 2004, Texas Instruments Incorporated

NC

16
15

L = F
F

14

NC

13

K = E

12

E

11

J = D

10

D

9

Functional Block Diagrams

CD4049UB CD4050B

CD4049UB, CD4050B

32

AG =

54

BH =

76

CI =

910

DJ =

11 12

EK =

14 15

FL =

1

V

CC

8

V

SS

NC = 13
NC = 16

Schematic Diagrams

A

B

C

D

E

F

32

A G = A

54

B H = B

76

C I = C

910

D J = D

11 12

E K = E

14 15

F L = F

1

V

CC

8

V

SS

NC = 13
NC = 16

V

CC

P

R

IN

OUT

N

V

SS

FIGURE 1A. SCHEMATIC DIAGRAM OF CD4049UB, 1 OF 6

IDENTICAL UNITS

V

CC

P

R

IN

N

P

OUT

N

V

SS

FIGURE 1B. SCHEMATIC DIAGRAM OF CD4050B, 1 OF 6

IDENTICAL UNITS

2

CD4049UB, CD4050B

Absolute Maximum Ratings Thermal Information

Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . -0.5V to 20V

DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . ±10mA

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Specifications

TEST CONDITIONS

PARAMETER

Quiescent Device Current
IDD (Max)

Output Low (Sink) Current
IOL (Min)

Output High (Source) Current
IOH (Min)

Out Voltage Low Level
VOL (Max)

Output Voltage High Level
VOH (Min)

Input Low Voltage, VIL (Max)
CD4049UB

Input Low Voltage, VIL (Max)
CD4050B

V

O

(V)

- 0,5 5 1 1 30 30 - 0.02 1 µA

- 0,10 10 2 2 60 60 - 0.02 2 µA

- 0,15 15 4 4 120 120 - 0.02 4 µA

- 0,20 20 20 20 600 600 - 0.04 20 µA

0.4 0,5 4.5 3.3 3.1 2.1 1.8 2.6 5.2 - mA

0.4 0,5 5 4 3.8 2.9 2.4 3.2 6.4 - mA

0.5 0,10 10 10 9.6 6.6 5.6 8 16 - mA

1.5 0,15 15 26 25 20 18 24 48 - mA

4.6 0,5 5 -0.81 -0.73 -0.58 -0.48 -0.65 -1.2 - mA

2.5 0,5 5 -2.6 -2.4 -1.9 -1.55 -2.1 -3.9 - mA

9.5 0,10 10 -2.0 -1.8 -1.35 -1.18 -1.65 -3.0 - mA

13.5 0,15 15 -5.2 -4.8 -3.5 -3.1 -4.3 -8.0 - mA

- 0,5 5 0.05 0.05 0.05 0.05 - 0 0.05 V

- 0,10 10 0.05 0.05 0.05 0.05 - 0 0.05 V

- 0,15 15 0.05 0.05 0.05 0.05 - 0 0.05 V

- 0,5 5 4.95 4.95 4.95 4.95 4.95 5 - V

- 0,10 10 9.95 9.95 9.95 9.95 9.95 10 - V

- 0,15 15 14.95 14.95 14.95 14.95 14.95 15 - V

4.5 - 5 1 1 1 1 - - 1 V
9 - 102222- -2 V

13.5 - 15 2.5 2.5 2.5 2.5 - - 2.5 V

0.5 - 5 1.5 1.5 1.5 1.5 - - 1.5 V
1 - 103333- -3 V

1.5 - 15 4 4 4 4 - - 4 V

V

IN

(V) VCC (V) MIN TYP MAX

Package Thermal Impedance, θJA (see Note1):

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W

D (SOIC) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W

DW (SOIC) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57oC/W

NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W

PW (TSSOP) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W

Maximum Junction Temperature (Plastic Package). . . . . . . . .150oC

Maximum Storage Temperature Range. . . . . . . . . . . 65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .265oC

SOIC - Lead Tips Only

LIMITS AT INDICATED TEMPERATURE (oC)

25

UNITS-55 -40 85 125

3

CD4049UB, CD4050B

DC Electrical Specifications (Continued)

LIMITS AT INDICATED TEMPERATURE (oC)

TEST CONDITIONS

V

PARAMETER

Input High Voltage, VIH Min
CD4049UB

O

(V)

0.5 - 5 44444- - V
1 - 1088888- - V

1.5 - 15 12.5 12.5 12.5 12.5 12.5 - - V

Input High Voltage, VIH Min
CD4050B

4.5 - 5 3.5 3.5 3.5 3.5 3.5 - - V
9 - 1077777- - V

13.5 - 15 11 11 11 11 11 - - V

Input Current, IIN Max - 0,18 18 ±0.1 ±0.1 ±1 ±1-±10

V

IN

(V) VCC (V) MIN TYP MAX

25

-5

UNITS-55 -40 85 125

±0.1 µA

AC Electrical Specifications T

PARAMETER

Propagation Delay Time
Low to High, t
CD4049UB

Propagation Delay Time
Low to High, t
CD4050B

Propagation Delay Time
High to Low, t
CD4049UB

Propagation Delay Time
High to Low, t
CD4050B

Transition Time, Low to High, t

Transition Time, High to Low, t

PLH

PLH

PHL

PHL

TLH

THL

= 25oC, Input tr, tf = 20ns, CL = 50pF, RL = 200kΩ

A

TEST CONDITIONS LIMITS (ALL PACKAGES)

IN

V

CC

5 5 60 120 ns
10 10 32 65 ns
10 5 45 90 ns
15 15 25 50 ns
15 5 45 90 ns

5 5 70 140 ns
10 10 40 80 ns
10 5 45 90 ns
15 15 30 60 ns
15 5 40 80 ns

5 5 32 65 ns
10 10 20 40 ns
10 5 15 30 ns
15 15 15 30 ns
15 5 10 20 ns

5 5 55 110 ns
10 10 22 55 ns
10 5 50 100 ns
15 15 15 30 ns
15 5 50 100 ns

5 5 80 160 ns
10 10 40 80 ns
15 15 30 60 ns

5 5 30 60 ns
10 10 20 40 ns
15 15 15 30 ns

TYP MAX

UNITSV

4

CD4049UB, CD4050B

AC Electrical Specifications T

A

PARAMETER

Input Capacitance, C

IN

CD4049UB
Input Capacitance, C

IN

CD4050B

Typical Performance Curves

TA = 25oC
SUPPLY VOLTAGE (VCC) = 5V

5

4

3

2

, OUTPUT VOLTAGE (V)

O

V

1

01234

VI, INPUT VOLTAGE (V)

= 25oC, Input tr, tf = 20ns, CL = 50pF, RL = 200kΩ (Continued)

TEST CONDITIONS LIMITS (ALL PACKAGES)

IN

V

CC

TYP MAX

- - 15 22.5 pF

- - 5 7.5 pF

TA = 25oC
SUPPLY VOLTAGE (VCC) = 5V

5

MAXIMUMMINIMUM

4

3

2

, OUTPUT VOLTAGE (V)

O

V

1

01234

VI, INPUT VOLTAGE (V)

UNITSV

MAXIMUMMINIMUM

FIGURE 2. MINIMUM AND MAXIMUM VOLTAGE TRANSFER

CHARACTERISTICS FOR CD4049UB

TA = 25oC

70

15V

60

50

40

30

20

10

, OUTPUT LOW (SINK) CURRENT (mA)

OL

I

01234

10V

GATE TO SOURCE VOLTAGE (VGS) = 5V

5678

, DRAIN TO SOURCE VOLTAGE (V)

V

DS

FIGURE 4. TYPICAL OUTPUT LOW(SINK)CURRENT

CHARACTERISTICS

FIGURE 3. MINIMUM AND MAXIMUM VOLTAGE TRANSFER

CHARACTERISTICS FOR CD4050B

TA = 25oC

70

60

50

40

30

20

10

, OUTPUT LOW (SINK) CURRENT (mA)

OL

I

01234

GATE TO SOURCE VOLTAGE (VGS) = 5V

VDS, DRAIN TO SOURCE VOLTAGE (V)

10V15V

5678

FIGURE 5. MINIMUM OUTPUT LOW (SINK) CURRENT DRAIN

CHARACTERISTICS

5

CD4049UB, CD4050B

Typical Performance Curves (Continued)

VDS, DRAIN TO SOURCE VOLTAGE (V)

-8 -7 -6 -5 -4 -3 -2 -1 0

TA = 25oC

-5

GATE TO SOURCE VOLTAGE
V

= -5V

GS

-10V

-15V

-10

-15

-20

-25

-30

-35

FIGURE 6. TYPICAL OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

10

9
8
7
6
5
4

, OUTPUT VOLTAGE (V)

3

O

V

2
1
0

125oC

VCC = 5V

125oC

SUPPLY VOLTAGE

= 10V

V

CC

TA = -55oC

-55oC

876543210

VI, INPUT VOLTAGE (V)

910

TA = 25oC

GATE TO SOURCE VOLTAGE
VGS = -5V

OUTPUT HIGH (SOURCE)

CURRENT CHARACTERISTICS

FIGURE 7. MINIMUM OUTPUT HIGH (SOURCE) CURRENT

10

9
8
7
6
5
4

, OUTPUT VOLTAGE (V)

3

O

V

2
1
0

, DRAIN TO SOURCE VOLTAGE (V)

V

DS

-8 -7 -6 -5 -4 -3 -2 -1 0

-10V

-15V

CHARACTERISTICS

SUPPLY VOLTAGE
V

= 10V

CC

TA = -55oC

876543210

910

125oC

125oC

VCC = 5V

-55oC

V

, INPUT VOLTAGE (V)

I

-5

-10

-15

-20

-25

-30

OUTPUT HIGH (SOURCE)

-35

CURRENT CHARACTERISTICS

FIGURE 8. TYPICALVOL TAGETRANSFERCHARACTERISTICS

AS A FUNCTION OF TEMPERA TURE FOR CD4049UB

5

10

TA = 25oC

= 15V

10V

POWER DISSIPATION PER INVERTER (µW)

4

10

Y V

SUPPL

3

10

2

10

10

10

10

CC

GE V

A

T

OL

LOAD CAPACITANCE
C

(11pF FIXTURE + 39pF EXT)
C

(11pF FIXTURE + 4pF EXT)

2

f, INPUT FREQUENCY (kHz)

= 50pF

L

= 15pF

L

10

10V

5V

3

4

10

10

FIGURE 10. TYPICAL POWER DISSIPATION vs FREQUENCY

CHARACTERISTICS

6

FIGURE 9. TYPICALVOLTAGETRANSFERCHARACTERISTICS

AS A FUNCTION OF TEMPERA TURE FOR CD4050B

TA = 25oC

5

10

4

10

3

10

2

10

10

POWER DISSIPATION PER INVERTER (µW)

5

SUPPLY VOLTAGE VCC = 5V FREQUENCY (f) = 10kHz

2

3

4

10

10

10

tr, tf, INPUT RISE AND FALL TIME (ns)

10

5

10

15V; 1MHz
15V; 100kHz
10V; 100kHz
15V; 10kHz
10V; 10kHz
15V; 1kHz

6

10

7

10

8

10

FIGURE 11. TYPICAL POWER DISSIPATION vs INPUT RISE

AND FALL TIMES PER INVERTER FOR CD4049UB

CD4049UB, CD4050B

Typical Performance Curves (Continued)

6

10

TA = 25oC

5

10

4

10

3

10

2

10

10

SUPPLY VOLTAGE VCC = 5V FREQUENCY (f) = 10kHz

POWER DISSIPATION PER INVERTER (µW)

1

10 10

2

tr, tf, INPUT RISE AND FALL TIME (ns)

FIGURE 12. TYPICAL POWER DISSIPATION vs INPUT RISE

AND FALL TIMES PER INVERTER FOR CD4050B

Test Circuits

V

V

CC

INPUTS

V

SS

FIGURE 13. QUIESCENT DEVICE CURRENT TEST CIRCUIT

CC

I

DD

V

SS

10310

15V; 1MHz
15V; 100kHz
10V; 100kHz
15V; 10kHz
10V; 10kHz
15V; 1kHz

4

5

10

10610

7

8

10

V

CC

V

IH

OUTPUTSINPUTS

+

V

IL

V

SS

NOTE: Test any one input with other inputs at VCC or VSS.

FIGURE 14. INPUT VOLTAGE TEST CIRCUIT

DVM

-

V

CC

V

CC

I

V

SS

OUTPUTSINPUTS

V

SS

NOTE: Measure inputs sequentially, to both VCC and VSS connect
all unused inputs to either VCC or VSS.

FIGURE 15. INPUT CURRENT TEST CIRCUIT

7

10V = V

CMOS 10V LEVEL TO DTL/TTL 5V LEVEL

COS/MOS
IN

IH

0 = V

IL

VCC = 5V

CD4049

OUTPUT
TO DTL/TTL

INPUTS

V

SS

In Terminal - 3, 5, 7, 9, 11, or 14
Out Terminal - 2, 4, 6, 10, 12 or 15
VCC Terminal - 1
VSS Terminal - 8

FIGURE 16. LOGIC LEVEL CONVERSION APPLICATION

5V = V

0 = V

OH

OL

Test Circuits (Continued)

CD4049UB, CD4050B

V

DD

0.1µF

500µF

I

C

L

10kHz,

100kHz, 1MHz

INCLUDES FIXTURE CAPACITANCE

C

L

1
2
3
4
5
6
7
8

16
15
14
13
12
11

CD4049UB

10

9

FIGURE 17. DYNAMIC POWER DISSIPATION TEST CIRCUITS

8

CD4049UB, CD4050B

9

PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device Status

CD4049UBD ACTIVE SOIC D 16 40 Pb-Free

CD4049UBDR ACTIVE SOIC D 16 2500 Pb-Free

CD4049UBDT ACTIVE SOIC D 16 250 Pb-Free

CD4049UBDW ACTIVE SOIC DW 16 40 Pb-Free

CD4049UBDWR ACTIVE SOIC DW 16 2000 Pb-Free

CD4049UBE ACTIVE PDIP N 16 25 Pb-Free

CD4049UBF ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC

CD4049UBF3A ACTIVE CDIP J 16 1 None CallTI Level-NC-NC-NC

CD4049UBM OBSOLETE SOIC D 16 None Call TI Call TI

CD4049UBM96 OBSOLETE SOIC D 16 None Call TI Call TI

CD4049UBNSR ACTIVE SO NS 16 2000 Pb-Free

CD4049UBPW ACTIVE TSSOP PW 16 90 Pb-Free

CD4049UBPWR ACTIVE TSSOP PW 16 2000 Pb-Free

CD4050BD ACTIVE SOIC D 16 40 Pb-Free

CD4050BDR ACTIVE SOIC D 16 2500 Pb-Free

CD4050BDT ACTIVE SOIC D 16 250 Pb-Free

CD4050BDW ACTIVE SOIC DW 16 40 Pb-Free

CD4050BDWR ACTIVE SOIC DW 16 2000 Pb-Free

CD4050BE ACTIVE PDIP N 16 25 Pb-Free

CD4050BF ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC

CD4050BF3A ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC

CD4050BM OBSOLETE SOIC D 16 None Call TI Call TI

CD4050BNSR ACTIVE SO NS 16 2000 Pb-Free

CD4050BPW ACTIVE TSSOP PW 16 90 Pb-Free

CD4050BPWR ACTIVE TSSOP PW 16 2000 Pb-Free

JM38510/05553BEA ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC
JM38510/05554BEA ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-2-260C-1 YEAR/

CU NIPDAU Level-2-260C-1 YEAR/

CU NIPDAU Level-2-260C-1 YEAR/

CU NIPDAU Level-2-250C-1 YEAR/

CU NIPDAU Level-2-250C-1 YEAR/

CU NIPDAU Level-NC-NC-NC

CU NIPDAU Level-2-260C-1 YEAR/

CU NIPDAU Level-1-250C-UNLIM

CU NIPDAU Level-1-250C-UNLIM

CU NIPDAU Level-2-260C-1 YEAR/

CU NIPDAU Level-2-260C-1 YEAR/

CU NIPDAU Level-2-260C-1 YEAR/

CU NIPDAU Level-2-250C-1 YEAR/

CU NIPDAU Level-2-250C-1 YEAR/

CU NIPDAU Level-NC-NC-NC

CU NIPDAU Level-2-260C-1 YEAR/

CU NIPDAU Level-1-250C-UNLIM

CU NIPDAU Level-1-250C-UNLIM

Level-1-235C-UNLIM

Level-1-235C-UNLIM

Level-1-235C-UNLIM

Level-1-235C-UNLIM

Level-1-235C-UNLIM

Level-1-235C-UNLIM

Level-1-235C-UNLIM

Level-1-235C-UNLIM

Level-1-235C-UNLIM

Level-1-235C-UNLIM

Level-1-235C-UNLIM

Level-1-235C-UNLIM

28-Feb-2005

(3)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional

product content details.

None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

28-Feb-2005

Addendum-Page 2

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65

1,20 MAX

14

0,30
0,19

8

4,50
4,30

PINS **

7

Seating Plane

0,15
0,05

8

1

A

DIM

6,60
6,20

14

0,10

M

0,10

0,15 NOM

0°–8°

2016

Gage Plane

24

0,25

0,75
0,50

28

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

4040064/F 01/97

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