Texas Instruments CD4049UB, CD4050B Service Manual

CD4049UB, CD4050B

[ /Title
(CD40
49UB,
CD405
0B)
/Sub­ject
(CMO
S Hex
Buffer/
Con­verters)
/Autho
r ()
/Key­words
(Harris
Semi­con­ductor,
CD400
0,
metal
gate,
CMOS

Data sheet acquired from Harris Semiconductor
SCHS046A

CMOS Hex Buffer/Converters

The CD4049UB and CD4050B devices are inverting and
non-inverting hex buffers, respectively, and feature logic­level conversion using only one supply voltage (V
input-signal high level (V

) can exceed the VCC supply

IH

CC

). The

voltage when these devices are used for logic-level
conversions.These devices are intended for use as CMOS
to DTL/TTL converters and can drive directly two DTL/TTL
loads. (V

= 5V, VOL≤ 0.4V, and IOL≥ 3.3mA.)

CC

The CD4049UB and CD4050B are designated as
replacements for CD4009UB and CD4010B, respectively.
Because the CD4049UB and CD4050B require only one
power supply, they are preferred over the CD4009UB and
CD4010B and should be used in place of the CD4009UB
and CD4010B in all inverter, current driver, or logic-level
conversion applications. In these applications the
CD4049UB and CD4050B are pin compatible with the
CD4009UB and CD4010B respectively, and can be
substituted for these devices in existing as well as in new
designs. Terminal No. 16 is not connected internally on the
CD4049UB or CD4050B, therefore, connection to this
terminal is of no consequence to circuit operation. For
applications not requiring high sink-current or voltage
conversion, the CD4069UB Hex Inverter is recommended.

Pinouts

CD4049UB (PDIP, CERDIP)

TOP VIEW

August 1998 - Revised May 1999

Features

• CD4049UB Inverting

• CD4050B Non-Inverting

• High Sink Current for Driving 2 TTL Loads

• High-To-Low Level Logic Conversion

• 100% Tested for Quiescent Current at 20V

• Maximum Input Current of 1µA at 18V Over Full Package
Temperature Range; 100nA at 18V and 25

o

C

• 5V, 10V and 15V Parametric Ratings

Applications

• CMOS to DTL/TTL Hex Converter

• CMOS Current “Sink” or “Source” Driver

• CMOS High-To-Low Logic Level Converter

Ordering Information

TEMP.

PART NUMBER

CD4049UBE -55 to 125 16 Ld PDIP E16.3
CD4050BE -55 to 125 16 Ld PDIP E16.3
CD4049UBF -55 to 125 16 Ld CERDIP F16.3
CD4050BF -55 to 125 16 Ld CERDIP F16.3
CD4050BM -55 to 125 16 Ld SOIC M16.3

NOTE: Wafer and die for this part number is available which meets
all electrical specifications. Please contact your local sales office or
customer service for ordering information.

RANGE (oC) PACKAGE

CD4050B (PDIP, CERDIP, SOIC)

TOP VIEW

PKG.

NO.

V

CC

G = A

H =

I =

V

SS

NC

1
2

A

3
4

B
B

5
6

C

7

C

8

16
15

F

L =
F

14

NC

13

K =

12

E

11

E

10

J = D

9

D

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

V

CC

G = A

H = B

I = C

V

SS

1
2

A

3
4

B

5
6
7

C

8

Copyright

© 1999, Texas Instruments Incorporated

NC

16

L = F

15

F

14

NC

13

K = E

12

E

11

J = D

10

D

9

Functional Block Diagrams

CD4049UB CD4050B

CD4049UB, CD4050B

32

AG =

54

BH =

76

CI =

910

DJ =

11 12

EK =

14 15

FL =

1

V

CC

8

V

SS

NC = 13
NC = 16

Schematic Diagrams

A

B

C

D

E

F

32

A G = A

54

B H = B

76

C I = C

910

D J = D

11 12

E K = E

14 15

F L = F

1

V

CC

8

V

SS

NC = 13
NC = 16

V

CC

P

R

IN

OUT

N

V

SS

FIGURE 1A. SCHEMATIC DIAGRAM OF CD4049UB, 1 OF 6

IDENTICAL UNITS

V

CC

P

R

IN

N

P

OUT

N

V

SS

FIGURE 1B. SCHEMATIC DIAGRAM OF CD4050B, 1 OF 6

IDENTICAL UNITS

2

CD4049UB, CD4050B

Absolute Maximum Ratings Thermal Information

Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . -0.5V to 20V

DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . ±10mA

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications

TEST CONDITIONS

PARAMETER

Quiescent Device Current
IDD (Max)

Output Low (Sink) Current
IOL (Min)

Output High (Source) Current
IOH (Min)

Out Voltage Low Level
VOL (Max)

Output Voltage High Level
VOH (Min)

Input Low Voltage, VIL (Max)
CD4049UB

Input Low Voltage, VIL (Max)
CD4050B

Input High Voltage, VIH Min
CD4049UB

V

O

(V)

- 0,5 5 1 1 30 30 - 0.02 1 µA

- 0,10 10 2 2 60 60 - 0.02 2 µA

- 0,15 15 4 4 120 120 - 0.02 4 µA

- 0,20 20 20 20 600 600 - 0.04 20 µA

0.4 0,5 4.5 3.3 3.1 2.1 1.8 2.6 5.2 - mA

0.4 0,5 5 4 3.8 2.9 2.4 3.2 6.4 - mA

0.5 0,10 10 10 9.6 6.6 5.6 8 16 - mA

1.5 0,15 15 26 25 20 18 24 48 - mA

4.6 0,5 5 -0.81 -0.73 -0.58 -0.48 -0.65 -1.2 - mA

2.5 0,5 5 -2.6 -2.4 -1.9 -1.55 -2.1 -3.9 - mA

9.5 0,10 10 -2.0 -1.8 -1.35 -1.18 -1.65 -3.0 - mA

13.5 0,15 15 -5.2 -4.8 -3.5 -3.1 -4.3 -8.0 - mA

- 0,5 5 0.05 0.05 0.05 0.05 - 0 0.05 V

- 0,10 10 0.05 0.05 0.05 0.05 - 0 0.05 V

- 0,15 5 0.05 0.05 0.05 0.05 - 0 0.05 V

- 0,5 5 4.95 4.95 4.95 4.95 4.95 5 - V

- 0,10 10 9.95 9.95 9.95 9.95 9.95 10 - V

- 0,15 15 14.95 14.95 14.95 14.95 14.95 15 - V

4.5 - 5 1 1 1 1 - - 1 V
9-102222--2V

13.5 - 15 2.5 2.5 2.5 2.5 - - 2.5 V

0.5 - 5 1.5 1.5 1.5 1.5 - - 1.5 V
1-103333--3V

1.5 - 154444--4 V

0.5 - 5 4 4 4 4 4 - - V
1-1088888--V

1.5 - 15 12.5 12.5 12.5 12.5 12.5 - - V

V

IN

(V) VCC (V) MIN TYP MAX

Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)

PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A

CERDIP Package. . . . . . . . . . . . . . . . . 130 55

SOIC Package . . . . . . . . . . . . . . . . . . . 100 N/A

Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .265oC

(SOIC - Lead Tips Only)

LIMITS AT INDICATED TEMPERATURE (oC)

25

UNITS-55 -40 85 125

3

CD4049UB, CD4050B

DC Electrical Specifications (Continued)

LIMITS AT INDICATED TEMPERATURE (

TEST CONDITIONS

V

PARAMETER

Input High Voltage, VIH Min
CD4050B

O

(V)

4.5 - 5 3.5 3.5 3.5 3.5 3.5 - - V
9-1077777--V

13.5 - 15 11 11 11 11 11 - - V

Input Current, IIN Max - 0,18 18 ±0.1 ±0.1 ±1 ±1-±10

V

IN

(V) VCC (V) MIN TYP MAX

o

25

-5

C)

UNITS-55 -40 85 125

±0.1 µA

AC Electrical Specifications T

PARAMETER

Propagation Delay Time
Low to High, t
CD4049UB

Propagation Delay Time
Low to High, t
CD4050B

Propagation Delay Time
High to Low, t
CD4049UB

Propagation Delay Time
High to Low, t
CD4050B

Transition Time, Low to High, t

Transition Time, High to Low, t

Input Capacitance, C
CD4049UB

Input Capacitance, C
CD4050B

PLH

PLH

PHL

PHL

TLH

THL

IN

IN

= 25oC, Input tr, tf = 20ns, CL = 50pF, RL = 200kΩ

A

TEST CONDITIONS LIMITS (ALL PACKAGES)

IN

V

CC

5 5 60 120 ns
10 10 32 65 ns
1054590ns
15 15 25 50 ns
1554590ns

5 5 70 140 ns
10 10 40 80 ns
1054590ns
15 15 30 60 ns
1554080ns

5 5 32 65 ns
10 10 20 40 ns
1051530ns
15 15 15 30 ns
1551020ns

5 5 55 110 ns
10 10 22 55 ns
10 5 50 100 ns
15 15 15 30 ns
15 5 50 100 ns

5 5 80 160 ns
10 10 40 80 ns
15 15 30 60 ns

5 5 30 60 ns
10 10 20 40 ns
15 15 15 30 ns

- - 15 22.5 pF

- - 5 7.5 pF

TYP MAX

UNITSV

4