TEXAS INSTRUMENTS CC2530F32, CC2530F64, CC2530F128, CC2530F256 Technical data

CC2530F32, CC2530F64
CC2530F128, CC2530F256
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SWRS081B –APRIL 2009– REVISED FEBRUARY 2011
A True System-on-Chip Solution for 2.4-GHz IEEE 802.15.4 and ZigBee Applications
Check for Samples: CC2530F32, CC2530F64, CC2530F128, CC2530F256
1

FEATURES

2345
RF/Layout2.4-GHz IEEE 802.15.4 Compliant RF
Timers (One 16-Bit, Two 8-Bit)
– IR Generation Circuitry
Transceiver – 32-kHz Sleep Timer With Capture
– Excellent Receiver Sensitivity and – CSMA/CA Hardware Support
Robustness to Interference
Programmable Output Power Up to 4.5 dBmVery Few External Components
Accurate Digital RSSI/LQI SupportBattery Monitor and Temperature Sensor12-Bit ADC With Eight Channels and
Only a Single Crystal Needed for Configurable Resolution
Asynchronous Networks
6-mm × 6-mm QFN40 Package
AES Security CoprocessorTwo Powerful USARTs With Support for
Suitable for Systems Targeting Compliance Several Serial Protocols
With Worldwide Radio-Frequency Regulations: ETSI EN 300 328 and EN 300 440 (Europe), FCC CFR47 Part 15 (US) and ARIB STD-T-66 (Japan)
Low PowerActive-Mode RX (CPU Idle): 24 mAActive Mode TX at 1 dBm (CPU Idle): 29 mAPower Mode 1 (4 μs Wake-Up): 0.2 mAPower Mode 2 (Sleep Timer Running): 1 μAPower Mode 3 (External Interrupts): 0.4 μAWide Supply-Voltage Range (2 V3.6 V)
21 General-Purpose I/O Pins
(19 × 4 mA, 2 × 20 mA)
Watchdog Timer
Development ToolsCC2530 Development KitCC2530 ZigBee®Development Kit – CC2530 RemoTIDevelopment Kit for
RF4CE
SmartRFSoftwarePacket SnifferIAR Embedded WorkbenchAvailable
Microcontroller

High-Performance and Low-Power 8051 APPLICATIONS

Microcontroller Core With Code Prefetch
– 32-, 64-, 128-, or 256-KB
In-System-Programmable Flash
– 8-KB RAM With Retention in All Power
Modes
Hardware Debug Support
2.4-GHz IEEE 802.15.4 Systems
RF4CE Remote Control Systems (64-KB Flash
and Higher)
ZigBee Systems (256-KB Flash)
Home/Building Automation
Lighting Systems
Industrial Control and Monitoring
PeripheralsPowerful Five-Channel DMAIntegrated High-Performance Op-Amp and
Low-Power Wireless Sensor Networks
Consumer Electronics
Health Care
Ultralow-Power Comparator
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2RemoTI, SmartRF, Z-Stack are trademarks of Texas Instruments. 3IAR Embedded Workbench is a trademark of IAR Systems AB. 4ZigBee is a registered trademark of the ZigBee Alliance. 5All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
© 2009–2011, Texas Instruments Incorporated
CC2530F32, CC2530F64 CC2530F128, CC2530F256
SWRS081B –APRIL 2009– REVISED FEBRUARY 2011

DESCRIPTION

The CC2530 is a true system-on-chip (SoC) solution for IEEE 802.15.4, Zigbee and RF4CE applications. It enables robust network nodes to be built with very low total bill-of-material costs. The CC2530 combines the excellent performance of a leading RF transceiver with an industry-standard enhanced 8051 MCU, in-system programmable flash memory, 8-KB RAM, and many other powerful features. The CC2530 comes in four different flash versions: CC2530F32/64/128/256, with 32/64/128/256 KB of flash memory, respectively. The CC2530 has various operating modes, making it highly suited for systems where ultralow power consumption is required. Short transition times between operating modes further ensure low energy consumption.
Combined with the industry-leading and golden-unit-status ZigBee protocol stack ( Z-Stack) from Texas Instruments, the CC2530F256 provides a robust and complete ZigBee solution.
Combined with the golden-unit-status RemoTI stack from Texas Instruments, the CC2530F64 and higher provide a robust and complete ZigBee RF4CE remote-control solution.
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Product Folder Link(s): CC2530F32 CC2530F64 CC2530F128 CC2530F256
RESET
WATCHDOG
TIMER
IRQ CTRL
FLASH CTRL
DEBUG
INTERFACE
CLOCK MUX
and
CALIBRATION
DMA
8051 CPU
CORE
32-MHz
CRYSTAL OSC
32.768-kHz
CRYSTAL OSC
HIGH-
SPEED
RC-OSC
POWER MANAGEMENT CONTROLLER
USART 0
USART 1
TIMER 1 (16-Bit)
TIMER 3 (8-Bit)
TIMER 4 (8-Bit)
TIMER 2
(IEEE 802.15.4 MAC TIMER)
32/64/128/256-KB
FLASH
8-KB SRAM
ON-CHIP VOLTAGE
REGULATOR
POWER-ON RESET
BROWN OUT
VDD (2 V–3.6 V)
DCOUPL
RESET_N
XOSC_Q2
XOSC_Q1
P2_4
P1_7
P0_7
P2_3
P1_6
P0_6
P2_2
P1_5
P0_5
P1_2
P0_2
P2_1
P1_4
P0_4
P1_1
P0_1
P2_0
P1_3
P0_3
P1_0
P0_0
B0301-02
RADIO DATA INTERFACE
CSMA/CA STROBE PROCESSOR
RADIO REGISTERS
MODULATOR
DEMODULATOR
AND AGC
RECEIVE
CHAIN
TRANSMIT
CHAIN
FREQUENCY
SYNTHESIZER
SYNTH
RF_P RF_N
FIFO and FRAME CONTROL
12-BIT
ADC
DS
AES
ENCRYPTION
AND
DECRYPTION
MEMORY ARBITER
SLEEP TIMER
32-kHz
RC-OSC
I/O CONTROLLER
DIGITAL
ANALOG
MIXED
ANALOG
COMPARATOR
OP-AMP
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CC2530F32, CC2530F64
CC2530F128, CC2530F256
SWRS081B –APRIL 2009– REVISED FEBRUARY 2011
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
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Product Folder Link(s): CC2530F32 CC2530F64 CC2530F128 CC2530F256
CC2530F32, CC2530F64 CC2530F128, CC2530F256
SWRS081B –APRIL 2009– REVISED FEBRUARY 2011

ABSOLUTE MAXIMUM RATINGS

(1)
MIN MAX UNIT
Supply voltage All supply pins must have the same voltage –0.3 3.9 V Voltage on any digital pin V
–0.3 VDD + 0.3,
Input RF level 10 dBm Storage temperature range –40 125 °C
ESD
(2)
All pads, according to human-body model, JEDEC STD 22, method A114 2 kV According to charged-device model, JEDEC STD 22, method C101 500 V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) CAUTION: ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage.

RECOMMENDED OPERATING CONDITIONS

MIN MAX UNIT
Operating ambient temperature range, T
A
–40 125 °C
Operating supply voltage 2 3.6 V

ELECTRICAL CHARACTERISTICS

Measured on Texas Instruments CC2530 EM reference design with TA= 25°C and VDD = 3 V, unless otherwise noted. Boldface limits apply over the entire operating range, TA= 40°C to 125°C, VDD = 2 V to 3.6 V, and fc= 2394 MHz to 2507 MHz.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Digital regulator on. 16-MHz RCOSC running. No radio, crystals, or peripherals active. Medium CPU activity: normal flash access
32-MHz XOSC running. No radio or peripherals active. Medium CPU activity: normal flash access
32-MHz XOSC running, radio in RX mode, –50-dBm input power, no peripherals active, CPU idle
32-MHz XOSC running, radio in RX mode at -100-dBm input power (waiting for signal), no
I
I
Core current
core
consumption
Peripheral Current Consumption (Adds to core current I Timer 1 Timer running, 32-MHz XOSC used 90 μA Timer 2 Timer running, 32-MHz XOSC used 90 μA Timer 3 Timer running, 32-MHz XOSC used 60 μA Timer 4 Timer running, 32-MHz XOSC used 70 μA
peri
Sleep timer Including 32.753-kHz RCOSC 0.6 μA ADC When converting 1.2 mA
Flash
peripherals active, CPU idle 32-MHz XOSC running, radio in TX mode, 1-dBm output power, no peripherals active, CPU idle 28.7 mA 32-MHz XOSC running, radio in TX mode, 4.5-dBm output power, no peripherals active, CPU
idle Power mode 1. Digital regulator on; 16-MHz RCOSC and 32-MHz crystal oscillator off;
32.768-kHz XOSC, POR, BOD and sleep timer active; RAM and register retention Power mode 2. Digital regulator off; 16-MHz RCOSC and 32-MHz crystal oscillator off;
32.768-kHz XOSC, POR, and sleep timer active; RAM and register retention Power mode 3. Digital regulator off; no clocks; POR active; RAM and register retention 0.4 1 μA
Erase 1 mA Burst write peak current 6 mA
(1) Normal flash access means that the code used exceeds the cache storage, so cache misses happen frequently.
(1)
, no RAM access
(1)
, no RAM access
for each peripheral unit activated)
core
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3.9
3.4 mA
6.5 8.9 mA
20.5 mA
24.3 29.6 mA
33.5 39.6 mA
0.2 0.3 mA
1 2 μA

GENERAL CHARACTERISTICS

Measured on Texas Instruments CC2530 EM reference design with TA= 25°C and VDD = 3 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
WAKE-UP AND TIMING
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GENERAL CHARACTERISTICS (continued)
Measured on Texas Instruments CC2530 EM reference design with TA= 25°C and VDD = 3 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power mode 1 active 4 μs
Power mode 2 or 3 active 0.1 ms
Active TX or RX
RX/TX and TX/RX turnaround 192 μs
RADIO PART
RF frequency range 2394 2507 MHz Radio baud rate As defined by [1] 250 kbps
Radio chip rate As defined by [1] 2 MChip/s Flash erase cycles 20 k cycles Flash page size 2 KB
Digital regulator on, 16-MHz RCOSC and 32-MHz crystal oscillator off. Start-up of 16-MHz RCOSC
Digital regulator off, 16-MHz RCOSC and 32-MHz crystal oscillator off. Start-up of regulator and 16-MHz RCOSC
Initially running on 16-MHz RCOSC, with 32-MHz XOSC OFF
With 32-MHz XOSC initially on 192 μs
Programmable in 1-MHz steps, 5 MHz between channels for compliance with [1]
SWRS081B –APRIL 2009– REVISED FEBRUARY 2011
0.5 ms
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CC2530F32, CC2530F64 CC2530F128, CC2530F256
SWRS081B –APRIL 2009– REVISED FEBRUARY 2011

RF RECEIVE SECTION

Measured on Texas Instruments CC2530 EM reference design with TA= 25°C, VDD = 3 V, and fc= 2440 MHz, unless otherwise noted. Boldface limits apply over the entire operating range, TA= 40°C to 125°C, VDD = 2 V to 3.6 V, and fc= 2394 MHz to 2507 MHz.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Receiver sensitivity dBm
Saturation (maximum input level) 10 dBm
Adjacent-channel rejection, 5-MHz channel spacing
Adjacent-channel rejection, –5-MHz channel spacing
Alternate-channel rejection, 10-MHz channel spacing
Alternate-channel rejection, –10-MHz channel spacing
Channel rejection
20 MHz 802.15.4 modulated channel, stepped through all channels 57 dB ≤ –20 MHz 57
Co-channel rejection modulated at the same frequency as the desired signal. Signal –3 dB
Blocking/desensitization 5 MHz from band edge Wanted signal 3 dB above the sensitivity level, CW jammer, –33
10 MHz from band edge PER = 1%. Measured according to EN 300 440 class 2. –33 20 MHz from band edge –32 50 MHz from band edge –31
5 MHz from band edge 3510 MHz from band edge 3520 MHz from band edge 3450 MHz from band edge 34
Spurious emission. Only largest spurious emission stated within each band.
30 MHz–1000 MHz < 1 GHz–12.75 GHz
Frequency error tolerance Symbol rate error tolerance
(1) Difference between center frequency of the received RF signal and local oscillator frequency. (2) Difference between incoming symbol rate and the internally generated symbol rate
(1)
(2)
PER = 1%, as specified by [1] [1] requires –85 dBm
PER = 1%, as specified by [1] [1] requires –20 dBm
Wanted signal –82 dBm, adjacent modulated channel at 5 MHz, PER = 1 %, as specified by [1].
[1] requires 0 dB Wanted signal –82 dBm, adjacent modulated channel
at –5 MHz, PER = 1 %, as specified by [1]. [1] requires 0 dB
Wanted signal –82 dBm, adjacent modulated channel at 10 MHz, PER = 1%, as specified by [1]
[1] requires 30 dB Wanted signal –82 dBm, adjacent modulated channel
at –10 MHz, PER = 1 %, as specified by [1] [1] requires 30 dB
Wanted signal at –82 dBm. Undesired signal is an IEEE from 2405 to 2480 MHz. Signal level for PER = 1%.
Wanted signal at –82 dBm. Undesired signal is 802.15.4 level for PER = 1%.
Conducted measurement with a 50-single-ended load. Suitable for systems targeting compliance with EN 300 328, dBm EN 300 440, FCC CFR47 Part 15 and ARIB STD-T-66.
[1] requires minimum 80 ppm ±150 ppm [1] requires minimum 80 ppm ±1000 ppm
–97 –92
49 dB
49 dB
57 dB
57 dB
8057
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–88
dBm
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CC2530F32, CC2530F64
CC2530F128, CC2530F256
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RF TRANSMIT SECTION

Measured on Texas Instruments CC2530 EM reference design with TA= 25°C, VDD = 3 V and fc= 2440 MHz, unless otherwise noted. Boldface limits apply over the entire operating range, TA= 40°C to 125°C, VDD = 2 V to 3.6 V and fc= 2394 MHz to 2507 MHz.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Delivered to a single-ended 50-load through a balun using
Nominal output power dBm
Programmable output power 32 dB range
Spurious emissions Max recommended output power setting Measured conducted 25 MHz–1000 MHz (outside restricted bands) –60
according to stated regulations. Only largest spurious emission stated within each band.
Error vector magnitude (EVM) 2%
Optimum load impedance 69 + j29
(1) Texas Instruments CC2530 EM reference design is suitable for systems targeting compliance with EN 300 328, EN 300 440, FCC
CFR47 Part 15 and ARIB STD-T-66.
(2) Margins for passing conducted requirements at the third harmonic can be improved by using a simple band-pass filter connected
between matching network and RF connector (1.8 pF in parallel with 1.6 nH); this filter must be connected to a good RF ground.
(3) Margins for passing FCC requirements at 2483.5 MHz and above when transmitting at 2480 MHz can be improved by using a lower
output-power setting or having less than 100% duty cycle.
maximum-recommended output-power setting [1] requires minimum –3 dBm
(1)
25 MHz–2400 MHz (within FCC restricted bands) –60 25 MHz–1000 MHz (within ETSI restricted bands) –60 1800–1900 MHz (ETSI restricted band) –57
5150–5300 MHz (ETSI restricted band) At 2 × fcand 3 × fc(FCC restricted band) At 2 × fcand 3 × fc(ETSI EN 300-440 and EN 300-328) 1 GHz–12.75 GHz (outside restricted bands) At 2483.5 MHz and above (FCC restricted band)
fc= 2480 MHz
Measured as defined by [1] using maximum-recommended output-power setting
[1] requires maximum 35%. Differential impedance as seen from the RF port (RF_P and RF_N)
towards the antenna
(3)
SWRS081B –APRIL 2009– REVISED FEBRUARY 2011
0 4.5 8
8 10
55
(2)
423153
42
dBm
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SWRS081B –APRIL 2009– REVISED FEBRUARY 2011

32-MHz CRYSTAL OSCILLATOR

Measured on Texas Instruments CC2530 EM reference design with TA= 25°C and VDD = 3 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Crystal frequency 32 MHz Crystal frequency accuracy
requirement ESR Equivalent series resistance 6 60 C
0
C
L
(1) Including aging and temperature dependency, as specified by [1]
Crystal shunt capacitance 1 7 pF
Crystal load capacitance 10 16 pF
Start-up time 0.3 ms
Power-down guard time requirement is valid for all modes of operation. The 3 ms
(1)
The crystal oscillator must be in power down for a guard time before it is used again. This
need for power-down guard time can vary with crystal type and load.
–40 40 ppm

32.768-kHz CRYSTAL OSCILLATOR

Measured on Texas Instruments CC2530 EM reference design with TA= 25°C and VDD = 3 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Crystal frequency 32.768 kHz
Crystal frequency accuracy
requirement ESR Equivalent series resistance 40 130 k C
0
C
L
(1) Including aging and temperature dependency, as specified by [1]
Crystal shunt capacitance 0.9 2 pF
Crystal load capacitance 12 16 pF
Start-up time 0.4 s
(1)
–40 40 ppm
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32-kHz RC OSCILLATOR

Measured on Texas Instruments CC2530 EM reference design with TA= 25°C and VDD = 3 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Calibrated frequency Frequency accuracy after calibration ±0.2% Temperature coefficient Supply-voltage coefficient Calibration time
(1) The calibrated 32-kHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 977. (2) Frequency drift when temperature changes after calibration (3) Frequency drift when supply voltage changes after calibration (4) When the 32-kHz RC oscillator is enabled, it is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillator
is performed while SLEEPCMD.OSC32K_CALDIS is 0.
(1)
(2)
(3)
(4)
32.753 kHz
0.4 %/°C 3 %/V 2 ms
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CC2530F32, CC2530F64
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16-MHz RC OSCILLATOR

Measured on Texas Instruments CC2530 EM reference design with TA= 25°C and VDD = 3 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Frequency Uncalibrated frequency accuracy ±18% Calibrated frequency accuracy ±0.6% ±1% Start-up time 10 μs Initial calibration time
(1) The calibrated 16-MHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 2. (2) When the 16-MHz RC oscillator is enabled, it is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillator
(1)
(2)
is performed while SLEEPCMD.OSC_PD is set to 0.

RSSI/CCA CHARACTERISTICS

Measured on Texas Instruments CC2530 EM reference design with TA= 25°C and VDD = 3 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RSSI range 100 dB Absolute uncalibrated RSSI/CCA accuracy ±4 dB RSSI/CCA offset Step size (LSB value) 1 dB
(1) Real RSSI = Register value – offset
(1)
SWRS081B –APRIL 2009– REVISED FEBRUARY 2011
16 MHz
50 μs
73 dB

FREQEST CHARACTERISTICS

Measured on Texas Instruments CC2530 EM reference design with TA= 25°C and VDD = 3 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FREQEST range ±250 kHz FREQEST accuracy ±40 kHz FREQEST offset Step size (LSB value) 7.8 kHz
(1) Real FREQEST = Register value – offset
(1)
20 kHz

FREQUENCY SYNTHESIZER CHARACTERISTICS

Measured on Texas Instruments CC2530 EM reference design with TA= 25°C, VDD = 3 V and fc= 2440 MHz, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
At ±1-MHz offset from carrier –110
Phase noise, unmodulated carrier At ±2-MHz offset from carrier –117 dBc/Hz
At ±5-MHz offset from carrier –122

ANALOG TEMPERATURE SENSOR

Measured on Texas Instruments CC2530 EM reference design with TA= 25°C and VDD = 3 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Output at 25°C 1480 12-bit ADC Temperature coefficient 4.5 /1°C Voltage coefficient 1 /0.1 V Initial accuracy without calibration ±10 °C Accuracy using 1-point calibration (entire
temperature range) Current consumption when enabled (ADC
current not included)
Measured using integrated ADC using internal bandgap voltage reference and maximum resolution
±5 °C
0.5 mA
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SWRS081B –APRIL 2009– REVISED FEBRUARY 2011

OP-AMP CHARACTERISTICS

TA= 25°C, VDD = 3 V . All measurement results are obtained using the CC2530 reference designs post-calibration.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Chopping Configuration, Register APCFG = 0x07, OPAMPMC = 0x03, OPAMPC = 0x01
Output maximum voltage VDD – 0.07 V Output minimum voltage 0.07 V Open-loop gain 108 dB Gain-bandwidth product 2 MHz Slew rate 107 V/μs Input maximum voltage VDD + 0.13 V Intput minimum voltage –55 mV Input offset voltage 40 μV
CMRR Common-mode rejection ratio 90 dB
Supply current 0.4 mA
Input noise voltage nV/(Hz)
Non-Chopping Configuration, Register APCFG = 0x07, OPAMPMC = 0x00, OPAMPC = 0x01
Output maximum voltage VDD – 0.07 V Output minimum voltage 0.07 V Open-loop gain 108 dB Gain-bandwidth product 2 MHz Slew rate 107 V/μs Input maximum voltage VDD + 0.13 V Intput minimum voltage –55 mV Input offset voltage 0.8 mV
CMRR Common-mode rejection ratio 90 dB
Supply current 0.4 mA
Input noise voltage nV/(Hz)
f = 0.01 Hz to 1 Hz 1.1 f = 0.1 Hz to 10 Hz 1.7
f = 0.01 Hz to 1 Hz 60 f = 0.1 Hz to 10 Hz 65
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COMPARATOR CHARACTERISTICS

TA= 25°C, VDD = 3 V. All measurement results are obtained using the CC2530 reference designs, post-calibration.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Common-mode maximum voltage VDD V Common-mode minimum voltage –0.3 Input offset voltage 1 mV Offset vs temperature 16 µV/°C Offset vs operating voltage 4 mV/V Supply current 230 nA Hysteresis 0.15 mV
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ADC CHARACTERISTICS

TA= 25°C and VDD = 3 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input voltage VDD is voltage on AVDD5 pin 0 VDD V External reference voltage VDD is voltage on AVDD5 pin 0 VDD V External reference voltage differential VDD is voltage on AVDD5 pin 0 VDD V Input resistance, signal Using 4-MHz clock speed 197 k Full-scale signal
(1)
ENOB
THD
CMRR Common-mode rejection ratio >84 dB
DNL
(1)
INL
SINAD (–THD+N)
Effective number of bits bits
Useful power bandwidth 7-bit setting, both single and differential 0–20 kHz
(1)
Total harmonic distortion dB
Signal to nonharmonic ratio
Crosstalk >84 dB Offset Midscale –3 mV
Gain error 0.68 %
(1)
Differential nonlinearity LSB
Integral nonlinearity LSB
(1)
Signal-to-noise-and-distortion dB
Conversion time μs
Power consumption 1.2 mA Internal reference voltage 1.15 V Internal reference VDD coefficient 4 mV/V Internal reference temperature coefficient 0.4 mV/10°C
(1) Measured with 300-Hz sine-wave input and VDD as reference.
(1)
(1)
Peak-to-peak, defines 0 dBFS 2.97 V Single-ended input, 7-bit setting 5.7 Single-ended input, 9-bit setting 7.5 Single-ended input, 10-bit setting 9.3 Single-ended input, 12-bit setting 10.8 Differential input, 7-bit setting 6.5 Differential input, 9-bit setting 8.3 Differential input, 10-bit setting 10.0 Differential input, 12-bit setting 11.5
Single-ended input, 12-bit setting, –6 dBFS –75.2 Differential input, 12-bit setting, –6 dBFS –86.6 Single-ended input, 12-bit setting 70.2 Differential input, 12-bit setting 79.3 Single-ended input, 12-bit setting, –6 dBFS 78.8 Differential input, 12-bit setting, –6 dBFS 88.9 Differential input, 12-bit setting, 1-kHz sine (0 dBFS),
limited by ADC resolution Single-ended input, 12-bit setting, 1-kHz sine (0 dBFS),
limited by ADC resolution
12-bit setting, mean 0.05 12-bit setting, maximum 0.9 12-bit setting, mean 4.6 12-bit setting, maximum 13.3 Single-ended input, 7-bit setting 35.4 Single-ended input, 9-bit setting 46.8 Single-ended input, 10-bit setting 57.5 Single-ended input, 12-bit setting 66.6 Differential input, 7-bit setting 40.7 Differential input, 9-bit setting 51.6 Differential input, 10-bit setting 61.8 Differential input, 12-bit setting 70.8 7-bit setting 20 9-bit setting 36 10-bit setting 68 12-bit setting 132
SWRS081B –APRIL 2009– REVISED FEBRUARY 2011
dB
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