Texas Instruments CC2511F8, CC2511 Datasheet

CC2510Fx / CC2511Fx

SWRS055D Page 1 of 243

Low-Power SoC (System-on-Chip) with MCU, Memory,

2.4 GHz RF Transceiver, and USB Controller

Applications

• 2400-2483.5 MHz ISM/SRD band systems

• Consumer electronics

• Wireless keyboard and mouse

• Wireless voice-quality audio

• RF enabled remote controls

• Wireless sports and leisure equipment

• Low power telemetry

•

CC2511Fx

: USB dongles

Product Description

The

CC2510Fx/CC2511Fx

is a true low-cost 2.4
GHz system-on-chip (SoC) designed for low­power wireless applications. The

CC2510Fx/CC2511Fx

combines the excellent
performance of the state-of-the-art RF
transceiver CC2500 with an industry-standard
enhanced 8051 MCU, up to 32 kB of in-system
programmable flash memory and 4 kB of
RAM, and many other powerful features. The
small 6x6 mm package makes it very suited
for applications with size limitations.

The

CC2510Fx/CC2511Fx

is highly suited for
systems where very low power consumption is
required. This is ensured by several advanced
low-power operating modes. The

CC2511Fx

adds a full-speed USB controller to the feature
set of the

CC2510Fx

. Interfacing to a PC using
the USB interface is quick and easy, and the
high data rate (12 Mbps) of the USB interface
avoids the bottlenecks of RS-232 or low-speed
USB interfaces.

Key Features

• Radio

o High-performance RF transceiver based on

the market-leading CC2500

o Excellent receiver selectivity and blocking

performance

o High sensitivity (-103 dBm at 2.4 kBaud)
o Programmable data rate up to 500 kBaud
o Programmable output power up to 1 dBm for

all supported frequencies

o Frequency range: 2400 – 2483.5 MHz
o Digital RSSI / LQI support

• Current Consumption

o Low current consumption (RX: 17.1 mA @

2.4 kBaud, TX: 18.5 mA @ -6 dBm output
power)

o 0.3 µA in PM3 (the operating mode with the

lowest power consumption)

• MCU, Memory, and Peripherals

o High performance and low power 8051

microcontroller core.

o 8/16/32 kB in-system programmable flash,

and 1/2/4 kB RAM

o Full-Speed USB Controller with 1 kB USB

FIFO (

CC2511Fx

)

o I

2

S interface

o 7-12 bit ADC with up to eight inputs
o 128-bit AES security coprocessor
o Powerful DMA functionality
o Two USARTs
o 16-bit timer with DSM mode
o Three 8-bit timers
o Hardware debug support
o 21 (

CC2510Fx

) or 19 (

CC2511Fx

) GPIO pins

• General

o Wide supply voltage range (2.0V – 3.6V)
o Green package: RoHS compliant and no

antimony or bromine, 6x6mm QLP36

C2510Fx / CC2511Fx

SWRS055D Page 2 of 243

Table of Contents

1 ABBREVIATIONS.................................................................................................................................... 4

2 REGISTER CONVENTIONS.................................................................................................................. 5

3 KEY FEATURES (IN MORE DETAILS) ..............................................................................................6

3.1 HIGH-PERFORMANCE AND LOW-POWER 8051-COMPATIBLE MICROCONTROLLER....................................... 6

3.2 8/16/32 KB NON-VOLATILE PROGRAM MEMORY AND 1/2/4 KB DATA MEMORY......................................... 6

3.3 FULL-SPEED USB CONTROLLER (

CC2511F

X

)................................................................................................ 6

3.4 I2S INTERFACE.............................................................................................................................................. 6

3.5 HARDWARE AES ENCRYPTION/DECRYPTION............................................................................................... 6

3.6 PERIPHERAL FEATURES ................................................................................................................................6

3.7 LOW POWER ................................................................................................................................................. 6

3.8 2.4 GHZ RADIO WITH BASEBAND MODEM ................................................................................................... 7

4 ABSOLUTE MAXIMUM RATINGS...................................................................................................... 8

5 OPERATING CONDITIONS ..................................................................................................................8

5.1

CC2510F

X

OPERATING CONDITIONS .............................................................................................................. 8

5.2

CC2511F

X

OPERATING CONDITIONS .............................................................................................................. 8

6 GENERAL CHARACTERISTICS.......................................................................................................... 9

7 ELECTRICAL SPECIFICATIONS ...................................................................................................... 10

7.1 CURRENT CONSUMPTION ........................................................................................................................... 10

7.2 RF RECEIVE SECTION ................................................................................................................................. 13

7.3 RF TRANSMIT SECTION ..............................................................................................................................15

7.4 CRYSTAL OSCILLATORS ............................................................................................................................. 16

7.5 32.768 KHZ CRYSTAL OSCILLATOR ........................................................................................................... 17

7.6 LOW POWER RC OSCILLATOR.................................................................................................................... 18

7.7 HIGH SPEED RC OSCILLATOR .................................................................................................................... 18

7.8 FREQUENCY SYNTHESIZER CHARACTERISTICS ........................................................................................... 19

7.9 ANALOG TEMPERATURE SENSOR ............................................................................................................... 19

7.10 7-12 BIT ADC............................................................................................................................................. 20

7.11 CONTROL AC CHARACTERISTICS ............................................................................................................... 21

7.12 SPI AC CHARACTERISTICS......................................................................................................................... 22

7.13 DEBUG INTERFACE AC CHARACTERISTICS ................................................................................................ 23

7.14 PORT OUTPUTS AC CHARACTERISTICS ...................................................................................................... 24

7.15 TIMER INPUTS AC CHARACTERISTICS ........................................................................................................24

7.16 DC CHARACTERISTICS ............................................................................................................................... 24

8 PIN AND I/O PORT CONFIGURATION ............................................................................................ 26

9 CIRCUIT DESCRIPTION ..................................................................................................................... 30

9.1 CPU AND PERIPHERALS ............................................................................................................................. 31

9.2 RADIO ........................................................................................................................................................ 33

10 APPLICATION CIRCUIT..................................................................................................................... 33

10.1 BIAS RESISTOR ........................................................................................................................................... 33

10.2 BALUN AND RF MATCHING........................................................................................................................ 33

10.3 CRYSTAL .................................................................................................................................................... 34

10.4 USB (

CC2511F

X

) .........................................................................................................................................34

10.5 POWER SUPPLY DECOUPLING ..................................................................................................................... 34

10.6 PCB LAYOUT RECOMMENDATIONS............................................................................................................ 37

11 8051 CPU.................................................................................................................................................. 38

11.1 8051 INTRODUCTION ..................................................................................................................................38

11.2 MEMORY ....................................................................................................................................................38

11.3 CPU REGISTERS .........................................................................................................................................52

11.4 INSTRUCTION SET SUMMARY ..................................................................................................................... 54

11.5 INTERRUPTS................................................................................................................................................ 58

12 DEBUG INTERFACE............................................................................................................................. 68

12.1 DEBUG MODE............................................................................................................................................. 68

12.2 DEBUG COMMUNICATION...........................................................................................................................68

12.3 DEBUG LOCK BIT ....................................................................................................................................... 69

12.4 DEBUG COMMANDS.................................................................................................................................... 70

C2510Fx / CC2511Fx

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13 PERIPHERALS....................................................................................................................................... 74

13.1 POWER MANAGEMENT AND CLOCKS.......................................................................................................... 74

13.2 RESET......................................................................................................................................................... 81

13.3 FLASH CONTROLLER .................................................................................................................................. 82

13.4 I/O PORTS................................................................................................................................................... 88

13.5 DMA CONTROLLER ................................................................................................................................... 99

13.6 16-BIT TIMER, TIMER 1............................................................................................................................. 111

13.7 MAC TIMER (TIMER 2) ............................................................................................................................123

13.8 SLEEP TIMER ............................................................................................................................................ 125

13.9 8-BIT TIMERS, TIMER 3 AND TIMER 4 .......................................................................................................129

13.10 ADC......................................................................................................................................................... 140

13.11 RANDOM NUMBER GENERATOR ............................................................................................................... 146

13.12 AES COPROCESSOR.................................................................................................................................. 147

13.13 WATCHDOG TIMER................................................................................................................................... 150

13.14 USART .................................................................................................................................................... 152

13.15 I2S ............................................................................................................................................................ 163

13.16 USB CONTROLLER ...................................................................................................................................170

14 RADIO.................................................................................................................................................... 187

14.1 COMMAND STROBES ................................................................................................................................187

14.2 RADIO REGISTERS ....................................................................................................................................189

14.3 INTERRUPTS.............................................................................................................................................. 189

14.4 TX/RX DATA TRANSFER ......................................................................................................................... 191

14.5 DATA RATE PROGRAMMING..................................................................................................................... 192

14.6 RECEIVER CHANNEL FILTER BANDWIDTH................................................................................................ 192

14.7 DEMODULATOR, SYMBOL SYNCHRONIZER, AND DATA DECISION ............................................................ 193

14.8 PACKET HANDLING HARDWARE SUPPORT ............................................................................................... 194

14.9 MODULATION FORMATS........................................................................................................................... 197

14.10 RECEIVED SIGNAL QUALIFIERS AND LINK QUALITY INFORMATION......................................................... 198

14.11 FORWARD ERROR CORRECTION WITH INTERLEAVING.............................................................................. 202

14.12 RADIO CONTROL ...................................................................................................................................... 203

14.13 FREQUENCY PROGRAMMING .................................................................................................................... 206

14.14 VCO......................................................................................................................................................... 207

14.15 OUTPUT POWER PROGRAMMING .............................................................................................................. 207

14.16 SELECTIVITY ............................................................................................................................................ 209

14.17 SYSTEM CONSIDERATIONS AND GUIDELINES ............................................................................................211

14.18 RADIO REGISTERS ....................................................................................................................................213

15 VOLTAGE REGULATORS ................................................................................................................231

15.1 VOLTAGE REGULATOR POWER-ON........................................................................................................... 231

16 RADIO TEST OUTPUT SIGNALS..................................................................................................... 231

17 REGISTER OVERVIEW..................................................................................................................... 232

18 PACKAGE DESCRIPTION (QLP 36)................................................................................................ 236

18.1 RECOMMENDED PCB LAYOUT FOR PACKAGE (QLP 36) ..........................................................................237

18.2 SOLDERING INFORMATION........................................................................................................................ 237

18.3 TRAY SPECIFICATION ............................................................................................................................... 237

18.4 CARRIER TAPE AND REEL SPECIFICATION ................................................................................................238

19 ORDERING INFORMATION............................................................................................................. 238

20 REFERENCES ......................................................................................................................................239

21 GENERAL INFORMATION............................................................................................................... 240

21.1 DOCUMENT HISTORY ............................................................................................................................... 240

21.2 PRODUCT STATUS DEFINITIONS ............................................................................................................... 241

22 ADDRESS INFORMATION................................................................................................................ 242

23 TI WORLDWIDE TECHNICAL SUPPORT..................................................................................... 242

C2510Fx / CC2511Fx

SWRS055D Page 4 of 243

1 Abbreviations

∆Σ

Delta-Sigma

ADC Analog to Digital Converter

AES Advanced Encryption Standard

AGC Automatic Gain Control

ARIB Association of Radio Industries and

Businesses

BCD Binary Coded Decimal

BER Bit Error Rate

BOD Brown Out Detector

CBC Cipher Block Chaining

CBC-MAC Cipher Block Chaining Message

Authentication Code

CCA Clear Channel Assessment

CCM Counter mode + CBC-MAC

CFB Cipher Feedback

CFR Code of Federal Regulations

CMOS Complementary Metal Oxide Semiconductor

CPU Central Processing Unit

CRC Cyclic Redundancy Check

CTR Counter mode (encryption)

DAC Digital to Analog Converter

DMA Direct Memory Access

DSM Delta-Sigma Modulator

ECB Electronic Code Book

EM Evaluation Module

ENOB Effective Number of Bits

EP{0-5} USB Endpoints 0 – 5

ESD Electro Static Discharge

ESR Equivalent Series Resistance

ETSI European Telecommunications Standard

Institute

FCC Federal Communications Commission

FIFO First In First Out

GPIO General Purpose Input / Output

HSSD High Speed Serial Debug

I

2

S Inter-IC Sound

I/O Input / Output

I/Q In-phase / Quadrature-phase

IF Intermediate Frequency

IOC I/O Controller

ISM Industrial, Scientific and Medical

ISR Interrupt Service Routine

IV Initialization Vector

JEDEC Joint Electron Device Engineering Council

kbps kilo bits per second

KB Kilo Bytes (1024 bytes)

LFSR Linear Feedback Shift Register

LNA Low-Noise Amplifier

LO Local Oscillator

LQI Link Quality Indication

LSB Least Significant Bit / Byte

MAC Medium Access Control

MCU Microcontroller Unit

MISO Master In Slave Out

MOSI Master Out Slave In

MSB Most Significant Bit / Byte

NA Not Applicable

OFB Output Feedback (encryption)

PA Power Amplifier

PCB Printed Circuit Board

PER Packet Error Rate

PLL Phase Locked Loop

PM{0-3} Power Mode 0-3

PMC Power Management Controller

POR Power On Reset

PWM Pulse Width Modulator

Px_n Port x pin n (x = 0, 1, or 2 and n = 0, 1, 2, .., 7)

QLP Quad Leadless Package

RAM Random Access Memory

RCOSC RC Oscillator

RF Radio Frequency

RoHS Restriction on Hazardous Substances

RSSI Receive Signal Strength Indicator

RX Receive

SCK Serial Clock

SFD Start of Frame Delimiter

SFR Special Function Register

SINAD Signal-to-noise and distortion ratio

SPI Serial Peripheral Interface

SRAM Static Random Access Memory

T/R Transmit / Receive

TX Transmit

UART Universal Asynchronous Receiver/Transmitter

USART Universal Synchronous/Asynchronous

Receiver/Transmitter

USB Universal Serial Bus

VCO Voltage Controlled Oscillator

VGA Variable Gain Amplifier

WDT Watchdog Timer

XOSC Crystal Oscillator

C2510Fx / CC2511Fx

SWRS055D Page 5 of 243

2 Register Conventions

Each SFR is described in a separate table. The table heading is given in the following format:

REGISTER NAME (SFR Address) - Register Description.

Each RF register is described in a separate table. The table heading is given in the following format:

XDATA Address: REGISTER NAME - Register Description

All register descriptions include a symbol denoted R/W describing the accessibility of each bit in the
register. The register values are always given in binary notation unless prefixed by ‘0x’, which
indicates hexadecimal notation.

Symbol Access Mode

R/W Read/write

R Read only

R0 Read as 0

R1 Read as 1

W Write only

W0 Write as 0

W1 Write as 1

H0 Hardware clear

H1 Hardware set

Table 1: Register Bit Conventions

C2510Fx / CC2511Fx

SWRS055D Page 6 of 243

3 Key Features (in more details)

3.1 High-Performance and Low-Power

8051-Compatible Microcontroller

• Optimized 8051 core which typically

gives 8x the performance of a standard
8051

• Two data pointers

• In-circuit interactive debugging is

supported by the IAR Embedded
Workbench through a simple two-wire
serial interface

3.2 8/16/32 kB Non-volatile Program

Memory and 1/2/4 kB Data Memory

• 8, 16, or 32 kB of non-volatile flash

memory, in-system programmable
through a simple two-wire interface or
by the 8051 core

• Minimum flash memory endurance:

1000 write/erase cycles

• Programmable read and write lock of

portions of flash memory for software
security

• 1, 2, or 4 kB of internal SRAM

3.3 Full-Speed USB Controller (

CC2511Fx

)

• 5 bi-directional endpoints in addition to

control endpoint 0

• Full-Speed, 12 Mbps transfer rate

• Support for Bulk, Interrupt, and

Isochronous endpoints

• 1024 bytes of dedicated endpoint FIFO

memory

• 8 – 512 byte data packet size supported

• Configurable FIFO size for IN and OUT

direction of endpoint

3.4 I

2

S Interface

• Industry standard I

2

S interface for

transfer of digital audio data

• Full duplex

• Mono and stereo support

• Configurable sample rate and sample

size

• Support for µ-law compression and

expansion

• Typically used to connect to external

DAC or ADC

3.5 Hardware AES Encryption/Decryption

• 128-bit AES supported in hardware

coprocessor

3.6 Peripheral Features

• Powerful DMA Controller

• Power On Reset/Brown-Out Detection

• ADC with eight individual input

channels, single-ended or differential
(

CC2511Fx

has six channels) and

configurable resolution

• Programmable watchdog timer

• Five timers: one general 16-bit timer

with DSM mode, two general 8-bit
timers, one MAC timer, and one sleep
timer

• Two programmable USARTs for

master/slave SPI or UART operation

• 21 configurable general-purpose digital

I/O-pins (

CC2511Fx

has 19)

• Random number generator

3.7 Low Power

• Four flexible power modes for reduced

power consumption

• System can wake up on external

interrupt or when the Sleep Timer
expires

• 0.5 µA current consumption in PM2,

where external interrupts or the Sleep
Timer can wake up the system

• 0.3 µA current consumption in PM3,

where external interrupts can wake up
the system

• Low-power fully static CMOS design

• System clock source is either a high

speed crystal oscillator (24 – 27 MHz for

CC2510Fx

and 48 MHz for

CC2511Fx

) or a
high speed RC oscillator (12 – 13.5 MHz
for

CC2510Fx

and 12 MHz for

CC2511Fx

).
The high speed crystal oscillator must
be used when the radio is active.

C2510Fx / CC2511Fx

SWRS055D Page 7 of 243

• Clock source for ultra-low power

operation can be either a low-power RC
oscillator or an optional 32.768 kHz
crystal oscillator

• Very fast transition to active mode from

power modes enables ultra low average
power consumption in low duty-cycle
systems

3.8 2.4 GHz Radio with Baseband Modem

• Based on the industry leading

CC2500

radio core

• Few external components: On-chip

frequency synthesizer, no external filters
or RF switch needed

• Flexible support for packet oriented

systems: On-chip support for sync word
detection, address check, flexible packet
length, and automatic CRC handling

• Supports use of DMA for both RX and

TX resulting in minimal CPU intervention
even on high data rates

• Programmable channel filter bandwidth

• 2-FSK, GFSK and MSK supported

• Optional automatic whitening and de-

whitening of data

• Programmable Carrier Sense (CS)

indicator

• Programmable Preamble Quality

Indicator for detecting preambles and
improved protection against sync word
detection in random noise

• Support for automatic Clear Channel

Assessment (CCA) before transmitting
(for listen-before-talk systems

• Support for per-package Link Quality

Indication (LQI)

• Suited for systems targeting compliance

with EN 300 328, EN 300 440, FCC
CFR47 Part 15 and ARIB STD-T-66

• When transmitting in band 2480-

2483.5MHz under FCC, duty-cycling or
reducing output power might be needed

C2510Fx / CC2511Fx

SWRS055D Page 8 of 243

4 Absolute Maximum Ratings

Under no circumstances must the absolute maximum ratings given in Table 2 be violated. Stress
exceeding one or more of the limiting values may cause permanent damage to the device.

Parameter Min Max Units Condition

Supply voltage (VDD) -0.3 3.9 V All supply pins must have the same voltage

Voltage on any digital pin -0.3 VDD + 0.3,

max 3.9

V

Voltage on the pins RF_P, RF_N
and DCOUPL

-0.3 2.0 V

Voltage ramp-up rate 120 kV/µs

Input RF level +10 dBm

Storage temperature range -50 150

°C

Device not programmed

Solder reflow temperature 260

°C

According to IPC/JEDEC J-STD-020D

ESD

CC2510Fx

750 V According to JEDEC STD 22, method A114, Human

Body Model (HBM)

ESD

CC2510Fx

500 V According to JEDEC STD 22, C101C, Charged Device

Model (CDM)

ESD

CC2511x

750 V According to JEDEC STD 22, method A114, Human

Body Model (HBM)

ESD

CC2511x

500 V According to JEDEC STD 22, C101C, Charged Device

Model (CDM)

Table 2: Absolute Maximum Ratings

Caution! ESD sensitive device.
Precaution should be used when handling
the device in order to prevent permanent
damage.

5 Operating Conditions

5.1

CC2510Fx

Operating Conditions

The operating conditions for

CC2510Fx

are listed in Table 3 below.

Parameter Min Max Unit Condition

Operating ambient temperature, TA -40 85

°C

Operating supply voltage (VDD) 2.0 3.6 V All supply pins must have the same voltage

Table 3: Operating Conditions for

CC2510Fx

5.2

CC2511Fx

Operating Conditions

The operating conditions for

CC2511Fx

are listed in Table 4 below.

Parameter Min Max Unit Condition

Operating ambient temperature, TA 0 85

°C

Operating supply voltage (VDD) 3.0 3.6 V All supply pins must have the same voltage

Table 4: Operating Conditions for

CC2511Fx

C2510Fx / CC2511Fx

SWRS055D Page 9 of 243

6 General Characteristics

TA = 25 °C, VDD = 3.0 V if nothing else stated

Parameter Min Typ Max Unit Condition/Note

Radio part

Frequency range 2400 2483.5 MHz There will be spurious signals at n/2·crystal

oscillator frequency (n is an integer number).
RF frequencies at n/2·crystal oscillator
frequency should therefore be avoided (e.g.
2405, 2418, 2431, 2444, 2457, 2470 and
2483 MHz when using a 26 MHz crystal).

Data rate 1.2

1.2

26

500

250

500

kBaud

kBaud

kBaud

2-FSK

GFSK

(Shaped) MSK (also known as differential
offset QPSK)

Optional Manchester encoding (the data rate
in kbps will be half the baud rate)

Wake-Up Timing

PM1 Æ Active Mode 4 µs Digital regulator on. HS RCOSC and high

speed crystal oscillator off. 32.768 kHz
XOSC or low power RCOSC running.

SLEEP.OSC_PD=1 and CLKCON.OSC=1

PM2/3Æ Active Mode 100 µs Digital regulator off. HS RCOSC and high

speed crystal oscillator off. 32.768 kHz
XOSC or low power RCOSC running (PM2).
No crystal oscillators or RC oscillators are
running in PM3.

SLEEP.OSC_PD=1 and CLKCON.OSC=1

Table 5: General Characteristics

C2510Fx / CC2511Fx

SWRS055D Page 10 of 243

7 Electrical Specifications

7.1 Current Consumption

T

A

= 25 °C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the

CC2510EM reference design ([1]).

Parameter Min Typ Max Unit Condition

4.8 mA System clock running at 26 MHz.

4.6 mA System clock running at 24 MHz.

Active mode, full
speed (high speed
crystal oscillator)

1

.

Low CPU activity.

Digital regulator on. High speed crystal oscillator and low power

RCOSC running. No peripherals running.

Low CPU activity: No flash access (i.e. only cache hit), no RAM
access

Active mode, full
speed (HS
RCOSC)

1

.

Low CPU activity.

2.5 mA System clock running at 26 MHz.

Digital regulator on. HS RCOSC and low power RCOSC running.
System clock running at 13 MHz. No peripherals running.

Low CPU activity: No flash access (i.e. only cache hit), no RAM
access

Digital regulator on. High speed crystal oscillator and low power

RCOSC running. Radio in RX mode (sensitivity optimized
MDMCFG2.DEM_DCFILT_OFF=0)

19.8 mA 2.4 kBaud, input at sensitivity limit, system clock running at 26 MHz.

17.1 mA 2.4 kBaud, input at sensitivity limit, system clock running at 203 kHz.

19.8 mA 2.4 kBaud, input well above sensitivity limit, system clock running at
26 MHz.

21.5 mA 10 kBaud, input at sensitivity limit, system clock running at 26 MHz.

18.8 mA 10 kBaud, input at sensitivity limit, system clock running at 203 kHz.

19.0 mA 10 kBaud, input well above sensitivity limit, system clock running at
26 MHz.

22.9 mA 250 kBaud, input at sensitivity limit, system clock running at 26 MHz.

20.5 mA 250 kBaud, input at sensitivity limit, system clock running at 1.625
MHz.

19.6 mA 250 kBaud, input well above sensitivity limit, system clock running at
26 MHz. See Figure 2 for typical variation over operating conditions

19.7 mA 500 kBaud, input at sensitivity limit, system clock running at 26 MHz.

17.5 mA 500 kBaud, input at sensitivity limit, system clock running at 3.25
MHz.

16.7 mA 500 kBaud, input well above sensitivity limit

Digital regulator on. High speed crystal oscillator and low power

RCOSC running. Radio in RX mode (current optimized
MDMCFG2.DEM_DCFILT_OFF=1)

17.4 mA 2.4 kBaud, input at sensitivity limit, system clock running at 26 MHz.

14.7 mA 2.4 kBaud, input at sensitivity limit, system clock running at 203 kHz.

17.4 mA 2.4 kBaud, input well above sensitivity limit, system clock running at
26 MHz.

19.4 mA 10 kBaud, input at sensitivity limit, system clock running at 26 MHz.

15.7 mA 10 kBaud, input at sensitivity limit, system clock running at 203 kHz.

Active mode with
radio in RX

16.9 mA 10 kBaud, input well above sensitivity limit, system clock running at
26 MHz.

1

Note: In order to reduce the current consumption in active mode, the clock speed can be reduced by

setting CLKCON.CLKSPD ≠ 000 (see section 13.1 for details). Figure 1 shows typical current
consumption in active mode for different clock speeds

C2510Fx / CC2511Fx

SWRS055D Page 11 of 243

Parameter Min Typ Max Unit Condition

System clock running at 24 MHz.

Digital regulator on. High speed crystal oscillator and low power
RCOSC running. Radio in RX mode (sensitivity optimized
MDMCFG2.DEM_DCFILT_OFF=0)

20.6 mA 2.4 kBaud, input at sensitivity limit

22.1 mA 10 kBaud, input at sensitivity limit

22.7 mA 250 kBaud, input at sensitivity limit

Active mode with
radio in RX

20.8 mA 500 kBaud, input at sensitivity limit

System clock running at 26 MHz.

Digital regulator on. High speed crystal oscillator and low power
RCOSC running. Radio in TX mode

26 mA

0 dBm output power (PA_TABLE0=0xFE). See Table 7 for typical
variation over operating conditions

18.5 mA

-6 dBm output power (PA_TABLE0=0x7F)

15.5 mA

-12 dBm output power (PA_TABLE0=0x95)

Active mode with
radio in TX

26 mA System clock running at 24 MHz.

Digital regulator on. High speed crystal oscillator and low power
RCOSC running. Radio in TX mode

w

/0 dBm output power

(PA_TABLE0=0xFE)

PM0 4.3 mA Same as active mode, but the CPU is not running (see 13.1.2.2 for

details). System clock running at 26 MHz

PM1 220

µA

Digital regulator on. HS RCOSC and high speed crystal oscillator off.

32.768 kHz XOSC or low power RCOSC running (see 13.1.2.3 for
details)

PM2 0.5 1

µA

Digital regulator off. HS RCOSC and high speed crystal oscillator off.
Low power RCOSC running (see 13.1.2.4 for details)

PM3 0.3 1

µA

Digital regulator off. No crystal oscillators or RC oscillators are
running (see 13.1.2.5 for details)

Peripheral
Current
Consumption

Add to the figures above if the peripheral unit is activated

Timer 1 2.7

µA/MHz

When running

Timer 2 1.3

µA/MHz

When running

Timer 3 1.6

µA/MHz

When running

Timer 4 2

µA/MHz

When running

ADC 1.2 mA During conversion

Table 6: Current Consumption

C2510Fx / CC2511Fx

SWRS055D Page 12 of 243

Figure 1: Current Consumption (Active Mode) vs. Clock Speed

Figure 2:

Typical Variation in RX Current Consumption over Temperature and Input Power Level.

Data Rate = 250 kBaud.

Supply Voltage, VDD = 2 V Supply Voltage, VDD = 3 V Supply Voltage, VDD = 3.6 V

Temperature [°C] -40 +25 +85 -40 +25 +85 -40 +25 +85

Current [mA] 26 25.6 26 26.3 26 26.3 26.5 26.2 26.6

Table 7: Typical Variation in TX Current Consumption over Temperature and Supply Voltage

Typical Variation in RX Current Consumption over

Temperature and Input Power Level.

Data Rate = 250 kBaud

15.0

17.0

19.0

21.0

23.0

25.0

-120 -100 -80 -60 -40 -20 0

Input Power Level [dBm]

Current [mA]

-40 °C

+25 °C

+85 °C

Current Consumption Active Mode. No Peripherals Running.

f

xosc

= 26 MHz

0,0

1,0

2,0

3,0

4,0

5,0

6,0

0 2 4 6 8 10121416182022242628

Clock Speed [MHz]

Measurements done for all valid CLKCON.CLKSPD settings

(000 – 111 for HS XOSC, 001 – 111 for HS RCOSC)

Current [mA]

HS XOSC

HS RCOSC

C2510Fx / CC2511Fx

SWRS055D Page 13 of 243

7.2 RF Receive Section

T

A

= 25 °C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the

CC2510EM reference design ([1]).

Parameter Min Typ Max Unit Condition/Note

Digital channel
filter bandwidth

58 812 kHz User programmable (see Section 14.6). The bandwidth limits are

proportional to crystal frequency (given values assume a 26.0 MHz
crystal).

2.4 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0
(2-FSK, 1% packet error rate, 20 bytes packet length, 203 kHz digital channel filter bandwidth)

Receiver
sensitivity

-103

dBm

The RX current consumption can be reduced by approximately 2.4 mA
by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical sensitivity is then

-101 dBm.

The sensitivity can be improved to typically -105 dBm with

MDMCFG2.DEM_DCFILT_OFF=0

by changing registers TEST2 and

TEST1 (see Page 227). The temperature range is then from 0

o

C to +85

o

C.

Saturation -10 dBm

Adjacent
channel
rejection

23 dB Desired channel 3 dB above the sensitivity limit. 250 kHz channel

spacing

Alternate
channel
rejection

32 dB Desired channel 3 dB above the sensitivity limit. 250 kHz channel

spacing

See Figure 54 for plot of selectivity versus frequency offset

Blocking

±10 MHz offset

±20 MHz offset

±50 MHz offset

64

70

71

dB

dB

dB

Wanted signal 3 dB above sensitivity level.

Compliant with ETSI EN 300 440 class 2 receiver requirements.

10 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0

(2-FSK, 1% packet error rate, 20 bytes packet length, 232 kHz digital channel filter bandwidth)

Receiver
sensitivity

-98 dBm The RX current consumption can be reduced by approximately 2.2 mA
by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical sensitivity is then

-97 dBm.

The sensitivity can be improved to typically -100 dBm with

MDMCFG2.DEM_DCFILT_OFF=0

by changing registers TEST2 and

TEST1 (see Page 227). The temperature range is then from 0

o

C to +85

o

C.

Saturation -9 dBm

Adjacent
channel
rejection

19 dB Desired channel 3 dB above the sensitivity limit. 250 kHz channel

spacing

Alternate
channel
rejection

25 dB Desired channel 3 dB above the sensitivity limit. 250 kHz channel

spacing

See Figure 55 for plot of selectivity versus frequency offset

Blocking

±10 MHz offset

±20 MHz offset

±50 MHz offset

59

65

66

dB

dB

dB

Wanted signal 3 dB above sensitivity level.

Compliant with ETSI EN 300 440 class 2 receiver requirements.

C2510Fx / CC2511Fx

SWRS055D Page 14 of 243

Parameter Min Typ Max Unit Condition/Note

250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0

(MSK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth)

Receiver
sensitivity

-90 dBm See Table 9 for typical variation over operating conditions

Saturation -11 dBm

Adjacent
channel
rejection

21 dB Desired channel 3 dB above the sensitivity limit. 750 kHz channel

spacing

Alternate
channel
rejection

30 dB Desired channel 3 dB above the sensitivity limit. 750 kHz channel

spacing

See Figure 56 for plot of selectivity versus frequency offset

Blocking

±10 MHz offset

±20 MHz offset

±50 MHz offset

46

53

55

dB

dB

dB

Wanted signal 3 dB above sensitivity level.

Compliant with ETSI EN 300 440 class 2 receiver requirements.

500 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MDMCFG2.DEM_DCFILT_OFF=1 cannot
be used for data rates >100 kBaud)
(MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth)

Receiver
sensitivity

-82 dBm

Saturation -15 dBm

Adjacent
channel
rejection

12 dB Desired channel 3 dB above the sensitivity limit. 1 MHz channel spacing

Alternate
channel
rejection

23 dB Desired channel 3 dB above the sensitivity limit. 1 MHz channel spacing

See Figure 58 for plot of selectivity versus frequency offset

General

Spurious
emissions

Conducted measurement in a 50 Ω single ended load. Complies with EN
300 328, EN 300 440 class 2, FCC CFR47, Part 15 and ARIB STD-T-66.

25 MHz –
1 GHz

-57 dBm

Above 1 GHz

-47 dBm

Table 8: RF Receive Section

Supply Voltage, VDD = 2 V Supply Voltage, VDD = 3 V Supply Voltage, VDD = 3.6 V

Temperature [°C] -40 +25 +85 -40 +25 +85 -40 +25 +85

Sensitivity [dBm] -91.5 -90.3 -88.7 -90 -89.6 -88.1 -88.7 -89.3 -88.4

Table 9: Typical Variation in Sensitivity over Temperature and Supply Voltage @ 2.44 GHz and

250 kBaud Data Rate

C2510Fx / CC2511Fx

SWRS055D Page 15 of 243

7.3 RF Transmit Section

T

A

= 25 °C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the

CC2510EM reference designs ([1]).

Parameter Min Typ Max Unit Condition/Note

Differential load
impedance

80 + j74

Ω

Differential impedance as seen from the RF-port (RF_P and
RF_N) towards the antenna. Follow the CC2510EM
reference design [1] available from TI’s website.

Output power, highest
setting

+1 dBm Output power is programmable and is available across the

entire frequency band. See Figure 3 typical variation over
operating conditions (output power is 0 dBm)

Delivered to a 50 Ω single-ended load via the CC2510EM
reference design [1] RF matching network.

Output power, lowest
setting

-30 dBm Output power is programmable and is available across the
entire frequency band

Delivered to a 50 Ω single-ended load via the CC2510EM
reference design [1] RF matching network.

Occupied bandwidth
(99%)

-28

-27

-22

-21

dBc

dBc

dBc

dBc

2.4 kBaud, 38.2 kHz deviation, 2-FSK, 250 kHz channel
spacing

10 kBaud, 38.2 kHz deviation, 2-FSK, 250 kHz channel
spacing

250 kBaud, MSK, 750 kHz channel spacing

500 kBaud, MSK, 1 MHz channel spacing

Spurious emissions 0 dBm output power.

25 MHz – 1 GHz -36 dBm

47 - 74, 87.5 - 118,
174 - 230, and 470 ­862 MHz

-54 dBm

1800-1900 MHz -47 dBm Restricted band in Europe

At 2·RF and 3·RF -41 dBm Restricted bands in USA

Otherwise above
1 GHz

-30 dBm

Table 10: RF Transmit Section

Figure 3: Typical Variation in Output Power over Frequency and Temperature

(0 dBm output power)

Typical Variation in Output Power (0 dBm) over Frequency and

Temperature

2

2400 2408 2416 2424 2432 2440 2448 2456 2464 2472 2480

Frequency [MHz]

Output Power [dBm]

A

vg -40 °C

A

vg +85 °C

A

vg +25 °C

0

-2

-2

C2510Fx / CC2511Fx

SWRS055D Page 16 of 243

7.4 Crystal Oscillators

7.4.1

CC2510Fx

Crystal Oscillator

T

A

= 25 °C, VDD = 3.0 V if nothing else is stated.

Parameter Min Typ Max Unit Condition/Note

Crystal frequency 24 26 27 MHz Referred to as f

XOSC.

For operation in the range 24 – 26 MHz, please

refer to Table 4 for Operating Conditions.

Crystal frequency
accuracy
requirement

±40 ppm This is the total tolerance including a) initial tolerance, b) crystal

loading, c) aging, and d) temperature dependence.

The acceptable crystal tolerance depends on RF frequency and
channel spacing / bandwidth.

C0 1 5 7 pF Simulated over operating conditions

Load capacitance 10 13 20 pF Simulated over operating conditions

ESR 100

Ω

Simulated over operating conditions

Start-up time 250 µs f

XOSC

= 26 MHz

Note: A Ripple counter of 12 bit is included to ensure duty-cycle
requirements. Start-up time includes ripple counter delay until
SLEEP.XOSC_STB is asserted

Table 11:

CC2510Fx

Crystal Oscillator Parameters

7.4.2

CC2511Fx

Crystal Oscillator

T

A

= 25 °C, VDD = 3.0 V if nothing else is stated.

Parameter Min Typ Max Unit Condition/Note

Crystal frequency 48 MHz Referred to as f

XOSC

Crystal frequency
accuracy
requirement

±40 ppm This is the total tolerance including a) initial tolerance, b) crystal

loading, c) aging, and d) temperature dependence.

The acceptable crystal tolerance depends on RF frequency and
channel spacing / bandwidth.

C0

Fundamental 0.85 1 1.15 pF Simulated over operating conditions. Variation given by reference

crystal NX2520SA from NDK

3rd overtone 2 3 7 pF

Load capacitance 15 16 17 pF Simulated over operating conditions

ESR 60

Ω

Simulated over operating conditions

Start-up time

Note: A Ripple counter of 14 bit is included to ensure duty-cycle
requirements. Start-up time includes ripple counter delay until
SLEEP.XOSC_STB is asserted

Fundamental 650 µs

3rd overtone 3 ms Simulated value

Table 12:

CC2511Fx

Crystal Oscillator Parameters

C2510Fx / CC2511Fx

SWRS055D Page 17 of 243

7.5 32.768 kHz Crystal Oscillator

T

A

= 25 °C, VDD = 3.0V if nothing else is stated.

Parameter Min Typ Max Unit Condition/Note

Crystal frequency 32.768 kHz

C0 0.9 2.0 pF Simulated over operating conditions

Load capacitance 12 16 pF Simulated over operating conditions

ESR 40 130

kΩ

Simulated over operating conditions

Start-up time 400 ms Value is simulated

Table 13: 32.768 kHz Crystal Oscillator Parameters

C2510Fx / CC2511Fx

SWRS055D Page 18 of 243

7.6 Low Power RC Oscillator

T

A

= 25 °C, VDD = 3.0 V if nothing else is stated.

Parameter Min Typ Max Unit Condition/Note

Calibrated frequency2 32.0 34.7 36.0 kHz Calibrated low power RC oscillator frequency is

f

XOSC

/ 750

Frequency accuracy after
calibration

±1 %

Temperature coefficient +0.5

%/°C

Frequency drift when temperature changes after
calibration

Supply voltage coefficient +3 %/V Frequency drift when supply voltage changes after

calibration

Initial calibration time 2 ms When the low power RC oscillator is enabled,

calibration is continuously done in the background
as long as the high speed crystal oscillator is
running.

Table 14: Low Power RC Oscillator Parameters

7.7 High Speed RC Oscillator

T

A

= 25 °C, VDD = 3.0 V if nothing else is stated.

Parameter Min Typ Max Unit Condition/Note

Calibrated frequency2 12 13 13.5 MHz Calibrated HS RCOSC frequency is f

XOSC

/ 2

Uncalibrated frequency
accuracy

±15

%

Calibrated frequency
accuracy

±1

%

Start-up time 10 µs

Temperature coefficient -325

ppm/°C

Frequency drift when temperature changes after
calibration

Supply voltage coefficient 28 ppm/V Frequency drift when supply voltage changes after

calibration

Initial calibration time 65 µs The HS RCOSC will be calibrated once when the

high speed crystal oscillator is selected as system
clock source (CLKCON.OSC is set to 0), and also
when the system wakes up from PM{1-3}. See

13.1.5.1 for details).

Table 15: High Speed RC Oscillator Parameters

2

Min figures are given using f

XOSC

= 24 MHz. Typ figures are given using f

XOSC

= 26 MHz, and Max

figures are given using f

XOSC

= 27 MHz

C2510Fx / CC2511Fx

SWRS055D Page 19 of 243

7.8 Frequency Synthesizer Characteristics

T

A

= 25 °C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the

CC2510EM reference designs ([1]).

Parameter Min Typ Max Unit Condition/Note

Programmed frequency
resolution

367 397 412 Hz 24 - 27 MHz crystal.

Frequency resolution = f

XOSC

/ 216

Synthesizer frequency
tolerance

±40 ppm Given by crystal used. Required accuracy (including

temperature and aging) depends on frequency band and
channel bandwidth / spacing.

RF carrier phase noise -77 dBc/Hz @ 50 kHz offset from carrier

RF carrier phase noise -77 dBc/Hz @ 100 kHz offset from carrier

RF carrier phase noise -78 dBc/Hz @ 200 kHz offset from carrier

RF carrier phase noise -88 dBc/Hz @ 500 kHz offset from carrier

RF carrier phase noise -98 dBc/Hz @ 1 MHz offset from carrier

RF carrier phase noise -107 dBc/Hz @ 2 MHz offset from carrier

RF carrier phase noise -116 dBc/Hz @ 5 MHz offset from carrier

RF carrier phase noise -125 dBc/Hz @ 10 MHz offset from carrier

PLL turn-on / hop time3 85.1 88.4 95.8

µs

Time from leaving the IDLE state until arriving in the RX,
FSTXON, or TX state, when not performing calibration.
Crystal oscillator running.

PLL RX/TX settling time3 9.3 9.6 10.4

µs

Settling time for the 1·IF frequency step from RX to TX

PLL TX/RX settling time3 20.7 21.5 23.3

µs

Settling time for the 1·IF frequency step from TX to RX

PLL calibration time3 694 721 780.8

µs

Calibration can be initiated manually or automatically
before entering or after leaving RX/TX.

Table 16: Frequency Synthesizer Parameters

7.9 Analog Temperature Sensor

T

A

= 25 °C, VDD = 3.0V if nothing else stated. All measurement results are obtained using the

CC2510EM reference designs ([1]).

Parameter Min Typ Max Unit Condition/Note

Output voltage at -40 °C

0.654 V

Output voltage at 0 °C

0.750 V

Output voltage at +40 °C

0.848 V

Output voltage at +80 °C

0.946 V

Temperature coefficient 2.43

mV/°C Fitted from -20 °C to +80 °C

Error in calculated
temperature, calibrated

-2

*

0 2

*

°C From -20°C to +80°C when using 2.43 mV / °C, after 1-point

calibration at room temperature

*

The indicated minimum and maximum error with 1-point
calibration is based on measured values for typical process
parameters

Current consumption
increase when enabled

0.3 mA

Table 17: Analog Temperature Sensor Parameters

3

Min figures are given using f

XOSC

= 27 MHz. Typ figures are given using f

XOSC

= 26 MHz, and Max

figures are given using f

XOSC

= 24 MHz.

C2510Fx / CC2511Fx

SWRS055D Page 20 of 243

7.10 7-12 bit ADC

T

A

= 25 °C, VDD = 3.0V if nothing else stated. The numbers given here are based on tests performed

in accordance with IEEE Std 1241-2000 [7]. The ADC data are from

CC2430

characterization. As the

CC2510x/C2511Fx

uses the same ADC, the numbers listed in Table 18 should be good indicators of the

performance to be expected from

CC2510x

and

CC2511x

. Note that these numbers will apply for 24 MHz

operated systems (like

CC2510x

using a 24 MHz crystal or

CC2511x

using a 48 MHz crystal).

Performance will be slightly different for other crystal frequencies (e.g. 26 MHz and 27 MHz).

Parameter Min Typ Max Unit Condition/Note

Input voltage 0 AVDD V AVDD is voltage on AVDD pin

External reference voltage 0 AVDD V AVDD is voltage on AVDD pin

External reference voltage
differential

0 AVDD V AVDD is voltage on AVDD pin

Input resistance, signal 197

kΩ

Simulated using 4 MHz clock speed (see Section

13.10.2.7)

Full-Scale Signal4 2.97 V Peak-to-peak, defines 0 dBFS

ENOB4 5.7 bits 7-bits setting

Single ended input 7.5 9-bits setting

9.3 10-bits setting

10.8 12-bits setting

ENOB4 6.5 bits 7-bits setting

Differential input 8.3 9-bits setting

10.0 10-bits setting

11.5 12-bits setting

Useful Power Bandwidth 0-20 kHz 7-bits setting, both single and differential

THD4

-Single ended input -75.2 dB 12-bits setting, -6 dBFS

-Differential input -86.6 dB 12-bits setting, -6 dBFS

Signal To Non-Harmonic Ratio4

-Single ended input 70.2 dB 12-bits setting

-Differential input 79.3 dB 12-bits setting

Spurious Free Dynamic Range4

-Single ended input 78.8 dB 12-bits setting, -6 dBFS

-Differential input 88.9 dB 12-bits setting, -6 dBFS

CMRR, differential input <-84 dB 12- bit setting, 1 kHz Sine (0 dBFS), limited by ADC

resolution

Crosstalk, single ended input <-84 dB 12- bit setting, 1 kHz Sine (0 dBFS), limited by ADC

resolution

Offset -3 mV Mid. Scale

Gain error 0.68 %

DNL4 0.05 LSB 12-bits setting, mean

0.9 LSB 12-bits setting, max

INL4 4.6 LSB 12-bits setting, mean

13.3 LSB 12-bits setting, max

SINAD4 35.4 dB 7-bits setting

4

Measured with 300 Hz Sine input and VDD as reference.

C2510Fx / CC2511Fx

SWRS055D Page 21 of 243

Parameter Min Typ Max Unit Condition/Note

Single ended input 46.8 dB 9-bits setting

(-THD+N) 57.5 dB 10-bits setting

66.6 dB 12-bits setting

SINAD4 40.7 dB 7-bits setting

Differential input 51.6 dB 9-bits setting

(-THD+N) 61.8 dB 10-bits setting

70.8 dB 12-bits setting

Conversion time 20

µs

7-bits setting

36

µs

9-bits setting

68

µs

10-bits setting

132

µs

12-bits setting

Current consumption 1.2 mA

Table 18: 7-12 bit ADC Characteristics

7.11 Control AC Characteristics

T

A

= 25 °C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the

CC2510EM reference designs ([1]).

Parameter Min Typ Max Unit Condition/Note

System clock,
f

SYSCLK

t

SYSCLK

= 1/ f

SYSCLK

CC2510Fx

0.1875 26 27 MHz High speed crystal oscillator used as source (HS XOSC)

MHz Calibrated HS RCOSC used as source. 0.1875 13 13.5

HS

XOSC

HS
RCOSC

Min: f

XOSC

= 24 MHz, CLKCON.CLKSPD =

Typ: f

XOSC

= 26 MHz, CLKCON.CLKSPD =

Max: f

XOSC

= 27 MHz, CLKCON.CLKSPD =

111
000
000

111
001
001

0.1875 24

24

MHz

CC2511Fx

High speed crystal oscillator used as source.

0.1875 12 12 HS RCOSC used as source.

Min: f

XOSC

= 48 MHz, CLKCON.CLKSPD = 111

Typ and Max: f

XOSC

= 48 MHz, CLKCON.CLKSPD = 000

RESET_N low
width

250 ns See item 1, Figure 4. This is the shortest pulse that is

guaranteed to be recognized as a reset pin request.

Note: Shorter pulses may be recognized but will not lead to
complete reset of all modules within the chip.

Interrupt pulse
width

t

SYSCLK

See item 2, Figure 4. This is the shortest pulse that is

guaranteed to be recognized as an interrupt request. In PM2/3
the internal synchronizers are bypassed so this requirement
does not apply in PM2/3.

Table 19: Control Inputs AC Characteristics

C2510Fx / CC2511Fx

SWRS055D Page 22 of 243

Figure 4: Control Inputs AC Characteristics

7.12 SPI AC Characteristics

T

A

= 25 °C, VDD = 3.0V if nothing else stated. All measurement results are obtained using the

CC2510EM reference designs ([1]).

Parameter Min Typ Max Unit Condition/Note

SCK period See

Section

13.14.3

ns Master. See item 1, Figure 5

SCK duty cycle 50 % Master.

SSN low to SCK 2·t

SYSCLK

See item 5, Figure 5

SCK to SSN high 30 ns See item 6, Figure 5

MISO setup 10 ns Master. See item 2, Figure 5

MISO hold 10 ns Master. See item 3, Figure 5

SCK to MOSI 25 ns Master. See item 4, Figure 5, load = 10 pF

SCK period 100 ns Slave. See item 1, Figure 5

SCK duty cycle 50 % Slave.

MOSI setup 10 ns Slave. See item 2, Figure 5

MOSI hold 10 ns Slave. See item 3, Figure 5

SCK to MISO 25 ns Slave. See item 4, Figure 5, load = 10 pF

Table 20: SPI AC Characteristics

C2510Fx / CC2511Fx

SWRS055D Page 23 of 243

Figure 5: SPI AC Characteristics

7.13 Debug Interface AC Characteristics

T

A

= 25 °C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the

CC2510EM reference designs ([1]).

Parameter Min Typ Max Unit Condition/Note

Debug clock
period

125 ns See item 1, Figure 6

Note: CLKCON.CLKSPD must be 000 or 001 when using
the debug interface

Debug data setup 5 ns See item 2, Figure 6

Debug data hold 5 ns See item 3, Figure 6

Clock to data
delay

10 ns See item 4, Figure 6, load = 10 pF

RESET_N inactive
after P2_2 rising

10 ns See item , Figure 6

Table 21: Debug Interface AC Characteristics

C2510Fx / CC2511Fx

SWRS055D Page 24 of 243

Figure 6: Debug Interface AC Characteristics

7.14 Port Outputs AC Characteristics

T

A

= 25 °C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the

CC2510EM reference designs ([1]).

Parameter Min Typ Max Unit Condition/Note

P0_[0:7], P1_[2:7],
P2_[0:4] Port output
rise time
(PICTL.PADSC=0 /
PICTL.PADSC=1)

3.15 /

1.34

ns Load = 10 pF

Timing is with respect to 10% VDD and 90% VDD levels.

Values are estimated

P0_[0:7], P1_[2:7],
P2_[0:4] Port output
fall time
(PICTL.PADSC=0 /
PICTL.PADSC=1)

3.2 / 1.44 ns Load = 10 pF

Timing is with respect to 90% VDD and 10% VDD.

Values are estimated

Table 22: Port Outputs AC Characteristics

7.15 Timer Inputs AC Characteristics

T

A

= 25 °C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the

CC2510EM reference designs ([1]).

Parameter Min Typ Max Unit Condition/Note

Input capture
pulse width

t

SYSCLK

Synchronizers determine the shortest input pulse that can be

recognized. The synchronizers operate from the current
system clock rate (see Table 19)

Table 23: Timer Inputs AC Characteristics

7.16 DC Characteristics

The DC Characteristics of

CC2510Fx/CC2511Fx

are listed in Table 24 below.

T

A

= 25 °C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the

CC2510EM reference designs ([1]).

Digital Inputs/Outputs Min Typ Max Unit Condition

C2510Fx / CC2511Fx

SWRS055D Page 25 of 243

Logic "0" input voltage 30 % Of VDD supply (2.0 – 3.6 V)

Logic "1" input voltage 70 % Of VDD supply (2.0 – 3.6 V)

Logic "0" input current per pin NA 12 nA Input equals 0 V

Logic "1" input current per pin NA 12 nA Input equals VDD

Total logic “0” input current all pins 70 nA

Total logic “1” input current all pins 70 nA

I/O pin pull-up and pull-down resistor 20

kΩ

Table 24: DC Characteristics

C2510Fx / CC2511Fx

SWRS055D Page 26 of 243

8 Pin and I/O Port Configuration

The

CC2510Fx

pin-out is shown in Figure 7 and Table 25. See Section 13.4 for details on the I/O

configuration.

AGND
Exposed die
attached pad

DVDD

36 35 34 33 32 31 30 29 28

9

8

7

6

5

4

3

2

1

27

26

25

24

23

22

21

20

19

10 11 12 13 14 15 16 17 18

P1_1

P1_0

P0_0

P0_1

P0_2

P0_3

P0_4

AVDD

XOSC_Q2

AVDD

RF_N

AVDD

AVDD

RBIAS

XOSC_Q1

RF_P

P1_2

Figure 7:

CC2510Fx

Pinout Top View

Note: The exposed die attach pad must be connected to a solid ground plane as this is the ground
connection for the chip.

C2510Fx / CC2511Fx

SWRS055D Page 27 of 243

Pin Pin Name Pin Type Description

AGND Ground The exposed die attach pad must be connected to a solid ground

plane

1 P1_2 D I/O Port 1.2

2 DVDD Power (Digital) 2.0 V - 3.6 V digital power supply for digital I/O

3 P1_1 D I/O Port 1.1

4 P1_0 D I/O Port 1.0

5 P0_0 D I/O Port 0.0

6 P0_1 D I/O Port 0.1

7 P0_2 D I/O Port 0.2

8 P0_3 D I/O Port 0.3

9 P0_4 D I/O Port 0.4

10 DVDD Power (Digital) 2.0 V - 3.6 V digital power supply for digital I/O

11 P0_5 D I/O Port 0.5

12 P0_6 D I/O Port 0.6

13 P0_7 D I/O Port 0.7

14 P2_0 D I/O Port 2.0

15 P2_1 D I/O Port 2.1

16 P2_2 D I/O Port 2.2

17 P2_3/XOSC32_Q1 D I/O Port 2.3/32.768 kHz crystal oscillator pin 1

18 P2_4/XOSC32_Q2 D I/O Port 2.4/32.768 kHz crystal oscillator pin 2

19 AVDD Power (Analog) 2.0 V - 3.6 V analog power supply connection

20 XOSC_Q2 Analog I/O 26 MHz crystal oscillator pin 2

21 XOSC_Q1 Analog I/O 26 MHz crystal oscillator pin 1, or external clock input

22 AVDD Power (Analog) 2.0 V - 3.6 V analog power supply connection

23 RF_P RF I/O Positive RF input signal to LNA in receive mode

Positive RF output signal from PA in transmit mode

24 RF_N RF I/O Negative RF input signal to LNA in receive mode

Negative RF output signal from PA in transmit mode

25 AVDD Power (Analog) 2.0 V – 3.6 V analog power supply connection

26 AVDD Power (Analog) 2.0 V - 3.6 V analog power supply connection

27 RBIAS Analog I/O External precision bias resistor for reference current

28 GUARD Power (Digital) Power supply connection for digital noise isolation

29 AVDD_DREG Power (Digital) 2.0 V - 3.6 V digital power supply for digital core voltage regulator

30 DCOUPL Power decoupling 1.8 V digital power supply decoupling

31 RESET_N DI Reset, active low

32 P1_7 D I/O Port 1.7

33 P1_6 D I/O Port 1.6

34 P1_5 D I/O Port 1.5

35 P1_4 D I/O Port 1.4

36 P1_3 D I/O Port 1.3

Table 25:

CC2510Fx

Pin-out Overview

C2510Fx / CC2511Fx

SWRS055D Page 28 of 243

The

CC2511Fx

pin-out is shown in Figure 8 and Table 26. See Section 13.4 for details on the I/O

configuration.

AGND

Exposed die

attached pad

DVDD

36 35 34 33 32 31 30 29 28

9

8

7

6

5

4

3

2

1

27

26

25

24

23

22

21

20

19

10 11 12 13 14 15 16 17 18

P1_1

P1_0

P0_0

P0_1

P0_2

P0_3

P0_4

AVDD

XOSC_Q2

AVDD

RF_N

AVDD

AVDD

R_BIAS

XOSC_Q1

RF_P

P1_2

Figure 8:

CC2511Fx

Pin-out Top View

Note: The exposed die attach pad must be connected to a solid ground plane as this is the ground
connection for the chip.

C2510Fx / CC2511Fx

SWRS055D Page 29 of 243

Pin Pin Name Pin Type Description

AGND Ground The exposed die attach pad must be connected to a solid ground

plane

1 P1_2 D I/O Port 1.2

2 DVDD Power (Digital) 2.0 V - 3.6 V digital power supply for digital I/O

3 P1_1 D I/O Port 1.1

4 P1_0 D I/O Port 1.0

5 P0_0 D I/O Port 0.0

6 P0_1 D I/O Port 0.1

7 P0_2 D I/O Port 0.2

8 P0_3 D I/O Port 0.3

9 P0_4 D I/O Port 0.4

10 DP USB I/O USB Differential Data Bus Plus

11 DM USB I/O USB Differential Data Bus Minus

12 DVDD Power (Digital) 2.0 V - 3.6 V digital power supply for digital I/O

13 P0_5 D I/O Port 0.5

14 P2_0 D I/O Port 2.0

15 P2_1 D I/O Port 2.1

16 P2_2 D I/O Port 2.2

17 P2_3/XOSC32_Q1 D I/O Port 2.3/32.768 kHz crystal oscillator pin 1

18 P2_4/XOSC32_Q2 D I/O Port 2.4/32.768 kHz crystal oscillator pin 2

19 AVDD Power (Analog) 2.0 V - 3.6 V analog power supply connection

20 XOSC_Q2 Analog I/O 48 MHz crystal oscillator pin 2

21 XOSC_Q1 Analog I/O 48 MHz crystal oscillator pin 1, or external clock input

22 AVDD Power (Analog) 2.0 V - 3.6 V analog power supply connection

23 RF_P RF I/O Positive RF input signal to LNA in receive mode

Positive RF output signal from PA in transmit mode

24 RF_N RF I/O Negative RF input signal to LNA in receive mode

Negative RF output signal from PA in transmit mode

25 AVDD Power (Analog) 2.0 V - 3.6 V analog power supply connection

26 AVDD Power (Analog) 2.0 V - 3.6 V analog power supply connection

27 RBIAS Analog I/O External precision bias resistor for reference current

28 GUARD Power (Digital) Power supply connection for digital noise isolation

29 AVDD_DREG Power (Digital) 2.0 V - 3.6 V digital power supply for digital core voltage regulator

30 DCOUPL Power

decoupling

1.8 V digital power supply decoupling

31 RESET_N DI Reset, active low

32 P1_7 D I/O Port 1.7

33 P1_6 D I/O Port 1.6

34 P1_5 D I/O Port 1.5

35 P1_4 D I/O Port 1.4

36 P1_3 D I/O Port 1.3

Table 26:

CC2511Fx

Pin-out Overview

C2510Fx / CC2511Fx

SWRS055D Page 30 of 243

9 Circuit Description

SFR bus SFR bus

MEMORY

ARBITRATOR

8051 CPU

CORE

DMA

32 KB

FLASH

4 KB

SRAM

FLASH CTRL

DEBUG

INTERFACE

RESET

RESET_N

P2_4

P2_3

P2_2

P2_1

P2_0

P1_4

P1_3

P1_2

P1_1

P1_0

P1_7

P1_6

P1_5

P0_4

P0_3

P0_2

P0_1

P0_0

P0_5

32.768 kHz

CRYSTAL OSC

HIGH SPEED

CRYSTAL OSC

(24 – 27 MHz)

HIGH SPEED

RC-OSC

LOW PWR

RC-OSC

CLOCK MUX &

CALIBRATION

RAM

I/O CONTROLLER

USART 0

USART 1

TIMER 1 (16-bit) + Module

TIMER 3 (8-bit)

TIMER 2 (8-bit MAC Timer)

TIMER 4 (8-bit)

AES

ENCRYPTION &

DECRYPTION

WATCHDOG TIMER

RADIO DATA INTERFACE

IRQ

CTRL

FLASH

UNIFIED

FRAME CONTROL

AGC

RF_P RF_N

SYNTH

MODULATORDEMODULATOR

POWER ON RESET

RADIO / I2S REGISTERS

POWER MGT. CONTROLLER

SLEEP TIMER

CODE

XDATA

DATA

SFR

XOSC_Q2

XOSC_Q1

RECEIVE

CHAIN

TRANSMIT

CHAIN

ADC

AUDIO / DC

DIGITAL

ANALOG

MIXED

VDD (2.0 - 3.6 V)

DCOUPL

ON-CHIP VOLTAGE

REGULATOR

FREQUENCY

SYNTHESIZER

USB

USB BUS

USB PHY

DM

DP

1 KB

FIFO SRAM

P0_7

P0_6

I2S

Figure 9:

C C2510Fx/CC2511Fx

Block Diagram

A block diagram of

CC2510Fx/CC2511Fx

is
shown in Figure 9. The modules can be
divided into one out of three categories: CPU­related modules, radio-related modules, and

modules related to power, test, and clock
distribution. In the following subsections, a
short description of each module that appears
in Figure 9.