TEXAS INSTRUMENTS CC2500 Technical data

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CC2500

Low-Cost Low-Power 2.4 GHz RF Transceiver

Applications

• 2400-2483.5 MHz ISM/SRD band systems

• Consumer electronics

• Wireless game controllers

Product Description

The

CC2500

designed for very low-power wireless applications. The circuit is intended for the 2400-

2483.5 MHz ISM (Industrial, Scientific and Medical) and SRD (Short Range Device) frequency band.

The RF transceiver is integrated with a highly configurable baseband modem. The modem supports various modulation formats and has a configurable data rate up to 500 kBaud.

is a low-cost 2.4 GHz transceiver

• Wireless audio

• Wireless keyboard and mouse

• RF enabled remote controls

controlled via an SPI interface. In a typical system, the a microcontroller and a few additional passive components.

CC2500

2019181716

will be used together with

CC2500

for packet handling, data buffering, burst transmissions, clear channel assessment, link quality indication, and wake-on-radio.

The main operating parameters and the 64byte transmit/receive FIFOs of

provides extensive hardware support

CC2500

can be

Key Features RF Performance

• High sensitivity (–104 dBm at 2.4 kBaud,

1% packet error rate)

• Low current consumption (13.3 mA in RX,

250 kBaud, input well above sensitivity limit)

• Programmable output power up to +1 dBm

• Excellent receiver selectivity and blocking

performance

• Programmable data rate from 1.2 to 500

kBaud

• Frequency range: 2400 – 2483.5 MHz

Analog Features

• OOK, 2-FSK, GFSK, and MSK supported

• Suitable for frequency hopping and multi-

channel systems due to a fast settling

678910

frequency synthesizer with 90 us settling time

• Automatic Frequency Compensation

(AFC) can be used to align the frequency synthesizer to the received centre frequency

• Integrated analog temperature sensor

Digital Features

• Flexible support for packet oriented

systems: On-chip support for sync word detection, address check, flexible packet length, and automatic CRC handling

• Efficient SPI interface: All registers can be

programmed with one “burst” transfer

• Digital RSSI output

• Programmable channel filter bandwidth

• Programmable Carrier Sense (CS)

indicator

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CC2500

• Programmable Preamble Quality Indicator

(PQI) for improved protection against false sync word detection in random noise

• Support for automatic Clear Channel

Assessment (CCA) before transmitting (for listen-before-talk systems)

• Support for per-package Link Quality

Indication (LQI)

• Optional automatic whitening and de-

whitening of data

Low-Power Features

• 400 nA SLEEP mode current consumption

• Fast startup time: 240 us from SLEEP to

RX or TX mode (measured on EM design)

• Wake-on-radio functionality for automatic

low-power RX polling

• Separate 64-byte RX and TX data FIFOs

(enables burst mode data transmission)

General

• Few external components: Complete on-

chip frequency synthesizer, no external filters or RF switch needed

• Green package: RoHS compliant and no

antimony or bromine

• Small size (QLP 4x4 mm package, 20

pins)

• Suited for systems compliant with EN 300

328 and EN 300 440 class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STDT66 (Japan)

• Support for asynchronous and

synchronous serial receive/transmit mode for backwards compatibility with existing radio communication protocols

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CC2500

Abbreviations

Abbreviations used in this data sheet are described below.

ACP Adjacent Channel Power MSB Most Significant Bit

ADC Analog to Digital Converter MSK Minimum Shift Keying

AFC Automatic Frequency Offset Compensation NA Not Applicable

AGC Automatic Gain Control NRZ Non Return to Zero (Coding)

AMR Automatic Meter Reading OOK On Off Keying

ARIB Association of Radio Industries and Businesses PA Power Amplifier

BER Bit Error Rate PCB Printed Circuit Board

BT Bandwidth-Time product PD Power Down

CCA Clear Channel Assessment PER Packet Error Rate

CFR Code of Federal Regulations PLL Phase Locked Loop

CRC Cyclic Redundancy Check POR Power-on Reset

CS Carrier Sense PQI Preamble Quality Indicator

CW Continuous Wave (Unmodulated Carrier) PQT Preamble Quality Threshold

DC Direct Current RCOSC RC Oscillator

DVGA Digital Variable Gain Amplifier QPSK Quadrature Phase Shift Keying

ESR Equivalent Series Resistance QLP Quad Leadless Package

FCC Federal Communications Commission RC Resistor-Capacitor

FEC Forward Error Correction RF Radio Frequency

FIFO First-In-First-Out RSSI Received Signal Strength Indicator

FHSS Frequency Hopping Spread Spectrum RX Receive, Receive Mode

2-FSK Frequency Shift Keying SMD Surface Mount Device

GFSK Gaussian shaped Frequency Shift Keying SNR Signal to Noise Ratio

IF Intermediate Frequency SPI Serial Peripheral Interface

I/Q In-Phase/Quadrature SRD Short Range Device

ISM Industrial, Scientific and Medical T/R Transmit/Receive

LBT Listen Before Transmit TX Transmit, Transmit Mode

LC Inductor-Capacitor VCO Voltage Controlled Oscillator

LNA Low Noise Amplifier WLAN Wireless Local Area Networks

LO Local Oscillator WOR Wake on Radio, Low power polling

LQI Link Quality Indicator XOSC Crystal Oscillator

LSB Least Significant Bit XTAL Crystal

MCU Microcontroller Unit

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CC2500

APPLICATIONS...........................................................................................................................................1

PRODUCT DESCRIPTION.........................................................................................................................1

KEY FEATURES..........................................................................................................................................1

RF PERFORMANCE ...........................................................................................................................................1

ANALOG FEATURES..........................................................................................................................................1

DIGITAL FEATURES ..........................................................................................................................................1

LOW-POWER FEATURES ...................................................................................................................................2

GENERAL..........................................................................................................................................................2

ABBREVIATIONS........................................................................................................................................3

TABLE OF CONTENTS..............................................................................................................................4

1 ABSOLUTE MAXIMUM RATINGS...........................................................................................................7

2 OPERATING CONDITIONS......................................................................................................................7

3 GENERAL CHARACTERISTICS ...............................................................................................................7

4 ELECTRICAL SPECIFICATIONS...............................................................................................................8

4.1 CURRENT CONSUMPTION .....................................................................................................................8

4.2 RF RECEIVE SECTION.........................................................................................................................10

4.3 RF TRANSMIT SECTION ......................................................................................................................12

4.4 CRYSTAL OSCILLATOR.......................................................................................................................13

4.5 LOW POWER RC OSCILLATOR............................................................................................................13

4.6 FREQUENCY SYNTHESIZER CHARACTERISTICS...................................................................................14

4.7 ANALOG TEMPERATURE SENSOR .......................................................................................................15

4.8 DC CHARACTERISTICS .......................................................................................................................15

4.9 POWER-ON RESET..............................................................................................................................15

5 PIN CONFIGURATION ..........................................................................................................................16

6 CIRCUIT DESCRIPTION........................................................................................................................18

7 APPLICATION CIRCUIT........................................................................................................................18

8 CONFIGURATION OVERVIEW ..............................................................................................................20

9 CONFIGURATION SOFTWARE ..............................................................................................................21

10 4-WIRE SERIAL CONFIGURATION AND DATA INTERFACE ...................................................................22

10.1 CHIP STATUS BYTE ............................................................................................................................23

10.2 REGISTER ACCESS ..............................................................................................................................24

10.3 SPI READ ...........................................................................................................................................24

10.4 COMMAND STROBES ..........................................................................................................................25

10.5 FIFO ACCESS .....................................................................................................................................25

10.6 PATABLE ACCESS .............................................................................................................................25

11 MICROCONTROLLER INTERFACE AND PIN CONFIGURATION...............................................................26

11.1 CONFIGURATION INTERFACE ..............................................................................................................26

11.2 GENERAL CONTROL AND STATUS PINS ..............................................................................................26

11.3 OPTIONAL RADIO CONTROL FEATURE ...............................................................................................27

12 DATA RATE PROGRAMMING...............................................................................................................27

13 RECEIVER CHANNEL FILTER BANDWIDTH..........................................................................................28

14 DEMODULATOR, SYMBOL SYNCHRONIZER AND DATA DECISION.......................................................28

14.1 FREQUENCY OFFSET COMPENSATION.................................................................................................28

14.2 BIT SYNCHRONIZATION......................................................................................................................28

14.3 BYTE SYNCHRONIZATION...................................................................................................................29

15 PACKET HANDLING HARDWARE SUPPORT .........................................................................................29

15.1 DATA WHITENING ..............................................................................................................................30

15.2 PACKET FORMAT................................................................................................................................30

15.3 PACKET FILTERING IN RECEIVE MODE...............................................................................................32

15.4 CRC CHECK .......................................................................................................................................32

15.5 PACKET HANDLING IN TRANSMIT MODE............................................................................................33

15.6 PACKET HANDLING IN RECEIVE MODE ..............................................................................................33

15.7 PACKET HANDLING IN FIRMWARE......................................................................................................34

16 MODULATION FORMATS.....................................................................................................................34

16.1 FREQUENCY SHIFT KEYING................................................................................................................34

16.2 MINIMUM SHIFT KEYING....................................................................................................................34

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16.3 AMPLITUDE MODULATION .................................................................................................................35

17 RECEIVED SIGNAL QUALIFIERS AND LINK QUALITY INFORMATION...................................................35

17.1 SYNC WORD QUALIFIER.....................................................................................................................35

17.2 PREAMBLE QUALITY THRESHOLD (PQT)...........................................................................................35

17.3 RSSI...................................................................................................................................................35

17.4 CARRIER SENSE (CS)..........................................................................................................................36

17.5 CLEAR CHANNEL ASSESSMENT (CCA) ..............................................................................................38

17.6 LINK QUALITY INDICATOR (LQI).......................................................................................................38

18 FORWARD ERROR CORRECTION WITH INTERLEAVING........................................................................38

18.1 FORWARD ERROR CORRECTION (FEC)...............................................................................................38

18.2 INTERLEAVING ...................................................................................................................................39

19 RADIO CONTROL................................................................................................................................40

19.1 POWER-ON START-UP SEQUENCE ......................................................................................................40

19.2 CRYSTAL CONTROL............................................................................................................................41

19.3 VOLTAGE REGULATOR CONTROL.......................................................................................................41

19.4 ACTIVE MODES ..................................................................................................................................42

19.5 WAKE ON RADIO (WOR)...................................................................................................................42

19.6 TIMING ...............................................................................................................................................43

19.7 RX TERMINATION TIMER ...................................................................................................................44

20 DATA FIFO........................................................................................................................................44

21 FREQUENCY PROGRAMMING ..............................................................................................................45

22 VCO...................................................................................................................................................46

22.1 VCO AND PLL SELF-CALIBRATION ...................................................................................................46

23 VOLTAGE REGULATORS .....................................................................................................................47

24 OUTPUT POWER PROGRAMMING........................................................................................................47

25 SELECTIVITY ......................................................................................................................................49

26 CRYSTAL OSCILLATOR.......................................................................................................................51

26.1 REFERENCE SIGNAL ...........................................................................................................................51

27 EXTERNAL RF MATCH .......................................................................................................................51

28 PCB LAYOUT RECOMMENDATIONS....................................................................................................52

29 GENERAL PURPOSE / TEST OUTPUT CONTROL PINS ...........................................................................53

30 ASYNCHRONOUS AND SYNCHRONOUS SERIAL OPERATION................................................................55

30.1 ASYNCHRONOUS OPERATION .............................................................................................................55

30.2 SYNCHRONOUS SERIAL OPERATION ...................................................................................................55

31 SYSTEM CONSIDERATIONS AND GUIDELINES .....................................................................................55

31.1 SRD REGULATIONS............................................................................................................................55

31.2 FREQUENCY HOPPING AND MULTI-CHANNEL SYSTEMS.....................................................................56

31.3 WIDEBAND MODULATION NO T USING SPREAD SPECTRUM ................................................................56

31.4 DATA BURST TRANSMISSIONS............................................................................................................56

31.5 CONTINUOUS TRANSMISSIONS ...........................................................................................................56

31.6 CRYSTAL DRIFT COMPENSATION .......................................................................................................57

31.7 SPECTRUM EFFICIENT MODULATION..................................................................................................57

31.8 LOW COST SYSTEMS ..........................................................................................................................57

31.9 BATTERY OPERATED SYSTEMS ..........................................................................................................57

31.10 INCREASING OUTPUT POWER .........................................................................................................57

32 CONFIGURATION REGISTERS..............................................................................................................58

32.1 CONFIGURATION REGISTER DETAILS – REGISTERS WITH PRESERVED VALUES IN SLEEP STATE ......62

32.2 CONFIGURATION REGISTER DETAILS – REGISTERS THA T LOSE PROGRAMMING IN SLEEP STATE.....81

32.3 STATUS REGISTER DETAILS................................................................................................................82

33 PACKAGE DESCRIPTION (QLP 20)......................................................................................................86

33.1 RECOMMENDED PCB LAYOUT FOR PACKAGE (QLP 20)....................................................................87

33.2 SOLDERING INFORMATION .................................................................................................................87

33.3 TRAY SPECIFICATION .........................................................................................................................87

33.4 CARRIER TAPE AND REEL SPECIFICATION ..........................................................................................88

34 ORDERING INFORMATION...................................................................................................................88

35 REFERENCES....................................................................................................................................... 88

36 GENERAL INFORMATION ....................................................................................................................89

36.1 DOCUMENT HISTORY .........................................................................................................................89

36.2 PRODUCT STATUS DEFINITIONS .........................................................................................................90

CC2500

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37 ADDRESS INFORMATION.....................................................................................................................91

38 TI WORLDWIDE TECHNICAL SUPPORT ...............................................................................................91

CC2500

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CC2500

1 Absolute Maximum Ratings

Under no circumstances must the absolute maximum ratings given in Table 1 be violated. Stress exceeding one or more of the limiting values may cause permanent damage to the device.

Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage.

Parameter Min Max Unit Condition

Supply voltage –0.3 3.9 V All supply pins must have the same voltage

Voltage on any digital pin –0.3 VDD+0.3,

Voltage on the pins RF_P, RF_N and DCOUPL

Voltage ramp-up rate 120 kV/µs

Input RF level +10 dBm

Storage temperature range –50 150

Solder reflow temperature 260

ESD <500 V According to JEDEC STD 22, method A114,

–0.3 2.0 V

max 3.9

°C

According to IPC/JEDEC J-STD-020D

°C

Human Body Model

Table 1: Absolute Maximum Rati ngs

2 Operating Conditions

The

CC2500

Parameter Min Max Unit Condition

Operating temperature –40 85

Operating supply voltage 1.8 3.6 V All supply pins must have the same voltage

operating conditions are listed in Table 2 below.

°C

Table 2: Operating Conditi ons

3 General Characteristics

Parameter Min Typ Max Unit Condition/Note

Frequency range 2400 2483.5 MHz There will be spurious signals at n/2·crystal oscillator

Data rate 1.2

1.2

500

250

500

kBaud

frequency (n is an integer number). RF frequencies at n/2·crystal oscillator frequency should therefore be avoided (e.g. 2405, 2418, 2431, 2444, 2457, 2470 and 2483 MHz when using a 26 MHz crystal).

2-FSK

GFSK and OOK

(Shaped) MSK (also known as differential offset QPSK)

Optional Manchester encoding (the data rate in kbps will be half the baud rate).

Table 3: General Characteristics

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CC2500

4 Electrical Specifications

4.1 Current Consumption

Tc = 25°C, VDD = 3.0 V if nothing else stated. All measurement results obtained using the CC2500EM reference design ([4]).

Parameter Min Typ Max Unit Condition

Current consumption in power down modes

Current consumption

Current consumption, RX states

400 nA Voltage regulator to digital part off, register values retained

900 nA Voltage regulator to digital part off, register values retained, low-

160

8.1

1.4

1.5 mA Only voltage regulator to digital part and crystal oscillator running

7.4 mA Only the frequency synthesizer is running (FSTXON state). This

17.0 mA Receive mode, 2.4 kBaud, input at sensitivity limit,

14.5 mA Receive mode, 2.4 kBaud, input well above sensitivity limit,

17.3 mA Receive mode, 10 kBaud, input at sensitivity limit,

14.9 mA Receive mode, 10 kBaud, input well above sensitivity limit,

18.8 mA Receive mode, 250 kBaud, input at sensitivity limit,

15.7 mA Receive mode, 250 kBaud, input well above sensitivity limit,

16.6 mA Receive mode, 250 kBaud current optimized, input at sensitivity

13.3 mA Receive mode, 250 kBaud current optimized, input well above

19.6 mA Receive mode, 500 kBaud, input at sensitivity limit,

17.0 mA Receive mode, 500 kBaud, input well above sensitivity limit,

(SLEEP state). All GDO pins programmed to 0x2F (HW to 0)

power RC oscillator running (SLEEP state with WOR enabled)

Voltage regulator to digital part off, register values retained,

µA

XOSC running (SLEEP state with MCSM0.OSC_FORCE_ON set)

Voltage regulator to digital part on, all other modules in power

µA

down (XOFF state)

Automatic RX polling once each second, using low-power RC

µA

oscillator, with 460 kHz filter bandwidth and 250 kBaud data rate, PLL calibration every 4 channel below carrier sense level (MCSM2.RX_TIME_RSSI=1).

Same as above, but with signal in channel above carrier sense

µA

level, 1.95 ms RX timeout, and no preamble/sync word found.

Automatic RX polling every 15th second, using low-power RC

µA

oscillator, with 460 kHz filter bandwidth and 250 kBaud data rate, PLL calibration every 4 channel below carrier sense level (MCSM2.RX_TIME_RSSI=1).

Same as above, but with signal in channel above carrier sense

µA

level, 29.3 ms RX timeout, and no preamble/sync word found.

(IDLE state)

currents consumption is also representative for the other intermediate states when going from IDLE to RX or TX, including the calibration state.

MDMCFG2.DEM_DCFILT_OFF=0

limit, MDMCFG2.DEM_DCFILT_OFF=1

sensitivity limit, MDMCFG2.DEM_DCFILT_OFF=1

MDMCFG2.DEM_DCFILT_OFF=0

wakeup. Average current with signal in

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CC2500

Current consumption, TX states

11.1 mA Transmit mode, –12 dBm output power

15.0 mA Transmit mode, -6 dBm output power

21.2 mA Transmit mode, 0 dBm output power

21.5 mA Transmit mode, +1 dBm output power

Table 4: Current Consumption

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CC2500

4.2 RF Receive Section

Tc = 25°C, VDD = 3.0 V if nothing else stated. All measurement results obtained using the CC2500EM reference design ([4]).

Parameter Min Typ Max Unit Condition/Note

Digital channel filter bandwidth

2.4 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (2-FSK, 1% packet error rate, 20 bytes packet length, 203 kHz digital channel filter bandwidth)

Receiver sensitivity –104 dBm The RX current consumption can be reduced by

Saturation –13 dBm

Adjacent channel rejection

Alternate channel rejection

See Figure 22 for plot of selectivity versus frequency

Blocking

±10 MHz offset

±20 MHz offset

±50 MHz offset 10 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0

(2-FSK, 1% packet error rate, 20 bytes packet length, 232 kHz digital channel filter bandwidth)

Receiver sensitivity –99 dBm The RX current consumption can be reduced by

Saturation –9 dBm

Adjacent channel rejection

Alternate channel rejection

See Figure 23 for plot of selectivity versus frequency

Blocking

±10 MHz offset

±20 MHz offset

±50 MHz offset

58 812 kHz User programmable. The bandwidth limits are

23 dB Desired channel 3 dB above the sensitivity limit. 250

31 dB Desired channel 3 dB above the sensitivity limit. 250

18 dB Desired channel 3 dB above the sensitivity limit. 250

25 dB Desired channel 3 dB above the sensitivity limit. 250

proportional to crystal frequency (given values assume a 26.0 MHz crystal).

approximately 1.7 mA by setting MDMCFG2.DEM_DCFILT_OFF= is then -102 dBm and the temperature range is from 0

to +85

The sensitivity can be improved to typically –106 dBm with MDMCFG2.DEM_DCFILT_OFF= registers TEST2 and TEST1 (see page 82). The temperature range is then from 0

kHz channel spacing

offset

Wanted signal 3 dB above sensitivity level.

Compliant with ETSI EN 300 440 class 2 receiver

dBm

requirements.

dBm

approximately 1.7 mA by setting MDMCFG2.DEM_DCFILT_OFF= is then -97 dBm

The sensitivity can be improved to typically –101 dBm with MDMCFG2.DEM_DCFILT_OFF= registers TEST2 and TEST1 (see page 82). The temperature range is then from 0

kHz channel spacing

offset

Wanted signal 3 dB above sensitivity level.

Compliant with ETSI EN 300 440 class 2 receiver

requirements.

1. The typical sensitivity

0 by programming

C to +85oC.

1. The typical sensitivity

0 by programming

C to +85oC.

SWRS040B Page 10 of 92

CC2500

Parameter Min Typ Max Unit Condition/Note 250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0

(MSK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth)

Receiver sensitivity –89 dBm

Saturation –13 dBm

Adjacent channel rejection 21 dB Desired channel 3 dB above the sensitivity limit. 750

Alternate channel rejection 30 dB Desired channel 3 dB above the sensitivity limit. 750

See Figure 24 for plot of selectivity versus frequency

Blocking

±10 MHz offset

±20 MHz offset

±50 MHz offset 250 kBaud data rate, current optimized, MDMCFG2.DEM_DCFILT_OFF=1

(MSK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth)

Receiver sensitivity –87 dBm

Saturation –12 dBm

Adjacent channel rejection 21 dB Desired channel 3 dB above the sensitivity limit. 750

Alternate channel rejection 30 dB Desired channel 3 dB above the sensitivity limit. 750

See Figure 25 for plot of selectivity versus frequency

Blocking

±10 MHz offset

±20 MHz offset

±50 MHz offset 500 kBaud data rate, MDMCFG2.DEM_DCFILT_OFF=0 (MDMCFG2.DEM_DCFILT_OFF=1 cannot be used for data rates

>250 kBaud) (MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth)

Receiver sensitivity –83 dBm

Saturation –18 dBm

Adjacent channel rejection 14 dB Desired channel 3 dB above the sensitivity limit. 1 MHz

Alternate channel rejection 25 dB Desired channel 3 dB above the sensitivity limit. 1 MHz

See Figure 26 for plot of selectivity versus frequency

Blocking

±10 MHz offset

±20 MHz offset

±50 MHz offset General

Spurious emissions

25 MHz – 1 GHz

Above 1 GHz

RX latency 9 bit Serial operation. Time from start of reception until data

–57

–47

kHz channel spacing

offset

Wanted signal 3 dB above sensitivity level.

Compliant with ETSI EN 300 440 class 2 receiver requirements.

kHz channel spacing

offset

Wanted signal 3 dB above sensitivity level.

Compliant with ETSI EN 300 440 class 2 receiver

requirements.

channel spacing

offset

Wanted signal 3 dB above sensitivity level.

Compliant with ETSI EN 300 440 class 2 receiver

requirements.

dBm

is available on the receiver data output pin is equal to 9 bit.

Table 5: RF Receive Section

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CC2500

4.3 RF Transmit Section

Tc = 25°C, VDD = 3.0 V, 0 dBm if nothing else stated. All measurement results obtained using the CC2500EM reference design ([4]).

Parameter Min Typ Max Unit Condition/Note

Differential load impedance

Output power, highest setting

Output power, lowest setting

Occupied bandwidth (99%)

Adjacent channel power (ACP)

Spurious emissions

25 MHz – 1 GHz

47-74, 87.5-118, 174230, 470-862 MHz

1800-1900 MHz

At 2·RF and 3·RF

Otherwise above 1 GHz

TX latency 8 bit Serial operation. Time from sampling the data on the

80 + j74

+1 dBm Output power is programmable and full range is available

–30 dBm Output power is programmable and full range is available

117

296

489

-28

-27

-22

-21

kHz

dBc

–36

–54

–47

–41

–30

Differential impedance as seen from the RF-port (RF_P and

Ω

RF_N) towards the antenna. Follow the CC2500EM reference design ([4]) available from the TI website.

across the entire frequency band.

Delivered to a 50 Ω single-ended load via CC2500EM reference design ([4]) RF matching network.

across the entire frequency band.

Delivered to a 50 Ω single-ended load via CC2500EM reference design ([4]) RF matching network.

It is possible to program less than -30 dBm output power, but this is not recommended due to large variation in output power across operating conditions and processing corners for these settings.

2.4 kBaud, 38.2 kHz deviation, 2-FSK

kHz

10 kBaud, 38.2 kHz deviation, 2-FSK

kHz

250 kBaud, MSK

kHz

500 kBaud, MSK

2.4 kBaud, 38.2 kHz deviation, 2-FSK, 250 kHz channel spacing

dBc

10 kBaud, 38.2 kHz deviation, 2-FSK, 250 kHz channel spacing

dBc

250 kBaud, MSK, 750 kHz channel spacing

dBc

500 kBaud, MSK, 1 MHz channel spacing

dBm

Restricted band in Europe

dBm

Restricted bands in USA

dBm

transmitter data input pin until it is observed on the RF output ports.

Table 6: RF Transmit Section

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CC2500

4.4 Crystal Oscillator

Tc = 25°C, VDD = 3.0 V if nothing else stated.

Parameter Min Typ Max Unit Condition/Note

Crystal frequency 26 26 27 MHz

Tolerance ±40 ppm This is the total tolerance including a) initial tolerance, b) crystal

ESR 100

Start-up time 150 µs Measured on CC2500EM reference design ([4]) using crystal

loading, c) aging, and d) temperature dependence.

The acceptable crystal tolerance depends on RF frequency and channel spacing / bandwidth.

Ω

AT-41CD2 from NDK.

This parameter is to a large degree crystal dependent.

Table 7: Crystal Oscillator Parameters

4.5 Low Power RC Oscillator

Tc = 25°C, VDD = 3.0 V if nothing else stated. All measurement results obtained using the CC2500EM reference design ([4]).

Parameter Min Typ Max Unit Condition/Note

Calibrated frequency 34.7 34.7 36 kHz Calibrated RC oscillator frequency is XTAL

Frequency accuracy after calibration

Temperature coefficient +0.4

Supply voltage coefficient +3 % / V Frequency drift when supply voltage changes

Initial calibration time 2 ms When the RC oscillator is enabled, calibration

-1 / +10

% / °C

% The RC oscillator contains an error in the

frequency divided by 750

calibration routine that statistically occurs in

17.3% of all calibrations performed. The given maximum accuracy figures account for the calibration error. Refer also to the Errata Notes.

Frequency drift when temperature changes after calibration

after calibration

is continuously done in the background as long as the crystal oscillator is running.

CC2500

Table 8: RC Oscillator Parameters

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CC2500

4.6 Frequency Synthesizer Characteris tics

Tc = 25°C, VDD = 3.0 V if nothing else stated. All measurement results obtained using the CC2500EM reference design ([4]). Min figures are given using a 27 MHz crystal. Typ and max figures are given using a 26 MHz crystal.

Parameter Min Typ Max Unit Condition/Note

Programmed frequency resolution

Synthesizer frequency tolerance

RF carrier phase noise

PLL turn-on / hop time 85.1 88.4 88.4

PLL RX/TX settling time

PLL TX/RX settling time

PLL calibration time 694 721 721

397 F

9.3 9.6 9.6

20.7 21.5 21.5

XOSC

±40 ppm Given by crystal used. Required accuracy (including

–78 dBc/Hz @ 50 kHz offset from carrier

–78 dBc/Hz @ 100 kHz offset from carrier

–81 dBc/Hz @ 200 kHz offset from carrier

–90 dBc/Hz @ 500 kHz offset from carrier

–100 dBc/Hz @ 1 MHz offset from carrier

–108 dBc/Hz @ 2 MHz offset from carrier

–114 dBc/Hz @ 5 MHz offset from carrier

–118 dBc/Hz @ 10 MHz offset from carrier

412 Hz 26-27 MHz crystal.

temperature and aging) depends on frequency band and channel bandwidth / spacing.

Time from leaving the IDLE state until arriving in the RX,

µs

FSTXON or TX state, when not performing calibration. Crystal oscillator running.

Settling time for the 1·IF frequency step from RX to TX

µs

Settling time for the 1·IF frequency step from TX to RX

µs

Calibration can be initiated manually or automatically

µs

before entering or after leaving RX/TX.

Table 9: Frequency Synthesizer Parameters

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CC2500

4.7 Analog Temperature Sensor

The characteristics of the analog temperature sensor at 3.0 V supply voltage are listed in Table 10 below. Note that it is necessary to write 0xBF to the PTEST register to use the analog temperature sensor in the IDLE state.

Parameter Min Typ Max Unit Condition/Note

Output voltage at –40°C

Output voltage at 0°C

Output voltage at +40°C

Output voltage at +80°C

Temperature coefficient 2.43

Error in calculated temperature, calibrated

Current consumption increase when enabled

0.654 V

0.750 V

0.848 V

0.946 V

mV/°C Fitted from –20°C to +80°C

-2

0.3 mA

0 2

°C From –20°C to +80°C when using 2.43 mV / °C,

after 1-point calibration at room temperature

The indicated minimum and maximum error with 1point calibration is based on measured values for typical process parameters

Table 10: Analog Temperature Sensor Parameters

4.8 DC Characteristics

Tc = 25°C if nothing else stated.

Digital Inputs/Outputs Min Max Unit Condition

Logic "0" input voltage 0 0.7 V

Logic "1" input voltage VDD-0.7 VDD V

Logic "0" output voltage 0 0.5 V For up to 4 mA output current

Logic "1" output voltage VDD-0.3 VDD V For up to 4 mA output current

Logic "0" input current N/A –50 nA Input equals 0 V

Logic "1" input current N/A 50 nA Input equals VDD

Table 11: DC Characteristics

4.9 Power-On Reset

When the power supply complies with the requirements in Table 12 below, proper Power-OnReset functionality is guaranteed. Otherwise, the chip should be assumed to have unknown state until transmitting an SRES strobe over the SPI interface. See Section 19.1 on page 40 for further details.

Parameter Min Typ Max Unit Condition/Note

Power ramp-up time 5 ms From 0 V until reaching 1.8 V

Power off time 1 ms Minimum time between power-on and power-off

Table 12: Power-on Reset Requirements

SWRS040B Page 15 of 92

5 Pin Configuration

GND

RBIAS

DGUARD

GND

20 19 18 17 16

CC2500

SCLK

SO (GDO1)

GDO2

DVDD

DCOUPL

GDO0 (ATEST)

XOSC_Q1

AVDD

CSn

109876

XOSC_Q2

AVDD

RF_N

RF_P

AVDD

GND Exposed die attach pad

Figure 1: Pinout Top View

Note: The exposed die attach pad must be connected to a solid ground plane as this is the main

ground connection for the chip.

SWRS040B Page 16 of 92

CC2500

Pin # Pin name Pin type Description

SCLK

SO (GDO1)

GDO2

4 DVDD Power (Digital) 1.8 - 3.6 V digital power supply for digital I/O’s and for the digital core

5 DCOUPL Power (Digital) 1.6 - 2.0 V digital power supply output for decoupling.

GDO0

(ATEST)

CSn

XOSC_Q1

9 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection

XOSC_Q2

11 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection

RF_P

RF_N

14 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection

15 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection

16 GND Ground (Analog) Analog ground connection

RBIAS

18 DGUARD Power (Digital) Power supply connection for digital noise isolation

19 GND Ground (Digital) Ground connection for digital noise isolation

Digital Input Serial configuration interface, clock input

Digital Output Serial configuration interface, data output.

Optional general output pin when CSn is high

Digital Output Digital output pin for general use:

• Test signals

• FIFO status signals

• Clear Channel Indicator

• Clock output, down-divided from XOSC

• Serial output RX data

voltage regulator

NOTE: This pin is intended for use with the used to provide supply voltage to other devices.

Digital I/O

Digital Input Serial configuration interface, chip select

Analog I/O Crystal oscillator pin 1, or external clock input

Analog I/O Crystal oscillator pin 2

RF I/O Positive RF input signal to LNA in receive mode

RF I/O Negative RF input signal to LNA in receive mode

Analog I/O External bias resistor for reference current

Digital Input Serial configuration interface, data input

Digital output pin for general use:

• Test signals

• FIFO status signals

• Clear Channel Indicator

• Clock output, down-divided from XOSC

• Serial output RX data

• Serial input TX data

Also used as analog test I/O for prototype/production testing

Positive RF output signal from PA in transmit mode

Negative RF output signal from PA in transmit mode

CC2500

only. It can not be

Table 13: Pinout Overview

SWRS040B Page 17 of 92

6 Circuit Description

LNA

RF_P RF_N

RC OSC

BIAS

RADIO CONTROL

ADC

XOSC

FREQ

SYNTH

DEMODULATOR

FEC / INTERLEAVER

MODULATOR

PACKET HANDLER

RXFIFO

DIGITAL INTERFACE TO MCU

TXFIFO

CC2500

SCLK SO (GDO1) SI

CSn

GDO0 (ATEST)

GDO2

RBIAS XOSC_Q1 XOSC_Q2

Figure 2:

CC2500

Simplified Block Dia gram

A simplified block diagram of

CC2500

is shown

in Figure 2.

CC2500

features a low-IF receiver. The received RF signal is amplified by the lownoise amplifier (LNA) and down-converted in quadrature (I and Q) to the intermediate frequency (IF). At IF, the I/Q signals are digitised by the ADCs. Automatic gain control (AGC), fine channel filtering, demodulation bit/packet synchronization are performed digitally.

The transmitter part of

CC2500

is based on

direct synthesis of the RF frequency.

The frequency synthesizer includes a completely on-chip LC VCO and a 90 degrees phase shifter for generating the I and Q LO

signals to the down-conversion mixers in receive mode.

A crystal is to be connected to XOSC_Q1 and XOSC_Q2. The crystal oscillator generates the reference frequency for the synthesizer, as well as clocks for the ADC and the digital part.

A 4-wire SPI serial interface is used for configuration and data buffer access.

The digital baseband includes support for channel configuration, packet handling, and data buffering.

7 Application Circuit

Only a few external components are required for using the

CC2500

application circuit is shown in Figure 3. The external components are described in Table 14, and typical values are given in Table 15.

. The recommended

SWRS040B Page 18 of 92

Bias Resistor

The bias resistor R171 is used to set an accurate bias current.

Balun and RF Matching

The components between the RF_N/RF_P pins and the point where the two signals are joined together (C122, C132, L121, and L131) form a

CC2500

balun that converts the differential RF signal on

CC2500

to a single-ended RF signal. C121 and C131 are needed for DC blocking. Together with an appropriate LC network, the balun components also transform the impedance to match a 50 Ω antenna (or cable). Suggested values are listed in Table

15.

The balun and LC filter component values and their placement are important to keep the performance optimized. It is highly recommended to follow the CC2500EM reference design ([4]).

Component Description

C51 Decoupling capacitor for on-chip voltage regulator to digital part

C81/C101 Crystal loading capacitors, see Section 26 on page 51 for details

C121/C131 RF balun DC blocking capacitors

C122/C132 RF balun/matching capacitors

C123/C124 RF LC filter/matching capacitors

L121/L131 RF balun/matching inductors (inexpensive multi-layer type)

L122 RF LC filter inductor (inexpensive multi-layer type)

R171 Resistor for internal bias current reference

XTAL 26-27 MHz crystal, see Section 26 on page 51 for details

Crystal

The crystal oscillator uses an external crystal with two loading capacitors (C81 and C101). See Section 26 on page 51 for details.

Power Supply Decoupling

The power supply must be properly decoupled close to the supply pins. Note that decoupling capacitors are not shown in the application circuit. The placement and the size of the decoupling capacitors are very important to achieve the optimum performance. The CC2500EM reference design ([4]) should be followed closely.

Table 14: Overview of External Components (excluding supply decoupling capacitors)

1.8V-3.6V power supply

Digital Inteface

SCLK

SO (GDO1) GDO2 (optional)

C51

GDO0 (optional) CSn

1 SCLK

2 SO (GDO1)

3 GDO2

4 DVDD

5 DCOUPL

SI 20

GND 19

CC2500

DIE ATTACH PAD:

6 GDO0

7 CSn

C81 C101

DGUARD 18

8 XOSC_Q1

XTAL

R171

RBIAS 17

9 AVDD

GND 16

AVDD 15

AVDD 14

RF_N 13

RF_P 12

AVDD 11

10 XOSC_Q2

L131

C131

C121

L121

C122

Alternative: Folded dipole PCB antenna (no external components needed)

Antenna

(50 Ohm)

C132

L122

C123 C124

Figure 3: Typical Application and Evaluation Circuit (excluding supply decoupling capacitors)

SWRS040B Page 19 of 92

CC2500

Component Value Manufacturer

C51 100 nF ±10%, 0402 X5R Murata GRM15 series

C81 27 pF ±5%, 0402 NP0 Murata GRM15 series

C101 27 pF ±5%, 0402 NP0 Murata GRM15 series

C121 100 pF ±5%, 0402 NP0 Murata GRM15 series

C122 1.0 pF ±0.25 pF, 0402 NP0 Murata GRM15 series

C123 1.8 pF ±0.25 pF, 0402 NP0 Murata GRM15 series

C124 1.5 pF ±0.25 pF, 0402 NP0 Murata GRM15 series

C131 100 pF ±5%, 0402 NP0 Murata GRM15 series

C132

L121

L122

L131

R171

XTAL

1.0 pF ±0.25 pF, 0402 NP0

1.2 nH ±0.3 nH, 0402 monolithic

56 kΩ ±1%, 0402

26.0 MHz surface mount crystal

Murata GRM15 series

Murata LQG15HS series

Koa RK73 series

NDK, AT-41CD2

Table 15: Bill Of Materials for the Application Circuit

Measurements have been performed with multi-layer inductors from other manufacturers (e.g. Würth) and the measurement results were the same as when using the Murata part.

The Gerber files for the CC2500EM reference design ([4]) are available from the TI website.

8 Configuration Overview

CC2500

performance for many different applications. Configuration is done using the SPI interface. The following key parameters can be programmed:

• Power-down / power up mode

• Crystal oscillator power-up / power-down

• Receive / transmit mode

• RF channel selection

• Data rate

• Modulation format

• RX channel filter bandwidth

• RF output power

• Data buffering with separate 64-byte

can be configured to achieve optimum

receive and transmit FIFOs

Figure 4: CC2500EM Reference Design ([4])

• Packet radio hardware support

• Forward Error Correction (FEC) with

interleaving

• Data Whitening

• Wake-On-Radio (WOR)

Details of each configuration register can be found in Section 32, starting on page 58.

Figure 5 shows a simplified state diagram that explains the main

CC2500

states, together with typical usage and current consumption. For detailed information on controlling the

CC2500

state machine, and a complete state diagram, see Section 19, starting on page 40.

SWRS040B Page 20 of 92

CC2500

Default state when the radio is not receiving or transmitting. Typ. current consumption: 1.5mA.

Used for calibrating frequency synthesizer upfront (entering receive or transmit mode can then be done quicker). Transitional state. Typ. current consumption: 7.4mA.

Frequency synthesizer is on, ready to start transmitting. Transmission starts very quickly after receiving the STX command strobe.Typ. current consumption: 7.4mA.

Typ. current consumption:

11.1mA at -12dBm output,

15.1mA at -6dBm output,

21.2mA at 0dBm output.

SPWD or wake-on-radio (WOR)

SIDLE

Idle

SCAL

Manual freq.

synth. calibration

Frequency

synthesizer on

STX

TXOFF_MODE=01

Transmit mode Receive mode

SRX or STX or SFSTXON or wake-on-radio (WOR)

Frequency

synthesizer startup,

SFSTXON

optional calibration,

settling

STX

SFSTXON or RXOFF_MODE=01

STX or RXOFF_MODE=10

SRX or TXOFF_MODE=11

CSn=0

SXOFF

CSn=0

Frequency synthesizer is turned on, can optionally be calibrated, and then settles to the correct frequency. Transitional state. Typ. current consumption: 7.4mA.

SRX or wake-on-radio (WOR)

Sleep

Crystal

oscillator off

Lowest power mode. Most register values are retained. Typ. current consumption 400nA, or 900nA when wake-on-radio (WOR) is enabled.

All register values are retained. Typ. current consumption; 0.16mA.

Typ. current consumption: from 13.3mA (strong input signal) to 16.6mA (weak input signal).

In FIFO-based modes, transmission is turned off and this state entered if the TX FIFO becomes empty in the middle of a packet. Typ. current consumption: 1.5mA.

TXOFF_MODE=00

TX FIFO

underflow

SFTX

Optional transitional state. Typ. current consumption: 7.4mA.

Optional freq.

synth. calibration

Idle

RXOFF_MODE=00

SFRX

RX FIFO

overflow

In FIFO-based modes, reception is turned off and this state entered if the RX FIFO overflows. Typ. current consumption:

1.5mA.

Figure 5: Simplified State Diagram with Typical Usage and Current Consumption at 250 kBaud

Data Rate and MDMCFG2.DEM_DCFILT_OFF=1 (current optimized)

9 Configuration Software

CC2500

Studio software [5]. The SmartRF

can be configured using the SmartRF®

Studio software is highly recommended for obtaining optimum register settings, and for evaluating performance and functionality. A screenshot of the SmartRF

Studio user interface for

CC2500

is shown in Figure 6.

After chip reset, all the registers have default values as shown in the tables in Section 32. The optimum register setting might differ from the default value. After a reset all registers that shall be different from the default value therefore needs to be programmed through the SPI interface.

SWRS040B Page 21 of 92

CC2500

Figure 6: SmartRF

Studio [5] User Interface

10 4-wire Serial Configuration and Data Interface

CC2500

compatible interface (SI, SO, SCLK and CSn) where

also used to read and write buffered data. All transfers on the SPI interface are done most significant bit first.

All transactions on the SPI interface start with a header byte containing a R/W bit, a burst access bit (B), and a 6-bit address (A

The CSn pin must be kept low during transfers on the SPI bus. If CSn goes high during the

is configured via a simple 4-wire SPI-

CC2500

is the slave. This interface is

– A0).

transfer of a header byte or during read/write from/to a register, the transfer will be cancelled. The timing for the address and data transfer on the SPI interface is shown in Figure 7 with reference to Table 16.

When CSn is pulled low, the MCU must wait until

CC2500

transfer the header byte. This indicates that the crystal is running. Unless the chip was in the SLEEP or XOFF states, the SO pin will always go low immediately after taking CSn low.

SO pin goes low before starting to

SWRS040B Page 22 of 92

CC2500

Figure 7: Configuration Register Write and Read Operations

Parameter Description Min Max Units

SCLK

sp,pd

tsp

tch Clock high 50 - ns

tcl Clock low 50 - ns

Clock rise time - 5 ns

rise

Clock fall time - 5 ns

fall

thd

tns

SCLK frequency

100 ns delay inserted between address byte and data byte (single access), or between address and data, and between each data byte (burst access).

SCLK frequency, single access

No delay between address and data byte

SCLK frequency, burst access

No delay between address and data byte, or between data bytes

CSn low to positive edge on SCLK, in power-down mode

CSn low to positive edge on SCLK, in active mode

Setup data (negative positive edge on

(tsd applies between address and data bytes, and

between data bytes)

Hold data after positive edge on

Negative edge on

SCLK edge) to

SCLK

SCLK to CSn high

Single access 55 - ns tsd

Burst access 76 - ns

- 10 MHz

9 MHz

6.5 MHz

150 µs

20 - ns

Table 16: SPI Interface Timing Requirements

Note: The minimum t

figure in Table 16 can be used in cases where the user does not read the

sp,pd

CHIP_RDYn signal. CSn low to positive edge on SCLK when the chip is woken from power-down depends on the start-up time of the crystal being used. The 150 us in Table 16 is the crystal oscillator start-up time measured on CC2500EM reference design ([4]) using crystal AT-41CD2 from NDK.

10.1 Chip Status Byte

When the header byte, data byte or, command strobe is sent on the SPI interface, the chip

status byte is sent by the

CC2500

on the SO

pin. The status byte contains key status signals, useful for the MCU. The first bit, s7, is the CHIP_RDYn signal; this signal must go low

before the first positive edge of SCLK. The CHIP_RDYn signal indicates that the crystal is running.

Bits 6, 5, and 4 comprise the STATE value. This value reflects the state of the chip. The XOSC and power to the digital core is on in the IDLE state, but all other modules are in power down. The frequency and channel

SWRS040B Page 23 of 92

CC2500

configuration should only be updated when the chip is in this state. The RX state will be active when the chip is in receive mode. Likewise, TX is active when the chip is transmitting.

The last four bits (3:0) in the status byte contains FIFO_BYTES_AVAILABLE. For read operations (the R/W bit in the header byte is set to 1), the FIFO_BYTES_AVAILABLE field

reading from the RX FIFO. For write operations (the R/W bit in the header byte is set to 0), the FIFO_BYTES_AVAILABLE field contains the number of bytes that can be written to the TX FIFO. When FIFO_BYTES_AVAILABLE=15, 15 or more bytes are available/free.

Table 17 gives a status byte summary.

contains the number of bytes available for

Bits Name Description

7 CHIP_RDYn Stays high until power and crystal have stabilized. Should always be low when using

6:4 STATE[2:0] Indicates the current main state machine mode

3:0 FIFO_BYTES_AVAILABLE[3:0] The number of bytes available in the RX FIFO or free bytes in the TX FIFO

the SPI interface.

Value State Description

000 IDLE Idle state

001 RX Receive mode

010 TX Transmit mode

011 FSTXON Frequency synthesizer is on, ready to start

100 CALIBRATE Frequency synthesizer calibration is running

101 SETTLING PLL is settling

110 RXFIFO_OVERFLOW RX FIFO has overflowed. Read out any

111 TXFIFO_UNDERFLOW TX FIFO has underflowed. Acknowledge with

(Also reported for some transitional states instead of SETTLING or CALIBRATE)

transmitting

useful data, then flush the FIFO with

SFTX

SFRX

Table 17: Status Byte Summary

10.2 Register Access

The configuration registers of the

CC2500

are located on SPI addresses from 0x00 to 0x2E. Table 35 on page 59 lists all configuration registers. It is highly recommended to use SmartRF

Studio [5] to generate optimum register settings. The detailed description of each register is found in Section 32.1, starting on page 62. All configuration registers can be both written to and read. The R/W bit controls if the register should be written to or read. When writing to registers, the status byte is sent on the SO pin each time a header byte or data byte is transmitted on the SI pin. When reading from registers, the status byte is sent on the SO pin each time a header byte is transmitted on the SI pin.

Registers with consecutive addresses can be accessed in an efficient way by setting the

SWRS040B Page 24 of 92

burst bit (B) in the header byte. The address bits (A

– A0) set the start address in an

internal address counter. This counter is incremented by one each new byte (every 8 clock pulses). The burst access is either a read or a write access and must be terminated by setting CSn high.

For register addresses in the range 0x300x3D, the burst bit is used to select between status registers, burst bit is one, and command strobes, burst bit is zero (see Section 10.4 below). Because of this, burst access is not available for status registers and they must be accessed one at a time. The status registers can only be read.

10.3 SPI Read

When reading register fields over the SPI interface while the register fields are updated

CC2500

by the radio hardware (e.g. MARCSTATE or TXBYTES), there is a small, but finite,

probability that a single read from the register is being corrupt. As an example, the probability of any single read from TXBYTES being corrupt, assuming the maximum data rate is used, is approximately 80 ppm. Refer to the

CC2500

10.4 Command Strobes

Command strobes may be viewed as single byte instructions to command strobe register, internal sequences will be started. These commands are used to disable the crystal oscillator, enable receive mode, enable wake-on-radio etc. The 13 command strobes are listed in Table 34 on page 58.

The command strobe registers are accessed by transferring a single header byte (no data is being transferred). That is, only the R/W bit, the burst access bit (set to 0), and the six address bits (in the range 0x30 through 0x3D)

are written. The R/W bit can be either one or zero and will determine how

the FIFO_BYTES_AVAILABLE field in the status byte should be interpreted.

When writing command strobes, the status byte is sent on the SO pin.

A command strobe may be followed by any other SPI access without pulling CSn high. However, if an SRES strobe is being issued, one will have to wait for SO to go low again before the next header byte can be issued as shown in Figure 8. The command strobes are executed immediately, with the exception of the SPWD and the SXOFF strobes that are executed when CSn goes high.

Errata Notes [1] for more details.

CC2500

. By addressing a

The TX FIFO is write-only, while the RX FIFO is read-only.

The burst bit is used to determine if the FIFO access is a single byte access or a burst access. The single byte access method expects a header byte with the burst bit set to zero and one data byte. After the data byte a new header byte is expected; hence, CSn can remain low. The burst access method expects one header byte and then consecutive data bytes until terminating the access by setting CSn high.

The following header bytes access the FIFOs:

• 0x3F: Single byte access to TX FIFO

• 0x7F: Burst access to TX FIFO

• 0xBF: Single byte access to RX FIFO

• 0xFF: Burst access to RX FIFO

When writing to the TX FIFO, the status byte (see Section 10.1) is output for each new data byte on SO, as shown in Figure 7. This status byte can be used to detect TX FIFO underflow while writing data to the TX FIFO. Note that the status byte contains the number of bytes

free before writing the byte in progress to the

TX FIFO. When the last byte that fits in the TX FIFO is transmitted on SI, the status byte received concurrently on SO will indicate that one byte is free in the TX FIFO.

The TX FIFO may be flushed by issuing a SFTX command strobe. Similarly, a SFRX command strobe will flush the RX FIFO. A SFTX or SFRX command strobe can only be issued in the IDLE, TXFIFO_UNDERLOW or RXFIFO_OVERFLOW states. Both FIFOs are flushed when going to the SLEEP state.

Figure 9 gives a brief overview of different register access types possible.

Figure 8: SRES Command Strobe

10.5 FIFO Access

The 64-byte TX FIFO and the 64-byte RX FIFO are accessed through the 0x3F address. When the R/W bit is zero, the TX FIFO is accessed, and the RX FIFO is accessed when the R/W bit is one.

SWRS040B Page 25 of 92

10.6 PATABLE Access

The 0x3E address is used to access the PATABLE, which is used for selecting PA power control settings. The PATABLE is an 8byte table, but not all entries into this table are used. The entries to use are selected by the 3bit value FREND0.PA_POWER.

• When using 2-FSK, GFSK, or MSK

modulation only the first entry into this table is used (index 0).

CC2500

• When using OOK modulation the first two

entries into this table are used (index 0 and index 1).

Since the PATABLE is an 8-byte table, the table is written and read from the lowest setting (0) to the highest (7), one byte at a time. An index counter is used to control the access to the table. This counter is incremented each time a byte is read or written to the table, and set to the lowest index when CSn is high. When the highest value is reached the counter restarts at 0.

The access to the PATABLE is either single byte or burst access depending on the burst bit. When using burst access the index counter will count up; when reaching 7 the counter will restart at 0. The R/W bit controls whether the

access is a write access (R/W=0) or a read access (R/W=1).

If one byte is written to the PATABLE and this value is to be read out then CSn must be set high before the read access in order to set the index counter back to zero.

Note that the content of the PATABLE is lost when entering the SLEEP state, except for the first byte (index 0).

See Section 24 on page 47 for output power programming details.

Figure 9: Register Access Types

11 Microcontroller Interface and Pin Configuration

In a typical system, microcontroller. This microcontroller must be able to:

• Program

• Read and write buffered data

• Read back status information via the 4-wire

SPI-bus configuration interface (SI, SO, SCLK and CSn)

11.1 Configuration Interface

The microcontroller uses four I/O pins for the SPI configuration interface (SI, SO, SCLK and CSn). The SPI is described in Section 10 on page 22.

CC2500

into different modes

will interface to a

11.2 General Control and Status Pins

The

CC2500

pins (GDO0 and GDO2) and one shared pin (GDO1) that can output internal status information useful for control software. These pins can be used to generate interrupts on the MCU. See Section 28 on page 52 for more details on the signals that can be programmed. GDO1 is shared with the SO pin in the SPI interface. The default setting for GDO1/SO is 3state output. By selecting any other of the programming options the GDO1/SO pin will become a generic pin. When CSn is low, the pin will always function as a normal SO pin.

In the synchronous and asynchronous serial modes, the GDO0 pin is used as a serial TX data input pin while in transmit mode.

has two dedicated configurable

SWRS040B Page 26 of 92

CC2500

The GDO0 pin can also be used for an on-chip analog temperature sensor. By measuring the voltage on the GDO0 pin with an external ADC, the temperature can be calculated. Specifications for the temperature sensor are found in Section 4.7 on page 15.

With default PTEST register setting (0x7F) the temperature sensor output is only available when the frequency synthesizer is enabled (e.g. the MANCAL, FSTXON, RX and TX states). It is necessary to write 0xBF to the PTEST register to use the analog temperature sensor in the IDLE state. Before leaving the IDLE state, the PTEST register should be restored to its default value (0x7F).

11.3 Optional Radio Control Feature

The

CC2500

has an optional way of controlling

the radio, by reusing SI, SCLK and CSn from the SPI interface. This feature allows for a simple three-pin control of the major states of the radio: SLEEP, IDLE, RX and TX.

This optional functionality is enabled with the MCSM0.PIN_CTRL_EN configuration bit.

State changes are commanded as follows: When CSn is high the SI and SCLK is set to the desired state according to Table 18. When CSn goes low the state of SI and SCLK is latched and a command strobe is generated internally according to the control coding. It is only possible to change state with this functionality. That means that for instance RX will not be restarted if SI and SCLK are set to RX and CSn toggles. When CSn is low the SI and SCLK has normal SPI functionality.

All pin control command strobes are executed immediately, except the SPWD strobe, which is delayed until CSn goes high.

CSn SCLK SI

1 X X Chip unaffected by SCLK/SI

↓ ↓ ↓ ↓

0 0 Generates

0 1 Generates

1 0 Generates

1 1 Generates

SPI

mode

Function

SPI

SPI mode (wakes up into IDLE if in SLEEP/XOFF)

SPWD strobe STX strobe SIDLE strobe SRX strobe

Table 18: Optional Pin Contr ol Coding

12 Data Rate Programming

The data rate used when transmitting, or the data rate expected in receive is programmed by the MDMCFG3.DRATE_M and the MDMCFG4.DRATE_E configuration registers. The data rate is given by the formula below. As the formula shows, the programmed data rate depends on the crystal frequency.

R ⋅

()

DATA

2_256

MDRATE

⋅+

The following approach can be used to find suitable values for a given data rate:

⎢

⎛

DATA

⎜

log_

EDRATE

⎢

⎜

⎝

DATA

⋅

XOSC

⋅

⎢

⎣

MDRATE

XOSC

EDRATE

XOSC

⎥

⎞

⋅

⎟

⎥

⎟

⎥

⎠

⎦

−

256

EDRATE

If DRATE_M is rounded to the nearest integer and becomes 256, increment DRATE_E and use DRATE_M=0.

The data rate can be set from 1.2 kBaud to 500 kBaud with the minimum step size of:

Min Data

Rate

[kBaud]

0.8 1.2/2.4 3.17 0.0062

3.17 4.8 6.35 0.0124

6.35 9.6 12.7 0.0248

12.7 19.6 25.4 0.0496

25.4 38.4 50.8 0.0992

50.8 76.8 101.6 0.1984

101.6 153.6 203.1 0.3967

203.1 250 406.3 0.7935

406.3 500 500 1.5869

Typical

Data Rate

[kBaud]

Max Data

Rate

[kBaud]

Data Rate Step Size

[kBaud]

Table 19: Data Rate Step Size

SWRS040B Page 27 of 92

13 Receiver Channel Filter Bandwidth

CC2500

In order to meet different channel width requirements, the receiver channel filter is programmable. The MDMCFG4.CHANBW_E and MDMCFG4.CHANBW_M configuration registers control the receiver channel filter bandwidth, which scales with the crystal oscillator frequency. The following formula gives the relation between the register settings and the channel filter bandwidth:

For best performance, the channel filter bandwidth should be selected so that the signal bandwidth occupies at most 80% of the channel filter bandwidth. The channel centre tolerance due to crystal accuracy should also be subtracted from the signal bandwidth. The following example illustrates this:

With the channel filter bandwidth set to 600 kHz, the signal should stay within 80% of 600

channel

XOSC

MCHANBW

2)·_4(8 +⋅

ECHANBW

kHz, which is 480 kHz. Assuming 2.44 GHz frequency and ±20 ppm frequency uncertainty for both the transmitting device and the receiving device, the total frequency uncertainty is ±40 ppm of 2.44 GHz, which is ±98 kHz. If the whole transmitted signal bandwidth is to be received within 480 kHz, the transmitted signal bandwidth should be maximum 480 kHz – 2·98 kHz, which is 284 kHz.

CC2500

The filter bandwidths:

Table 20: Channel Filter Bandwidths [kHz]

supports the following channel

MDMCFG4. MDMCFG4.CHANBW_E

CHANBW_M 00 01 10 11

00 812 406 203 102 01 650 325 162 81 10 541 270 135 68 11 464 232 116 58

(assuming a 26 MHz crystal)

14 Demodulator, Symbol Synchronizer and Data Decision

CC2500

configurable demodulator. Channel filtering and frequency offset compensation is performed digitally. To generate the RSSI level (see Section 17.3 for more information) the signal level in the channel is estimated. Data filtering is also included for enhanced performance.

14.1 Frequency Offset Compensation

When using 2-FSK, GFSK, or MSK modulation, the demodulator will compensate for the offset between the transmitter and receiver frequency, within certain limits, by estimating the centre of the received data. This value is available in the FREQEST status register. Writing the value from FREQEST into FSCTRL0.FREQOFF the frequency synthesizer is automatically adjusted according to the estimated frequency offset.

The tracking range of the algorithm is selectable as fractions of the channel bandwidth with the FOCCFG.FOC_LIMIT configuration register.

contains an advanced and highly

If the FOCCFG.FOC_BS_CS_GATE bit is set, the offset compensator will freeze until carrier sense asserts. This may be useful when the radio is in RX for long periods with no traffic, since the algorithm may drift to the boundaries when trying to track noise.

The tracking loop has two gain factors, which affects the settling time and noise sensitivity of the algorithm. FOCCFG.FOC_PRE_K sets the gain before the sync word is detected, and FOCCFG.FOC_POST_K selects the gain after the sync word has been found.

Note that frequency offset compensation is not supported for OOK modulation.

14.2 Bit Synchronization

The bit synchronization algorithm extracts the clock from the incoming symbols. The algorithm requires that the expected data rate is programmed as described in Section 12 on page 27. Re-synchronization is performed continuously to adjust for error in the incoming symbol rate.

SWRS040B Page 28 of 92

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TEXAS INSTRUMENTS CC2500 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

Applications

Product Description

Analog Features

Digital Features

Low-Power Features

General

Abbreviations

Table of Contents

Current consumption

4.3 RF Transmit Section

4.5 Low Power RC Oscillator

4.6 Frequency Synthesizer Characteris tics

4.7 Analog Temperature Sensor

11.2 General Control and Status Pins

11.3 Optional Radio Control Feature