TEXAS INSTRUMENTS CC2400 Technical data

CC2400

2.4 GHz Low-Power RF Transceiver

Applications

• 2.4 GHz MHz ISM/SRD band systems

• Game controllers

• Sports and leisure equipment

Product Description

The

CC2400

RF transceiver designed for low-power and low-voltage wireless applications. The RF transceiver is integrated with a baseband modem supporting data rates up to 1 Mbps.

The

CC2400

solution enabling robust wireless communication in the 2.4 - 2.4835 GHz unlicensed ISM band. It is intended for systems compliant with world-wide regulations covered by EN 300 440 (Europe), CFR47 Part 15 (US) and ARIB STD-T66 (Japan).

Targeting a wide range of applications at

2.4 GHz, the data rates of 10 kbps, 250 kbps and 1 Mbps without requiring any modifications to the hardware.

The support for packet handling, data buffering, burst transmissions, data coding

is a true single-chip 2.4 GHz

is a low-cost, highly integrated

CC2400

supports over-the-air

CC2400

provides extensive hardware

• Wireless audio

• PC peripherals

• Advanced toys

and error detection reducing the workload on the host microcontroller.

The main operating parameters of can be programmed via an SPI-bus. In a typical system together with a microcontroller and a few external, passive components.

CC2400

is based on Chipcon’s SmartRF-

03 technology in 0.18 µm CMOS.

CC2400

will be used

Key Features

• True single-chip 2.4 GHz RF transceiver with baseband modem

• 10 kbps, 250 kbps and 1 Mbps over- the-air data rates

• Low current consumption (RX: 24 mA)

• Low core supply voltage (1.8 V)

• Programmable output power

• No external RF switch / filter needed

• I/Q low-IF receiver

• I/Q direct up-conversion transmitter

• Few external components

• FIFO allows bursting of data

This document contains information on a pre-production product. Specifications and information herein are subject to change without notice.

SWRS042A Page 1 of 83

• Packet handling hardware

• Data buffering

• Digital RSSI output

• Small size (QFN 48 package), 7x7 mm

• Reference design complies with EN

300 328, EN 300 440, FCC CFR47 part 15 and ARIB STD-T66

• Powerful and flexible development tools available

• Easy-to-use software for generating the

CC2400

configuration data

CC2400

Table of contents

1 ABBREVIATIONS.............................................................................................................. 4

2 FEATURES........................................................................................................................5

3 ABSOLUTE MAXIMUM RATINGS.................................................................................... 6

4 OPERATING CONDITIONS .............................................................................................. 6

5 ELECTRICAL SPECIFICATIONS ..................................................................................... 7

6 GENERAL CHARACTERISTICS...................................................................................... 7

7 RF TRANSMIT SECTION............................................................ ...................................... 8

8 RF RECEIVE SECTION............................................................ ......................................... 9

9 AFC SECTION........................................................................................ ......................... 10

10 RSSI / CARRIER SENSE SECTION............................................................................ 11

11 IF SECTION.................................................................................................................. 11

12 FREQUENCY SYNTHESIZER SECTION.................................................................... 11

13 DIGITAL INPUTS/OUTPUTS....................................................................................... 12

14 PIN ASSIGNMENT....................................................................................................... 13

15 CIRCUIT DESCRIPTION ............................................................................................. 15

16 APPLICATION CIRCUIT.............................................................................................. 17

16.1 INPUT / OUTPUT MATCHING ....................................................................................... 17

16.2 BIAS RESISTOR ........................................................................................................ 17

16.3 CRYSTAL................................................................................................................. 17

16.4 DIGITAL I/O ............................................................................................................. 17

16.5 POWER SUPPLY DECOUPLING AND FILTERING ............................................................ 17

16.6 POWER SUPPLY SWITCHING...................................................................................... 17

17 CONFIGURATION OVERVIEW................................................................................... 20

18 CONFIGURATION SOFTWARE.................................................................................. 20

19 4-WIRE SERIAL CONFIGURATION INTERFACE...................................................... 21

20 OVERVIEW OF CONFIGURATIONS AND HARDWARE SUPPORT ........................ 24

21 MICROCONTROLLER INTERFACE AND PIN CONFIGURATION ........................... 25

21.1 CONFIGURATION INTERFACE ..................................................................................... 25

21.2 SIGNAL INTERFACE IN UN-BUFFERED MODE................................................................ 25

21.3 GENERAL CONTROL AND STATUS PINS....................................................................... 25

22 DATA BUFFERING...................................................................................................... 27

22.1 BUFFERED MODE ..................................................................................................... 27

22.2 BUFFERED MODE HARDWARE SUPPORT..................................................................... 27

23 PACKET HANDLING HARDWARE SUPPORT.......................................................... 29

23.1 DATA PACKET FORMAT ............................................................................................. 29

23.2 ERROR DETECTION .................................................................................................. 29

23.3 HARDWARE INTERFACE ............................................................................................ 31

24 DATA / LINE ENCODING ............................................................................................ 31

24.1 DATA ENCODING IN BUFFERED MODE......................................................................... 31

24.2 DATA ENCODING IN UN-BUFFERED MODE ................................................................... 32

25 RADIO CONTROL STATE MACHINE ........................................................................ 34

26 POWER MANAGEMENT FLOW CHART ................................................................... 36

27 FSK MODULATION FORMATS .................................................................................. 38

28 BUILT-IN TEST PATTERN GENERATOR.................................................... .............. 38

29 RECEIVER CHANNEL BANDWIDTH ......................................................................... 39

30 DATA RATE PROGRAMMING.................................................................................... 40

31 DEMODULATOR, BIT SYNCHRONIZER AND DATA DECISION............................. 41

32 AUTOMATIC FREQUENCY CONTROL ..................................................................... 42

33 LINEAR IF AND AGC SETTINGS ............................................................................... 43

34 RSSI.............................................................................................................................. 44

35 CARRIER SENSE ........................................................................................................ 45

36 INTERFACING AN EXTERNAL LNA OR PA ............................................................. 45

37 GENERAL PURPOSE / TEST OUTPUT CONTROL PINS......................................... 45

38 FREQUENCY PROGRAMMING.................................................................................. 47

SWRS042A Page 2 of 83

CC2400

38.1 TRANSMIT MODE ...................................................................................................... 47

38.2 RECEIVE MODE ........................................................................................................ 47

39 ALTERNATE TX IF SETTING ..................................................................................... 47

40 VCO.............................................................................................................................. 48

41 VCO SELF-CALIBRATION.......................................................................................... 48

42 OUTPUT POWER PROGRAMMING........................................................................... 48

43 CRYSTAL OSCILLATOR ............................................................................................ 49

44 INPUT / OUTPUT MATCHING..................................................................................... 50

45 TYPICAL PERFORMANCE GRAPHS......................................................................... 50

46 SYSTEM CONSIDERATIONS AND GUIDELINES ..................................................... 53

46.1 SRD REGULATIONS.................................................................................................. 53

46.2 FREQUENCY HOPPING AND MULTI-CHANNEL SYSTEMS ................................................ 53

46.3 DATA BURST TRANSMISSIONS ................................................................................... 53

46.4 CONTINUOUS TRANSMISSIONS.................................................................................. 53

46.5 CRYSTAL DRIFT COMPENSATION ............................................................................... 53

46.6 SPECTRUM EFFICIENT MODULATION .......................................................................... 54

46.7 LOW LATENCY SYSTEMS........................................................................................... 54

46.8 LOW COST SYSTEMS ................................................................................................ 54

46.9 BATTERY OPERATED SYSTEMS.................................................................................. 54

46.10 INCREASING OUTPUT POWER .................................................................................... 54

47 PCB LAYOUT RECOMMENDATIONS ....................................................................... 56

48 ANTENNA CONSIDERATIONS .................................................................................. 57

49 CONFIGURATION REGISTERS ................................................................................. 58

50 PACKAGE DESCRIPTION (QFN48)........................................................................... 76

51 RECOMMENDED LAYOUT FOR PACKAGE (/QFN48)............................................. 77

52 PACKAGE THERMAL PROPERTIES......................................................................... 77

53 SOLDERING INFORMATION...................................................................................... 77

54 IC MARKING................................................................................................................ 78

55 PLASTIC TUBE SPECIFICATION............................................................................... 80

56 CARRIER TAPE AND REEL SPECIFICATION .......................................................... 80

57 ORDERING INFORMATION............................................................... ......................... 80

58 GENERAL INFORMATION..................................................................... ..................... 81

58.1 DOCUMENT HISTORY ............................................................................................... 81

58.2 PRODUCT STATUS DEFINITIONS................................................................................ 82

58.3 DISCLAIMER............................................................................................................. 82

58.4 TRADEMARKS .......................................................................................................... 82

58.5 LIFE SUPPORT POLICY ............................................................................................. 82

59 ADDRESS INFORMATION.......................................................................................... 83

SWRS042A Page 3 of 83

1 Abbreviations

ACP Adjacent Channel Power ACR Adjacent Channel Rejection ADC Analog-to-Digital Converter AFC Automatic Frequency Correction AGC Automatic Gain Control BER Bit Error Rate BOM Bill Of Materials bps bits per second BT Bandwidth-Time product (for GFSK) CRC Cyclic Redundancy Check CSMA Carrier Sense Multiple Access CSMA / CA Carrier Sense Multiple Access / Collision Avoidance DAC Digital-to-Analog Converter ESR Equivalent Series Resistance FH Frequency Hopping FHSS Frequency Hopping Spread Spectrum FIFO First In First Out (queue) FS Frequency Synthesizer FSK Frequency Shift Keying GFSK Gaussian Frequency Shift Keying IF Intermediate Frequency ISM Industrial Scientific Medical kbps kilo bits per second LNA Low Noise Amplifier Mbps Mega bits per second MCU Micro Controller Unit NRZ Non Return to Zero PA Power Amplifier PD Phase Detector PCB Printed Circuit Board PN9 Pseudo-random Bit Sequence (9-bit) PLL Phase Locked Loop PRN Pseudo Random Number PRNG Pseudo Random Number Generator RF Radio Frequency RSSI Received Signal Strength Indicator RX Receive (mode) SPI Serial Peripheral Interface SRD Short Range Device TBD To Be Decided/Defined TDMA Time Division Multiple Access TX Transmit (mode) VCO Voltage Controlled Oscillator VGA Variable Gain Amplifier

CC2400

SWRS042A Page 4 of 83

2 Features

CC2400

• 2400 – 2483 MHz RF transceiver

• GFSK and FSK modulation

• Very low current consumption (RX:

24 mA)

• Over-the-air data rates of 10 kbps, 250 kbps and 1 Mbps

• High sensitivity (-87 dBm @ 1Mbps, BER=10

• Agile frequency synthesizer (40 us settling time)

• On-chip VCO, LNA and PA

• Low core supply voltage (1.6-2.0 V)

• Flexible I/O supply voltage

(1.6–3.6 V) to match the signal levels of the interfacing microcontroller

• Programmable output power

• I/Q low-IF receiver

• I/Q direct up-conversion transmitter

• Few external components

• Only reference crystal and a few

passives needed

• No external filters needed

• Programmable baseband modem

• 4-wire SPI interface

• Serial clock up to 20 MHz

• Digital RSSI output

-3

)

• Packet handling hardware support

• Preamble generator with

programmable length

• Programmable synchronization word insertion/detection

• CRC computation over the data field

• 8B/10B line coding option

• Data buffering

• 32 byte FIFO

• Provides for flexible communication

with the host controller.

• Burst transmission reduces the average power consumption.

• Powerful and flexible development tools available

• Fully equipped development kit

• Demonstration board reference

design with microcontroller code

• Easy-to-use SmartRF Studio

software for generating the configuration data

• Small size (QFN 48 package) 7 x 7 mm

• Reference design complies with EN

300 328, EN 300 440, FCC CFR47 part 15 and ARIB STD-T66

CC2400

SWRS042A Page 5 of 83

CC2400

3 Absolute Maximum Ratings

Supply voltage, chip core, AVDD/DVDD1.8=VDD Supply voltage (DVDD3.3=VDDIO), digital I/O −0.3 3.6 V Voltage on any pin, core −0.3 VDD+0.3,

Voltage on any pin, digital I/O (pin no. 27-35) −0.3 VDDIO+0.3,

Input RF level 10 dBm Storage temperature range −50 150 Reflow solder temperature 260

NOTE:

The supply voltage to the chip core (AVDD/DVDD1.8) should not be switched off when the digital IO (DVDD3.3)

supply voltage is still applied to the chip. If this is done, a large current will flow inside the be damaged as a result.

If the core supply needs to be switched off to lower the power consumption, please see page 17 for a suggested solution.

The absolute maximum ratings given above should under no circumstances be violated. Stress exceeding one or more of

Parameter Min. Max. Units Condition

−0.3 2.0 V

max 2.0

max 3.6

°C °C

CC2400

the limiting values may cause permanent damage to the device.

Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage.

T = 10 s

and the chip may

4 Operating Conditions

Parameter Min. Typ. Max. Unit Condition

Supply voltage, chip core, AVDD/DVDD1.8 Supply voltage (DVDD3.3), digital I/O, VDDIO

Recommended supply voltage, chip core, AVDD/DVDD1.8 Recommended supply voltage (DVDD3.3), digital I/O Operating ambient temperature range

1.6 2.0 V

1.6 3.6 V The digital I/O voltage (DVDD3.3

1.8V

1.8V/

3.3V

−40 85

SWRS042A Page 6 of 83

pin) must match the interfacing circuit.

°C

5 Electrical Specificati ons

CC2400

Parameter

Current Consumption, Power Down mode (OFF)

Current Consumption, Idle mode (IDLE)

Current Consumption, Frequency synthesizer (FS_ON)

Current Consumption, Receive mode

Current Consumption, Transmit mode:

P=−25 dBm

P=−5 dBm

P=0 dBm

Current Consumption, crystal oscillator core

Min. Typ. Max. Unit Condition / Note

1.5

1.2

6.3

24 mA

Oscillator core off

µA

The output power is delivered differentially to a 50Ω single-

ended load through a balun, see also p. 50.

16 MHz, 16 pF load crystal

µA

Table 1 Electrical specifications

6 General Characteristics

Tc = 25°C, AVDD/DVDD1.8 = 1.8 V, DVDD3.3 = 3.3V (digital I/O) if nothing else stated. Measured on Chipcon’s CC2400EM reference design.

Parameter

RF Frequency Range 2400

Data rate

Min. Typ. Max. Unit Condition / Note

250

2483 MHz Programmable in 1 MHz channel

kbps

Mbps

steps.

Data rate is

kbps

programmable/selectable, see page 40

Table 2 General characteristics

SWRS042A Page 7 of 83

CC2400

7 RF Transmit section

Tc = 25°C, AVDD/DVDD1.8 = 1.8 V, DVDD3.3 = 3.3V (digital I/O) if nothing else stated. Measured on Chipcon’s CC2400EM reference design.

Parameter

Binary FSK frequency deviation

Nominal output power 0 dBm Default settings.

Programmable output power range

Min. Typ. Max. Unit Condition / Note

250 500

25 dB

±kHz

The frequency corresponding to the digital "0" is denoted f

corresponds to a digital "1".

The frequency deviation is given by f

=±(f1−f0)/2. The RF carrier

frequency, f f

=(f0+f1)/2.

Power delivered to a 50 Ω singleended load through a balun. The output power is programmable in 8 steps.

, is then given by

, while

20 dB bandwidth

FSK GFSK

Adjacent Channel Power (ACP)

FSK GFSK

Harmonics

order harmonic

Spurious emission 30 - 1000 MHz 1– 12.75 GHz

1.8 – 1.9 GHz

5.15 – 5.3 GHz

Optimum load impedance 110

1.2

1.0

-30

-43

-41

-54

-65

-41

-69

-65

+ j130

Table 3 Transmit characteristics

-36

-30

-47

MHz MHz

dBc dBc

dBm dBm

dBm dBm dBm dBm

Ω

Maximum output power. Modulation is 1 Mbps, NRZ data, ± 250 kHz frequency deviation.

Maximum output power. Modulation is 1 Mbps, NRZ data, ± 250 kHz frequency deviation. Measured at 2 MHz offset.

At max output power delivered to 50 Ω single-ended load through a balun. Carrier modulated with pseudo-random data. See p.50.

Maximum output power. Modulation is 1 Mbps FSK, NRZ data, ±250 kHz frequency deviation. Complying with EN 300 440, CFR47 Part 15 and ARIB STDT66 Differential impedance as seen from the RF-port (RF_P and RF_N) towards the antenna. For matching details see “Input/ output matching” page 50 as well as the application circuit description on page 17.

SWRS042A Page 8 of 83

CC2400

8 RF Receive section

Tc = 25°C, AVDD/DVDD1.8 = 1.8 V, DVDD3.3 = 3.3V (digital I/O) if nothing else stated. Measured on Chipcon’s CC2400EM reference design.

Parameter

Receiver Sensitivity at BER = 10−3

1 Mbps, 1 MHz channel BW 250 kbps, 1 MHz channel BW 10 kbps, 500 kHz channel BW

Saturation (maximum input level) 3 dBm Maximum gain in LNA.

Co-channel rejection

Adjacent channel rejection (ACR)

1 Mbps 250 kbps

Image channel rejection

1 Mbps 250 kbps

Selectivity (C/I) (In-band channel rejection)

+ 2MHz ± 3MHz ± 4MHz ± 5MHz ± 10MHz ± 20 MHz ± 50MHz

+ 2 MHz ± 3 MHz ± 4 MHz ± 5 MHz ± 10 MHz ± 20 MHz ± 50 MHz

Min. Typ. Max. Unit Condition / Note

-87

-91

-101

-10 dB 1 Mbps wanted signal 10 dB

21 39

20 41 50 52 55 56 59

48 50 55 56 59 60 64

SWRS042A Page 9 of 83

Measured in a 50 Ohm singleended load through a balun. FSK, NRZ mode used.

dBm

±250 kHz frequency deviation

dBm

±250 kHz frequency deviation

dBm

±125 kHz frequency deviation

NRZ coded data, BER = 10

above the sensitivity level, interferer modulated like signal (pseudo-random FSK, ± 250 kHz deviation), interferer at operating frequency, BER = 10

FSK wanted signal 10 dB above the sensitivity level, 1 MHz

channel spacing, interferer

modulated like signal (pseudorandom FSK, ± 250 kHz deviation) at adjacent channel, BER = 10

FSK wanted signal 10 dB above the sensitivity level, interferer

modulated like signal (pseudo-

random FSK, ± 250 kHz deviation) at image frequency, BER = 10 is centered 2MHz below the center frequency of the desired channel.

1Mbps FSK wanted signal at

2441 MHz, 3 dB above the

sensitivity level (except + 2 MHz,

which is 10 dB above the

sensitivity limit), jammer

modulated like signal (pseudo-

random, ± 250 kHz deviation) at ± 2-39 MHz in 1 MHz steps offset, BER = 10 channels and image channel are excluded.

250 kbps FSK wanted signal at

2441 MHz, 3 dB above the

sensitivity level (except + 2 MHz,

which is 10 dB above the

sensitivity limit), jammer

modulated like signal (pseudo-

random, ± 250 kHz deviation) at ± 2-39 MHz in 1 MHz steps offset, BER = 10 channels and image channel are excluded.

−3

. The image channel

−3

. Adjacent

−3

. Adjacent

−3

Parameter

Blocking / Desensitization* (*out-of-band spurious response rejection)

0.3 – 2.0 GHz

2.0 – 2.399 GHz

2.498 – 3.0 GHz 3 – 12.75 GHz

Input IIP3

Out of band In band

Image frequency suppression

Spurious reception

Spurious emission < 1 GHz 1 – 12.75 GHz

Min. Typ. Max. Unit Condition / Note

56 dB Ratio between sensitivity for a

80 dB Ratio between the sensitivity for

71 50 49 76

-5

-17

−70

−56

-57

-47

dB dB dB dB

dBm dBm

1 Mbps FSK wanted signal 3 dB above the sensitivity level, sinewave interfering signal, BER =

−3

Measured directly by applying two tones and measuring the resulting difference tone amplitude.

signal at the image frequency and the sensitivity in the wanted channel with an inverted signal. The image frequency is centered

-2 MHz from the center of the wanted channel. The signal source is 1Mbps, NRZ coded data, ±250 kHz frequency deviation, signal level for BER =

−3

an unwanted frequency and the sensitivity in the wanted channel. The signal source is a 1 Mbps, NRZ coded data, ±250 kHz frequency deviation, swept over all frequencies 2400 – 2483.5 MHz. Signal level for BER = 10 Adjacent channels and image channel are excluded.

Complying with EN 300 440, CFR47 Part 15 and ARIB STDT66

Table 4 RF Receive characteristics

CC2400

−3

9 AFC section

Parameter

AFC range

AFC accuracy 5 kHz

Min. Typ. Max. Unit Condition / Note

For 1Mbps and 1 MHz channel

± 500 kHz Measured using an unmodulated

Table 5 AFC characteristics

SWRS042A Page 10 of 83

width,

AFC_SETTLING=4.

carrier.

10 RSSI / Carrier Sense section

CC2400

Parameter

Min. Typ. Max. Unit Condition / Note

RSSI range / Carrier sense range

RSSI settling time 20 s RSSI accuracy

For 1Mbps and 1 MHz channel

80 dB (The range is from –100 dBm to

± 4

dB See page 44 for details

Table 6 RSSI / Carrier sense characteristics

11 IF section

Parameter

Intermediate frequency (IF)

Digital channel filter bandwidth

Min. Typ. Max. Unit Condition / Note

1 MHz

125 1000 kHz The digital channel filter 6dB-

Table 7 IF characteristics

12 Frequency Synthesizer section

width.

–20 dBm typically)

bandwidth is programmable in steps: 125, 250, 500 and 1000 kHz. See page 39 for details.

Parameter

Min. Typ. Max. Unit Condition / Note

Crystal oscillator frequency

Crystal frequency accuracy requirement

Crystal operation

Crystal load capacitance

Crystal ESR

Crystal oscillator start-up time 1.13 ms 16 pF load

Phase noise

PLL loop bandwidth 50 kHz

16 MHz See page 49 for details.

20 ±ppm

Parallel C4 and C5 are loading

12 16 20 pF 16 pF recommended

-108

-114

SWRS042A Page 11 of 83

dBc/Hz dBc/Hz dBc/Hz

The total crystal frequency accuracy, i.e. initial tolerance plus aging and temperature dependency, will determine the frequency accuracy of the transmitted signal. 1 Mbps FSK, 250 kHz deviation.

capacitors, see page 49

Ω

Note: This time can be reduced to 15 s by enabling the XOSC core in power-down using the MANAND register.

Unmodulated carrier At ±1 MHz offset from carrier At ±2 MHz offset from carrier At ±5 MHz offset from carrier

Parameter

PLL lock time (RX / TX turn-on time)

PLL turn-on time from IDLE mode, crystal oscillator on

Table 8 Frequency synthesizer characteristics

13 Digital Inputs/Outputs

CC2400

Min. Typ. Max. Unit Condition / Note

100

Until within ± 10 kHz

µs

Step size is 1MHz, no calibration. Note: Calibration should be performed for frequency changes > 8 MHz.

Crystal oscillator running.

µs

Calibration time included.

Parameter

Min. Typ. Max. Unit Condition / Note

Logic "0" input voltage

Logic "1" input voltage

Logic "0" output voltage 0

Logic "1" output voltage 2.5

Logic "0" input current

Logic "1" input current

DIO setup time 20 ns TX un-buffered mode, minimum

DIO hold time

Serial interface (SCLK, SI, SO and CSn) timing specification

Signal levels are referred to the

0 0.3*

0.7*

DVDD

NA −1

NA 1

10 ns TX un-buffered mode, minimum

See Table 12 page 22

DVDD

DVDD V

0.4 V Output current −8 mA,

DVDD V Output current 8 mA,

voltage level at the pin DVDD3.3.

3.3 V supply voltage

3.3 V supply voltage Input signal equals GND

µA

Input signal equals DVDD

µA

time DIO must be ready before the positive edge of DCLK

time DIO must be held after the positive edge of DCLK

Table 9 Digital input/output characteristics

SWRS042A Page 12 of 83

14 Pin Assignment

CC2400

VCO_GUARD

AVDD_VCO

AVDD_PRE

AVDD_RF1

GND

RF_P

TXRX_SWITCH

RF_N

GND

AVDD_SW

AVDD_CHP

ATEST1

AVDD_RF2

R_BIAS

AVDD_IF1

ATEST2

QLP48

CC2400

DVDD_ADC

AVDD_ADC

AVDD_IF2

XOSC16_Q1

7x7

DGND_GUARD

XOSC16_Q2

DGUARD

AVDD_XOSC

BT/GR

GIO1

DGND

DSUB_PADS

DSUB_CORE

GIO6

SCLK

CSn

DCLK/FIFO

DIO/PKT

DVDD1.8

DVDD3.3

AGND Exposed die attach pad

Figure 1

CC2400

Top View

Pin no. Pin name Pin type Description

- AGND Ground (analog)

1 VCO_GUARD Power (Analog) Connection of guard ring for VCO shielding

2 AVDD_VCO Power (Analog) Power supply for VCO

3 AVDD_PRE Power (Analog) Power supply for Prescaler

4 AVDD_RF1 Power (Analog) Power supply for RF front-end

5 GND Ground (Analog) Grounded pin for RF shielding

6 RF_P RF I/O Positive RF input/output signal to LNA/from PA in

7 TXRX_SWITCH Power (Analog) Common supply connection for RF front-end. Must be

8 RF_N RF I/O Negative RF input/output signal to LNA/from PA in

9 GND Ground (Analog) Grounded pin for RF shielding

10 AVDD_SW Power (Analog) Power supply connection

Exposed die attach pad. Must be connected to solid ground plane

receive/transmit mode

connected to RF_P and RF_N externally through a DC path.

receive/transmit mode

SWRS042A Page 13 of 83

CC2400

Pin no. Pin name Pin type Description

11 NC --- No Connect

12 NC --- No Connect

13 NC --- No Connect

14 AVDD_RF2 Power (Analog) Power supply for receive and transmit mixers

15 AVDD_IF2 Power (Analog) Power supply for transmit IF chain

16 AVDD_ADC Power (Analog) Power supply connection of ADCs and DACs

17 DVDD_ADC Power (Digital) Power supply for digital part of receive ADCs

18 DGND_GUARD Ground (Digital) Ground connection for digital noise isolation

19 DGUARD Power (Digital) Power supply connection for digital noise isolation

20 BT/GR Digital Input Selection of Built-in-Test or Generic Radio (normal operation).

21 GIO1 Digital I/O General digital I/O pin. Configure as output when not used.

22 DGND Ground (Digital) Ground connection for digital modules

23 DSUB_PADS Ground (Digital) Substrate connection for digital I/O’s

24 DSUB_CORE Ground (Digital) Substrate connection for digital modules

25 DVDD3.3 Power (Digital) Power supply for digital I/O’s

26 DVDD1.8 Power (Digital) Power supply for digital modules

27 RX Digital Input Strobe signal for RX mode. Connect to ground when not used.

28 TX Digital I/O Strobe signal for TX mode. Connect to ground when not used.

29 DIO/PKT Digital I/O Data input/output in un-buffered mode or packet handling

30 DCLK/FIFO Digital Output Data clock output signal in un-buffered mode or FIFO control

31 CSn Digital Input SPI: Chip Select

32 SCLK Digital Input SPI: Serial data clock

33 SI Digital Input SPI: Slave Input

34 SO Digital Output SPI: Slave Output

35 GIO6 Digital Output General digital output pin. See Table 18

36 NC --- No Connect

37 NC --- No Connect

38 NC --- No Connect

39 NC --- No Connect

40 NC --- No Connect

41 AVDD_XOSC Power (Analog) Power supply for 16 MHz crystal oscillator

42 XOSC16_Q2 Analog output 16 MHz crystal oscillator

43 XOSC16_Q1 Analog input 16 MHz crystal oscillator or external clock input

44 AVDD_IF1 Power (Analog) Power supply connection of receive IF chain

45 R_BIAS Analog Output Connection for external precision bias resistor

46 ATEST2 Analog I/O Analog test I/O for prototype and production testing. Leave not

47 ATEST1 Analog I/O Analog test I/O for prototype and production testing. Leave not

48 AVDD_CHP Power (Analog) Power supply for phase detector and charge pump

NOTES:

The exposed die attach pad must be connected to a solid ground plane as this is the main ground connection for the chip.

The digital inputs SCLK, SI and CSn are high-impedance inputs (no internal pull-up) and should have external pullups if not driven. RX and TX should have external pull-down if not driven (to prevent the state machine from being trigged). SO is high-impedance when CSn is high. External pull-up should be used at SO to prevent floating input at the microcontroller.

Connect to ground for normal operation (NOTE: For Chipcon internal use only.)

See Table 18

control signal. Configure as output when not used.

signal. Leave open when not used.

connected when not used.

SWRS042A Page 14 of 83

15 Circuit Description

CC2400

LNA

TX/RX CONTROL



SmartRF

CC2400

Power

Control

On-chip

XOSC

BIAS

16 MHz

A simplified block diagram of shown in Figure 2.

CC2400

features a low-IF receiver. The received RF signal is amplified by the lownoise amplifier (LNA) and down-converted in quadrature (I and Q) to the intermediate frequency (IF). At IF (1 MHz), the I/Q signal is filtered and amplified, and then digitized by the ADCs. Automatic gain control, final channel filtering, demodulation and bit synchronization is performed digitally.

CC2400

outputs (in un-buffered mode only) the digital demodulated data on the DIO pin. A synchronized data clock is then available at the DCLK pin. In buffered mode the demodulated data is sent to a FIFO and is accessible through the SPI interface. RSSI is available in digital format and can be read via the serial interface. The RSSI also features a

Figure 2.

CC2400

simplified block diagram

SWRS042A Page 15 of 83

ADC

AGC CONTROL

FREQ

SYNTH

TX POWER CONTROL

DAC

DIGITAL

DEMODULATOR

- Digital RSSI

- Gain Control

- Image Suppression

- Channel Filtering

- Demodulation

DIGITAL

INTERFACE /

FIFO

CONTROL LOGIC

DIGITAL

MODULATOR

- Data Filtering

- Modulation

- Power Control

DAC

programmable carrier sense indicator with output on either GIO1 or GIO6.

In transmit mode the baseband signal is directly up-converted quadrature (I and Q) and then fed to the power amplifier (PA).

The TX IF signal is frequency shift keyed (FSK). Optionally Gaussian filtering can be used enabling GFSK. The BT of the Gaussian filter is 0.5 for a datarate of 1 Mbps.

The internal T/R switch circuitry simplifies the antenna interface and matching. The antenna connection is differential. The biasing of the PA and LNA is done by connecting TXRX_SWITCH to RF_P and RF_N through an external DC path.

The frequency synthesizer includes a completely on-chip LC VCO and a 90 degrees phase splitter for generating the

TO MICROCONTROLLER

LO_I and LO_Q signals to the downconversion mixers in receive mode and up-conversion mixers in transmit mode. The VCO operates in the frequency range 4800 – 4966 MHz, and the frequency is divided by two when split in I and Q.

A crystal must be connected to XOSC16_Q1 and XOSC16_Q2 and generates the reference frequency for the

CC2400

synthesizer. A PLL lock signal is available via the GIO pins.

The digital baseband includes support for packet handling and data buffering.

The 4-wire SPI serial interface is used for configuration (and data interface in buffered mode). A few digital I/O lines can be configured for use with packet handling strobe and interrupt signals.

SWRS042A Page 16 of 83

16 Application Circuit

Few external components are required for

CC2400

the operation of application circuit is shown in Figure 3. A description of the external components referring to Figure 3 are described in Table 10. The bill of materials (BOM) is given in Table 11.

Good PCB layout is vital for proper operation, please see the section on PCB Layout Recommendations on page 56 for more details.

16.1 Input / output matching

The RF input/output is high impedance and differential. The optimum differential load for the RF port is listed on page 8.

When using an unbalanced antenna like a monopole, a balun should be used in order to get optimum performance. The balun can be implemented using low-cost discrete inductors and capacitors. The balun consists of C61, C62, C71, C81, L61, L62 and L72, and will match the RF input/output to 50 Ω, see Figure 3. L61 and L62 also provide DC biasing of the LNA/PA input/output. L71 is used to isolate the TXRX_SWITCH pin. An internal T/R switch circuit is used to switch between the LNA and the PA. See “Input/output matching” on page 50 for more details.

If a balanced antenna, like a folded dipole, is used, the balun can be omitted. If the antenna also provides a DC path from the TXRX_SWITCH pin to the RF pins, inductors are not needed for DC biasing. The L71 isolation inductor should still be used to avoid antenna reflections. Figure 4 shows a typical application circuit with differential antenna. The dipole has a virtual ground point, hence bias is provided without degradation in antenna performance. Please note that a differential antenna is generally larger than an equivalent single-ended antenna.

. A typical

CC2400

16.3 Crystal

An external crystal with input and output loading capacitors (C421 and C431) is used for the crystal oscillator. See page 49 for details.

16.4 Digita l I/O

The supply voltage for the digital I/O must match the interfacing microcontroller. The digital I/Os of microcontrollers with supply voltages in the range 1.6 – 3.6 V.

16.5 Power supply decoupling and filtering

Proper power supply decoupling must be used for optimum performance. The placement and size of the decoupling capacitors and the power supply filtering are very important to achieve the best performance in an application. Chipcon provides a compact reference design that should be followed very closely.

16.6 Power supply switching

As described in a note in the Absolute Maximum Ratings section, the voltage supply to the chip core should not be switched off separately from the I/O supply voltage.

If it is necessary to switch the core power supply off, for instance to save the power dissipated in the 1.8V regulator, the I/O supply should be turned off as well. This can be done quite easily by running the I/O supply from a microcontroller I/O pin. Current drawn on the I/O supply is just a few milliamps, so an ordinary I/O pin should have no problems in sourcing this current. Power sequencing should be performed so that both supplies are turned on and off simultaneously.

CC2400

can interface

16.2 Bias resistor

The bias resistor R451 is used to set an accurate bias current for the chip.

SWRS042A Page 17 of 83

CC2400

Ref Description

C71 Front-end bias decoupling and match, see page 50 C61 Discrete balun and match, see page 50 C81 Discrete balun and match, see page 50 C62 DC block to antenna and match C421 16MHz crystal load capacitor, see page 49 C431 16MHz crystal load capacitor, see page 49 L61 DC bias and match, see page 50 L62 DC bias and match, see page 50 L71 RF blocking inductor, see page 50 L81 Discrete balun and match, see page 50 R451 Precision resistor for current reference generator XTAL 16MHz crystal, see page 49

Table 10. Overview and description of external components for an unbalanced antenna

(balun implemented with low cost discrete components)

AVDD=1.8V

AVDD

_CHP

C431 C421

R451

R_BIAS

ATEST2

ATEST1

XTAL

AVDD_IF1

XOSC16_Q2

XOSC16_Q1

AVDD_XOSC

Antenna

(50 Ohm)

C62

C61

C71

L81

L62

L61

C81

AVDD=1.8V

L71

VCO_GUARD

AVDD_VCO

AVDD_PRE

AVDD_RF1

GND

RF_P

TXRX_SWITCH

RF_N

GND

AVDD_SW

CC2400

DCLK/FIFO

DGND_GUARD

DVDD_ADC

AVDD_ADC

AVDD_RF2

AVDD_IF2

DGUARD

BT/GR

GIO1

DVDD=1.8V

DGND

DSUB_PADS

DSUB_CORE

DVDD1.8

DVDD3.3

GIO6

SCLK

CSn

DIO/PKT

Figure 3 Typical application circuit with discrete balun for interfacing single-ended

antenna

SPI-bus

Optional digital interface

DVDD=1.8V

DVDD Digital I/O =1.8 / 3.3V

SWRS042A Page 18 of 83

CC2400

AVDD=1.8V

AVDD

_CHP

C431 C421

R451

R_BIAS

ATEST2

ATEST1

XTAL

AVDD_IF1

XOSC16_Q2

XOSC16_Q1

AVDD_XOSC

Folded dipole antenna

L61

AVDD=1.8V

L71

VCO_GUARD

AVDD_VCO

AVDD_PRE

AVDD_RF1

GND

RF_P

TXRX_SWITCH

RF_N

GND

AVDD_SW

CC2400

DCLK/FIFO

DIO/PKT

DGND_GUARD

DVDD_ADC

AVDD_ADC

AVDD_RF2

AVDD_IF2

DGUARD

BT/GR

GIO1

DVDD=1.8V

DSUB_CORE

DSUB_PADS

DGND

DVDD1.8

DVDD3.3

GIO6

SCLK

CSn

Figure 4 Typical application circuit with differential antenna (folded dipole)

Item Single ended output, discrete

Differential antenna

balun

C62 5.6 pF, +/- 0.25pF, NP0, 0402 Not used C61 0.5 pF, +/- 0.25pF, NP0, 0402 Not used C81 0.5 pF, +/- 0.25pF, NP0, 0402 Not used C71 100 nF, 10%, X5R, 0402 100 nF, 10%, X5R, 0402 C421 18 pF, 5%, NP0, 0402 18 pF, 5%, NP0, 0402 C431 18 pF, 5%, NP0, 0402 18 pF, 5%, NP0, 0402 L61 7.5 nH, 5%, Monolithic/multilayer, 0402 27 nH, 5%, Monolithic/multilayer, 0402 L62 5.6 nH, 5%, Monolithic/multilayer, 0402 Not used L71 27 nH, 5%, Monolithic/multilayer, 0402 27 nH, 5%, Monolithic/multilayer, 0402 L81 7.5 nH, 5%, Monolithic/multilayer, 0402 Not used R451

43 kΩ, 1%, 0402 43 kΩ, 1%, 0402

XTAL 16 MHz crystal, 16 pF load (CL) 16 MHz crystal, 16 pF load (CL)

NOTE: Decoupling components are not included.

Table 11. Bill of materials for the appl icati on circuits

SPI-bus

Optional digital interface

DVDD=1.8V

DVDD Digital I/O =1.8 / 3.3V

SWRS042A Page 19 of 83

17 Configuration Overview

CC2400

can be configured to achieve optimum performance for different applications. Through the programmable configuration registers the following key parameters can be programmed:

• Receive / transmit mode

• RF frequency

• RF output power

• FSK frequency deviation

• Power-down / power-up mode

18 Configuration Software

CC2400

• Crystal oscillator power-up / power down

• Data rate and line coding (NRZ, 8B/10B coding)

• Synthesizer lock indicator mode

• Digital RSSI

• FSK / GFSK modulation

• Data buffering

• Packet handling hardware support

Chipcon provides users of software program, SmartRF (Windows interface) that generates all necessary based on the user's selections of various parameters. These hexadecimal numbers will then be the necessary input to the

CC2400

configuration data,

CC2400

Studio

with a

microcontroller for the configuration of

CC2400

Figure 5 shows the user interface of the

CC2400

configuration software.

Figure 5. SmartRF

Studio user interface

SWRS042A Page 20 of 83

19 4-wire Serial Configuration Interface

CC2400

is configured via a simple 4-wire SPI-compatible interface (SI, SO, SCLK and CSn) where interface is also used as data interface in buffered mode (see page 27).

There are 44 16-bit configuration registers, 9 Command Strobe Registers, and one register to access the FIFO. Each register has a 7-bit address. The FIFO (32 bytes) is 8 bits wide. A Read/Write bit indicates a read or a write operation and forms the 8bit address field together with the 7-bit address.

Some registers are termed Command Strobe Registers. By addressing a Command Strobe register internal sequences will be started. These commands can be used to quickly change from RX mode to TX mode, for example.

A full configuration of sending 44 data frames of 24 bits each (7 address bits, R/W bit and 16 data bits). The time needed for a full configuration depend on the SCLK frequency. With a SCLK frequency of 20 MHz the full configuration is done in less than 5 µs. Setting the device in power down mode requires addressing one command strobe register only, and will in this case take less than 0.4 µs. All registers except the strobe registers are also readable.

In each write-cycle, 24 bits are sent on the SI-line. The bit to be sent first is the R/W bit (0 for write, 1 for read). The next seven bits are the address-bits (A6:0). A6 is the MSB (Most Significant Bit) of the address and is sent first. The 16 data-bits are then transferred (D15:0). During address and data transfer the CSn (Chip Select, active low) must be kept low. See Figure 6.

The timing for the programming is shown in Figure 6 with reference to Table 12. The clocking of the data on SI into the is performed on the positive edge of SCLK.

CC2400

is the slave. This

CC2400

requires

CC2400

The data word is loaded into the internal configuration register, when the last bit, D0, of the 16 data bits has been written.

The configuration data will be retained during a programmed power-down mode, but not when the power-supply is turned off. The registers can be programmed in any order.

The configuration registers can also be read by the microcontroller via the same configuration interface. The R/W bit must be set high then the seven address bits are sent.

CC2400

addressed register. SO is used as the data output and must be configured as an input by the microcontroller.

The command strobe register is accessed in the same way as for a write operation, but no data is transferred. That is, only the R/W bit and the seven address bits are written before CSn should be set high.

Figure 7 shows a summary of read and write operations. A register read/write can be terminated after one byte if only the most significant byte is required. A register can also be accessed repeatedly without writing the address again. The buffer FIFO (8 bit wide, 32 bytes) can be written continuously by simply writing new bytes over and over. The internal data pointer is then updated for every written byte. The session is terminated when the CSn is set high.

Please note that a longer hold time, t needed before setting CSn high when accessing the FIFO in buffered mode.

During the transfer of the address, the

CC2400

line containing some important flags. This is shown in Table 13.

to initiate the data read-back,

then returns the data from the

, is

returns a status byte on the SO

SWRS042A Page 21 of 83

SCLK:

CSn:

Write to register:

Read from register:

Read or write a w hole register (16 bit):

Read or write 8 MSB of a register:

Read or write a whole register continuously:

Read or write n bytes from/to RF FIFO:

A6 A5 A4 A3 A2 A0A1 DW15 DW14 DW13 DW12 DW11 DW10 DW9 DW8 DW7 DW6 DW5 DW4 DW3 DW2 DW1 DW0

S7 S6 S5 S4 S3 S2 S0S1

A6 A5 A4 A3 A2 A0A1

Command strobe:

Figure 7. Configuration registers write and read operations via SPI

X X X

DR15 DR14 DR13 DR12 DR11 DR10 DR9 DR8 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0S7 S6 S5 S4 S3 S2 S0S1

Figure 6. SPI timing diagram

CSn:

ADDR

DATA

ADDR DATA

ADDR

ADDR DATA

ADDR

FIFO

DATA

8MSB

byte0

DATA

8LSB

byte1

DATA

CC2400

8MSB

byte2

DATA

8LSB

byte3

DATA

...

8MSB

DATA

...

byte n-2

DATA

DR15

8LSB

byte n-1

Parameter Symbol Min Max Units Conditions

SCLK, clock frequency SCLK low pulse duration SCLK high pulse duration CSn setup time CSn hold time 1 CSn hold time 2

SI setup time t

SI hold time

Rise time t

Fall time t

Note: The set-up- and hold-times refer to 50% of VDD.

SCLK

25 ns The minimum time SCLK must be low.

cl,min

25 ns The minimum time SCLK must be high.

ch,min

20 MHz

25 ns The minimum time CSn must be low before

positive edge of SCLK.

tns 25 ns The minimum time CSn must be held low after the

last negative edge of SCLK.

tps 300 ns In buffered mode: The minimum time CSn must be

held low after the last positive edge of SCLK. This only applies to FIFO accesses.

25 ns The minimum time data on SI must be ready

before the positive edge of SCLK.

thd 25 ns The minimum time data must be held at SI, after

the positive edge of SCLK.

100 ns The maximum rise time for SCLK and CSN

rise

100 ns The maximum fall time for SCLK and CSn

fall

Table 12. SPI timing specification

SWRS042A Page 22 of 83

Bit # Name Description

7 -

6 XOSC16M_STABLE

5 RESERVED

4 SYNC_RECEIVED

3 CRC_OK

2 FS_LOCK

1:0 RESERVED[1:0]

Table 13. Status byte returned during address transfer

Reserved, ignore value

Indicates whether the 16 MHz oscillator is running ('1') or not

Reserved

Indicates whether a sync word has been received or not so far in the RX operation

Indicates whether the next two bytes in the FIFO will make the CRC calculation successful or not:

0: CRC not OK or CRC off

1: CRC OK

Indicates whether the frequency synthesiser is in lock ('1') or not.

Reserved

CC2400

SWRS042A Page 23 of 83

20 Overview of Configurations and Hardware Support

CC2400

The

CC2400

can be configured for different data interfaces, coding schemes and packet handling hardware support.

Data

Data coding Packet handling support

interface

Buffered

(32 byte FIFO accessed through the SPI interface)

Un-buffered

(DIO and DCLK synchronous interface)

NRZ

8/10 code

Manchester

NRZ

Table 14 below gives a summary of the possibilities.

TX:

• Preamble generation

• Sync word insertion

• CRC computation and insertion

RX:

• Sync Word detection

• CRC computation and check

RX:

• Sync Word detection

Manchester

Table 14. Configurations and hardware support

SWRS042A Page 24 of 83

21 Microcontroller Interfa ce and Pin Configuration

CC2400

Used in a typical system, interface to a microcontroller. This microcontroller must be able to:

• Program

and read back status information via the 4-wire SPI-bus configuration interface (SI, SO, SCLK and CSn). In buffered mode the data signal is also transmitted through the SPI-bus

• Interface to the bi-directional

synchronous data signal interface (DIO and DCLK) if un-buffered data transmission is to be used

• Optionally interface to the general

control and status pins (RX, TX, FIFO, PKT, GIO1 and GIO6) if the hardware supported packet handling functions are to be used

• Optionally the microcontroller can

monitor the general I/O pins (GIO1, GIO6) for frequency lock status, carrier sense status, or other status information

• Optionally, the microcontroller can read

back digital RSSI value and other status information via the 4-wire SPI interface

21.1 Configuration interface

The microcontroller interface is shown in Figure 8. The microcontroller uses a minimum of 4 I/O pins for the SPI configuration interface (SI, SO, SCLK and CSn). All other pins are optional. SO should be connected to an input at the microcontroller. SI, SCLK and CSn must be microcontroller outputs.

The microcontroller pins connected to SI, SO and SCLK can be shared with other SPI-interface devices. SO is a high impedance output as long as CSn is not activated (active low).

CSn should have an external pull-up resistor or be set to a high level during power down mode in order to prevent the input from floating. SI and SCLK should be set to a defined level to prevent the input from floating.

CC2400

into different modes

CC2400

will

SWRS042A Page 25 of 83

21.2 Signal interface in un-buffered mode

A bi-directional pin (DIO) is used for data to be transmitted and received. DCLK providing the data timing should be connected to a microcontroller input.

The data is clocked in/out at the positive edge of DCLK.

21.3 General control and status pins

Optionally, in buffered mode, the FIFO pin can be used to interrupt the microcontroller at full/empty FIFO. This pin should then be connected to a microcontroller interrupt pin.

Optionally, using the packet handling support, the PKT pin can be used in buffered mode to interrupt the microcontroller when a sync word is detected (RX mode) and packet is transmitted (TX mode). This pin should then be connected to a microcontroller interrupt pin.

The polarity of FIFO and PKT can be controlled by the INT register (address 0x23).

Optionally, the RX and TX pins can be used to change the operating mode of

CC2400

as an alternative to using the SPI interface strobe commands. These pins should then be connected to microcontroller output pins. If the RX and TX pins are not used, they should be grounded in order to prevent accidental change of mode.

Optionally, the GIO1 and GIO6 can be used to monitor several status signals as selected by the IOCFG register. The GIO6 pin should be connected to a microcontroller input pin. See Table 18 for available signals.

Table 15 gives a summary of the possible pin configurations in the different operation modes.

CC2400

Pin name SCLK SI SO CSn DIO/

Pin number 32 33 34 31 29 30 27 28 21 35 Direction I I O I I/O O I I O O

Buffered mode Buffered mode with Packet handling Un-buffered mode

SCLK SI SO CSn - FIFO (RX) (TX) (GIO1) (GIO6)

SCLK SI SO CSn PKT FIFO (RX) (TX) (GIO1) (GIO6)

SCLK SI SO CSn DIO DCLK (RX) (TX) (GIO1) (GIO6)

PKT

NOTE: Pin functions in parentheses are optional * The use of GIO1 and GIO6 are selected in register IOCFG (address 0x08)

Table 15. Pin configuration

Buffered RF Mode: Unbuffered RF Mode:

CC2400 µC

CSn

SCLK

Data & Control

GIO1 MOSI MISO

SCLK

DCLK/ FIFO

RX TX GIO1* GIO6*

CC2400 µC

SCLK

CSn

Control

GIO1

MOSI MISO SCLK

Other Circuit

CSn

SCLK

DIO/PKT

DCLK/FIFO

Data

Data &

Control

GIO1

Control

MOSI MISO SCLK

GIO2DIO/PKT GIO3 GIO4RX GIO5 GIO6GIO1

GIO2

Full hardware support for packet handling :

CC2400 µC

CSn

SCLK

DCLK/FIFO

GIO6 GIO7

Figure 8. Microcontroller interface

SWRS042A Page 26 of 83

+ 58 hidden pages

TEXAS INSTRUMENTS CC2400 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual