TEXAS INSTRUMENTS CC11x1-Q1 Technical data

CC11x1-Q1

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Low-Power Sub-1-GHz Fractional-N UHF Device Family for Automotive

1 Introduction

1.1 Features

• Qualification in Accordance With AEC-Q100 Grade 1

• Extended Temperature Range Up To 125°C

• Radio-Frequency (RF) Performance – High Sensitivity (–114 dBm at 1.2 kBaud,

315 MHz, 1% Packet Error Rate)

– Low Current Consumption (15.5 mA in

Receive, 1.2 kBaud, 315 MHz)

• Programmable Output Power up to +10 dBm for All Supported Frequencies

• Excellent Receiver Selectivity and Blocking Performance

• Programmable Data Rate From 1.2 kBaud to 250 kBaud

• Frequency Bands: 310 MHz to 348 MHz, 420 MHz to 450 MHz, and 779 MHz to 928 MHz

• Analog Features – 2-FSK, GFSK, and MSK Supported, as Well

as OOK and Flexible ASK Shaping

– Suitable for Frequency-Hopping Systems

Due to a Fast Settling Frequency Synthesizer: 90-µs Settling Time

– Automatic Frequency Compensation (AFC)

Can Align Frequency Synthesizer to Received Center Frequency

– Integrated Analog Temperature Sensor

• Digital Features – Flexible Support for Packet-Oriented

Systems: On-Chip Support for Sync Word Detection, Address Check, Flexible Packet Length, and Automatic CRC Handling

– Efficient SPI Interface: All Registers Can Be

Programmed With One Burst Transfer – Digital RSSI Output – Programmable Channel Filter Bandwidth – Programmable Carrier Sense (CS) Indicator – Programmable Preamble Quality Indicator

(PQI) for Improved Protection Against False

Sync Word Detection in Random Noise

SWRS076B–11-07-22-013 - APRIL 2009–REVISED APRIL 2010

– Support for Automatic Clear Channel

Assessment (CCA) Before Transmitting (for Listen-Before-Talk Systems)

– Support for Per-Package Link Quality

Indication (LQI)

– Optional Automatic Whitening and

Dewhitening of Data

• Low-Power Features – Fast Startup Time: 240 µs From Sleep to

Receive (RX) or Transmit (TX) Mode

– Wake-On-Radio Functionality for Automatic

Low-Power RX Polling

– Separate 64-Byte RX and TX Data FIFOs

(Enables Burst Mode Data Transmission)

• General – Few External Components: Completely

On-Chip Frequency Synthesizer, No External Filters or RF Switch Needed

– Green Package: RoHS Compliant and No

Antimony or Bromine – Small Size QFN 5-mm×5-mm 32-Pin Package – Suited for Systems Compliant With

EN 300 220 (Europe) and FCC CFR Part 15

(US) – Support for Asynchronous and Synchronous

Serial Receive/Transmit Mode for Backward

Compatibility With Existing Radio

Communication Protocols – Designed for Automotive Applications

1.2 Applications

• Ultra-Low-Power Wireless Applications in the 315/433/868/915-MHz ISM/SRD Bands

• Remote Keyless Entry Systems

• Passive Entry/Passive Start Systems

• Vehicle Service Links

• Garage Door Opener

• TPMS Systems

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SmartRF is a registered trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

CC11x1-Q1

SWRS076B–11-07-22-013 - APRIL 2009–REVISED APRIL 2010

1.3 Advantages

• Relay Attack Prevention Through Fast Channel Hopping

• Lowest System Cost Through Highest Integration Level

• Only One Crystal Needed For Key-Fob Designs

• Integrated Protocol Handling, Wake-On-Radio, Clock Output Relax Microcontroller Requirements

1.4 Family Members

All family members are pin-to-pin and software compatible.

UHF Transceivers CC1101IRHBRG4Q1 (–40°C to 85°C)

CC1101TRHBRG4Q1 (–40°C to 105°C) CC1101QRHBRG4Q1 (–40°C to 125°C)

UHF Receivers CC1131IRHBRG4Q1 (–40°C to 85°C)

CC1131TRHBRG4Q1 (–40°C to 105°C) CC1131QRHBRG4Q1 (–40°C to 125°C)

UHF Transmitters CC1151IRHBRG4Q1 (–40°C to 85°C)

CC1151TRHBRG4Q1 (–40°C to 105°C) CC1151QRHBRG4Q1 (–40°C to 125°C)

1.5 Description

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The CC11x1-Q1 device family is designed for very low-power wireless applications. The circuits are mainly intended for the Industrial, Scientific and Medical (ISM) and Short Range Device (SRD) frequency bands at 315 MHz, 433 MHz, 868 MHz, and 915 MHz, but can easily be programmed for operation at other frequencies in the 310-MHz to 348-MHz, 420-MHz to 450-MHz, and 779-MHz to 928-MHz bands.

The devices integrate a highly configurable baseband modem. The modem supports various modulation formats and has a configurable data rate up to 250 kBaud. CC11x1-Q1 family provides extensive hardware support for packet handling, data buffering, burst transmissions, clear channel assessment, link quality indication, and wake-on-radio. The main operating parameters and the 64-byte transmit/receive FIFOs can be controlled via an SPI interface. In a typical system, the devices are used together with a microcontroller and a few additional passive components.

WARNING

This product shall not be used in any of the following products or systems without prior express written permission from Texas Instruments:

(i) implantable cardiac rhythm management systems, including without limitation pacemakers, defibrillators and cardiac resynchronization devices;

(ii) external cardiac rhythm management systems that communicate directly with one or more implantable medical devices; or

(iii) other devices used to monitor or treat cardiac function, including without limitation pressure sensors, biochemical sensors and neurostimulators.

Please contact lpw-medical-approval@list.ti.com if your application might fall within a category described above.

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1.6 Abbreviations

The following abbreviations are used in this data manual.

ACP Adjacent Channel Power MSK Minimum Shift Keying ADC Analog-to-Digital Converter N/A Not Applicable AFC Automatic Frequency Compensation NRZ Non Return to Zero (Coding) AGC Automatic Gain Control OOK On-Off Keying AMR Automatic Meter Reading PA Power Amplifier ASK Amplitude Shift Keying PCB Printed Circuit Board BER Bit Error Rate PD Power Down BT Bandwidth-Time Product PER Packet Error Rate CCA Clear Channel Assessment PLL Phase-Locked Loop CFR Code of Federal Regulations POR Power-On Reset CRC Cyclic Redundancy Check PQI Preamble Quality Indicator CS Carrier Sense PQT Preamble Quality Threshold CW Continuous Wave (Unmodulated Carrier) PTAT Proportional To Absolute Temperature DC Direct Current QLP Quad Leadless Package DVGA Digital Variable Gain Amplifier QPSK Quadrature Phase Shift Keying ESR Equivalent Series Resistance RC Resistor Capacitor FCC Federal Communications Commission RF Radio Frequency FEC Forward Error Correction RSSI Received Signal Strength Indicator FIFO First In, First Out RX Receive, Receive Mode FHSS Frequency Hopping Spread Spectrum SAW Surface Acoustic Wave 2-FSK Binary Frequency Shift Keying SMD Surface Mount Device GFSK Gaussian shaped Frequency Shift Keying SNR Signal-to-Noise Ratio IF Intermediate Frequency SPI Serial Peripheral Interface I/Q In-Phase/Quadrature SRD Short Range Devices ISM Industrial, Scientific, Medical TBD To Be Defined LC Inductor-Capacitor T/R Transmit/Receive LNA Low Noise Amplifier TX Transmit, Transmit Mode LO Local Oscillator UHF Ultra-High Frequency LSB Least-Significant Bit VCO Voltage Controlled Oscillator LQI Link Quality Indicator WOR Wake on Radio, Low power polling MCU Microcontroller Unit XOSC Crystal Oscillator MSB Most-Significant Bit XTAL Crystal

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1 Introduction .............................................. 1 3.7 Microcontroller Interface and Pin Configuration .... 28

1.1 Features .............................................. 1 3.8 Data Rate Programming ............................ 29

1.2 Applications .......................................... 1 3.9 Receiver Channel Filter Bandwidth ................. 29

1.3 Advantages .......................................... 2

1.4 Family Members ..................................... 2

1.5 Description ........................................... 2

1.6 Abbreviations ........................................ 3 3.13 Received Signal Qualifiers and Link Quality

2 Electrical Specifications ............................... 5

2.1 Absolute Maximum Ratings .......................... 5

2.2 Recommended Operating Conditions ............... 5

2.3 General Characteristics .............................. 5

2.4 Current Consumption ................................ 6

2.5 RF Receive Section Characteristics ................. 8

2.6 Selectivity ........................................... 10

2.7 RSSI Section Characteristics ....................... 11

2.8 RF Transmit Section Characteristics ............... 12

2.9 Crystal Oscillator Characteristics ................... 13

2.10 Low-Power RC Oscillator Characteristics .......... 13

2.11 Frequency Synthesizer Characteristics ............ 14

2.12 Analog Temperature Sensor Characteristics ....... 15

2.13 Digital Input/Output DC Characteristics ............ 15

2.14 Power-On Reset Characteristics ................... 15

2.15 SPI Interface Timing ................................ 16

2.16 Typical State Transition Timing ..................... 16

3 Detailed Description .................................. 17

3.1 Terminal Assignments .............................. 17

3.2 Block Diagram ...................................... 19

3.3 Application Circuit .................................. 20

3.4 Configuration Overview ............................. 22

3.5 Configuration Software ............................. 23

3.6 4-Wire Serial Configuration and Data Interface .... 24

3.10 Demodulator, Symbol Synchronizer, and Data

Decision ............................................ 30

3.11 Packet Handling Hardware Support ................ 31

3.12 Modulation Formats ................................ 37

Information .......................................... 38

3.14 Forward Error Correction With Interleaving ........ 43

3.15 Radio Control ....................................... 44

3.16 Data FIFO .......................................... 50

3.17 Frequency Programming ........................... 52

3.18 VCO ................................................ 52

3.19 Voltage Regulators ................................. 53

3.20 Output Power Programming ........................ 53

3.21 Shaping and PA Ramping .......................... 54

3.22 Crystal Oscillator ................................... 55

3.23 External RF Match .................................. 55

3.24 PCB Layout Recommendations .................... 56

3.25 General Purpose / Test Output Control Pins ....... 56

3.26 Asynchronous and Synchronous Serial Operation

...................................................... 59

3.27 System Considerations and Guidelines ............ 60

4 Configuration Registers .............................. 63

4.1 Overview ............................................ 63

4.2 Register Details ..................................... 68

5 Package and Shipping Information ................ 86

5.1 Package Thermal Properties ....................... 86

5.2 Soldering Information ............................... 86

5.3 Carrier Tape and Reel Specifications .............. 86

5.4 Ordering Information ................................ 86

6 References .............................................. 87

Revision History ............................................ 88

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2 Electrical Specifications

2.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

Supply voltage Voltage on any digital pin –0.3 V to (VDD+ 0.3 V) Voltage on the pins RF_P, RF_N, DCOUPL1 and DCOUPL2 –0.3 V to 2 V Voltage ramp-up rate 120 kV/µs

Input RF level 10 dBm T T

Storage temperature range –50°C to 150°C

stg

Solder reflow temperature

solder

ESD Electrostatic discharge rating

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All supply pins must have the same voltage. (3) Maximum voltage is 3.9 V. (4) Measured according to IPC/JEDEC J-STD-020C (5) High-sensitivity UHF devices must be handled with special care to avoid ESD damage. TI is not responsible for damage to this device

caused by external ESD conditions. The following electrostatic discharge (ESD) precautions are recommended:

• Protective outer garments

• Handling in ESD-safeguarded work area

• Transporting in ESD-shielded containers

• Frequent monitoring and testing of all ESD-protection equipment (6) Measured according to JEDEC STD 22, Method A114 (7) Measured according to JEDEC STD 22, C101C (8) Measured according to JEDEC STD 22, Method A115A

(2)

(4)

(5)

(1)

Human-Body Model (HBM)

(6)

Charged-Device Model (CDM) Machine Model (MM)

(8)

–0.3 V to 3.9 V

(3)

260°C

±750 V

(7)

±200 V ±100 V

2.2 Recommended Operating Conditions

MIN MAX UNIT

Supply voltage 1.8 3.6 V

I temperature suffix –40 85

Operating free-air temperature T temperature suffix –40 105 °C

Q temperature suffix –40 125

2.3 General Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

310 348

Frequency range TA= –40°C to 105°C, VDD= 1.8 V to 3.3 V 420 450 MHz

779 928

The data rate step size is determined by the reference frequency – see Data Rate Programming

Data rate

(1)

Shaped MSK (also known as differential offset QPSK) 26 to 250

Device weight 0.0715 g

(1) Optional Manchester encoding halves the data rate.

1.2 250 kBaud

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2.4 Current Consumption

VDD= 1.8 V to 3.3 V, f V. All measurement results obtained using the reference designs.

PARAMETER TEST CONDITIONS T

Current consumption in power-down modes

Current consumption, 315 MHz

Current consumption, 433 MHz

= 26 MHz, All voltages refer to GND (unless otherwise noted). Typical values at TA= 25°C, VDD= 3

REF

Voltage regulator to digital part off, register values –40°C to 105°C 0.7 5 retained, RC oscillator off, all GDO pins programmed to 0X2F (SLEEP state)

Voltage regulator to digital part off, register values –40°C to 105°C 2 6 retained, low-power RC oscillator running (SLEEP state with WOR enabled)

Voltage regulator to digital part off, register values –40°C to 105°C 370 490 retained, XOSC running (SLEEP state with MCSM0.OSC_FORCE_ON set)

Voltage regulator to digital part on, all other modules in power down (XOFF state)

Only voltage regulator to digital part and crystal oscillator running (IDLE state)

Only the frequency synthesizer running (after going from –40°C to 105°C 9 10.5 IDLE until reaching RX or TX states, and frequency calibration states)

Transmit mode

(1)

, 10-dBm output power, Continuous

wave

Transmit mode

(1)

, 0-dBm output power, Continuous wave

(1)

, –5-dBm output power, Continuous

wave Receive mode

(2)

, 1.2 kbps, input 20 dB above sensitivity

limit Receive mode

(2)

, 38.4 kbps, input 20 dB above sensitivity

limit Receive mode

(2)

, 38.4 kbps, input 20 dB above sensitivity –40°C to 105°C 15.5 17 limit, low-current mode (MDMCFG2.DEM_DCFILT_OFF = 1)

Receive mode

(2)

, 250 kbps, input 30 dB above sensitivity limit

Transmit mode

Receive mode

(1)

, 10-dBm output power

(1)

, 0-dBm output power

(1)

, –5-dBm output power

(2)

, 1.2 kbps, input 20 dB above sensitivity limit

Receive mode

(2)

, 38.4 kbps, input 20 dB above sensitivity limit

Receive mode

(2)

, 38.4 kbps, input 20 dB above sensitivity –40°C to 105°C 16.5 18 limit, low-current mode (MDMCFG2.DEM_DCFILT_OFF = 1)

Receive mode

(2)

, 250 kbps, input 30 dB above sensitivity limit

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MIN TYP MAX UNIT

125°C 1.9

125°C 2.5

125°C 400

–40°C to 105°C 160 300

125°C 190

–40°C to 105°C 1.8 2.5

125°C 1.9

125°C 9.1

–40°C to 105°C 29.5 32.9

125°C 28.9

–40°C to 105°C 14.6 16.5

125°C 14.3

–40°C to 105°C 12.2 14

125°C 12.1

–40°C to 105°C 17.5 21

125°C 18.3

–40°C to 105°C 17.5 21

125°C 18.4

125°C 16.5

–40°C to 105°C 17.8 21.5

125°C 18.4

–40°C to 105°C 30.5 33

125°C 30

–40°C to 105°C 15.4 17.5

125°C 15.1

–40°C to 105°C 13.1 14.9

125°C 13

–40°C to 105°C 18.6 22

125°C 19.2

–40°C to 105°C 18.6 22.2

125°C 19.3

125°C 17

–40°C to 105°C 18.6 22.2

125°C 19.3

µA

(1) Transmit parameters valid for CC1101 and CC1151 only (2) Receive parameters valid for CC1101 and CC1131 only

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Current Consumption (continued)

VDD= 1.8 V to 3.3 V, f V. All measurement results obtained using the reference designs.

PARAMETER TEST CONDITIONS T

Current consumption, 868 MHz

Current consumption, 915 MHz

= 26 MHz, All voltages refer to GND (unless otherwise noted). Typical values at TA= 25°C, VDD= 3

REF

Transmit mode

Receive mode

(1)

, 10-dBm output power

(1)

, 0-dBm output power

(1)

, –5-dBm output power

(2)

, 1.2 kbps, input 20 dB above sensitivity limit

Receive mode

(2)

, 38.4 kbps, input 20 dB above sensitivity limit

Receive mode

(2)

, 38.4 kbps, input 20 dB above sensitivity –40°C to 105°C 16 18 limit, low-current mode (MDMCFG2.DEM_DCFILT_OFF = 1)

Receive mode

(2)

, 250 kbps, input 30 dB above sensitivity limit

Transmit mode

Receive mode

(1)

, 10-dBm output power

(1)

, 0-dBm output power

(1)

, –5-dBm output power

(2)

, 1.2 kbps, input 20 dB above sensitivity limit

Receive mode

(2)

, 38.4 kbps, input 20 dB above sensitivity limit

Receive mode

(2)

, 38.4 kbps, input 20 dB above sensitivity –40°C to 105°C 16 18 limit, low-current mode (MDMCFG2.DEM_DCFILT_OFF = 1)

Receive mode

(2)

, 250 kbps, input 30 dB above sensitivity limit

SWRS076B–11-07-22-013 - APRIL 2009–REVISED APRIL 2010

MIN TYP MAX UNIT

–40°C to 105°C 35.5 39

125°C 33.9

–40°C to 105°C 16.4 18.5

125°C 16.2

–40°C to 105°C 15 17.5

125°C 16

–40°C to 105°C 18.5 21.5

125°C 19

–40°C to 105°C 18.4 21.5

125°C 19

125°C 16.5

–40°C to 105°C 18.5 22

125°C 19.1

–40°C to 105°C 34 41

125°C 32

–40°C to 105°C 16 18

125°C 15.8

–40°C to 105°C 14.5 16.5

125°C 15.5

–40°C to 105°C 18.2 21.5

125°C 18.8

–40°C to 105°C 18.3 21.5

125°C 18.8

125°C 16.5

–40°C to 105°C 18.3 21.5

125°C 18.8

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2.5 RF Receive Section Characteristics

VDD= 1.8 V to 3.3 V, Forward error correction disabled, All voltages refer to GND (unless otherwise noted). Typical values at TA= 25°C, VDD= 3 V. Receive parameters valid for CC1101 and CC1131 only.

PARAMETER TEST CONDITIONS T

Digital channel RX User programmable, depend on reference frequency, f filter input bandwidth = 26 MHz 812

1.2 kBaud / 2-FSK, 1% packet error rate, TX deviation 5.2 –40°C to 105°C –114 kHz, 58-kHz RX bandwidth, high-sensitivity mode (MDMCFG2.DEM_DCFILT_OFF = 0)

1.2 kBaud / 2-FSK, 1% packet error rate, TX deviation 5.2 –40°C to 105°C –109 kHz, 58-kHz RX bandwidth, low-current mode (MDMCFG2.DEM_DCFILT_OFF = 1)

Receiver sensitivity, 315 MHz

Receiver sensitivity, 433 MHz

Receiver sensitivity, 868 MHz

38.4 kBaud / 2-FSK, 1% packet error rate, TX deviation –40°C to 105°C –98 –105 19 kHz, 100-kHz RX bandwidth, high-sensitivity mode dBm (MDMCFG2.DEM_DCFILT_OFF = 0)

38.4 kBaud / 2-FSK, 1% packet error rate, TX deviation –40°C to 105°C –96 –103 19 kHz, 100-kHz RX bandwidth, low-current mode (MDMCFG2.DEM_DCFILT_OFF = 1)

1.2 kBaud / ASK, 1% packet error rate, 58-kHz RX bandwidth, high-sensitivity –40°C to 105°C –108 mode(MDMCFG2.DEM_DCFILT_OFF = 0)

1.2 kBaud / 2-FSK, 1% packet error rate, TX deviation 5.2 –40°C to 105°C –114 kHz, 58-kHz RX bandwidth, high-sensitivity mode (MDMCFG2.DEM_DCFILT_OFF = 0)

1.2 kBaud / 2-FSK, 1% packet error rate, TX deviation 5.2 –40°C to 105°C –109 kHz, 58-kHz RX bandwidth, low-current mode (MDMCFG2.DEM_DCFILT_OFF = 1)

38.4 kBaud / 2-FSK, 1% packet error rate, TX deviation –40°C to 105°C –100 –107 19 kHz, 100-kHz RX bandwidth, high-sensitivity mode dBm (MDMCFG2.DEM_DCFILT_OFF = 0)

38.4 kBaud / 2-FSK, 1% packet error rate, TX deviation –40°C to 105°C –98 –104 19 kHz, 100-kHz RX bandwidth, low-current mode (MDMCFG2.DEM_DCFILT_OFF = 1)

1.2 kBaud / ASK, 1% packet error rate, 58-kHz RX bandwidth, high-sensitivity mode. –40°C to 105°C –109 (MDMCFG2.DEM_DCFILT_OFF = 0)

1.2 kBaud / 2-FSK, 1% packet error rate, TX deviation 5.2 –40°C to 105°C –111 kHz, 58-kHz RX bandwidth, high-sensitivity mode (MDMCFG2.DEM_DCFILT_OFF = 0)

1.2 kBaud / 2-FSK, 1% packet error rate, TX deviation 5.2 –40°C to 105°C –107 kHz, 58-kHz RX bandwidth, low-current mode (MDMCFG2.DEM_DCFILT_OFF = 1)

38.4 kBaud / 2-FSK, 1% packet error rate, TX deviation –40°C to 105°C –100 –106 19 kHz, 100-kHz RX bandwidth, high-sensitivity mode (MDMCFG2.DEM_DCFILT_OFF = 0)

38.4 kBaud / 2-FSK, 1% packet error rate, TX deviation –40°C to 105°C –96 –103 19 kHz, 100-kHz RX bandwidth, low-current mode (MDMCFG2.DEM_DCFILT_OFF = 1)

250 kBaud / 2-FSK, 1% packet error rate, TX deviation –40°C to 105°C –90 –98 127 kHz, 540-kHz RX bandwidth, high-sensitivity mode (MDMCFG2.DEM_DCFILT_OFF = 0)

1.2 kBaud / ASK, 1% packet error rate, 58-kHz RX bandwidth, high-sensitivity mode. –40°C to 105°C –108 (MDMCFG2.DEM_DCFILT_OFF = 0)

REF

125°C –113

125°C –105

125°C –101

125°C –100

125°C –113

125°C –105

125°C –102

125°C –101

125°C –109

125°C –102

125°C –101

125°C –99

125°C –95

MIN TYP MAX UNIT

58 to

kHz

dBm

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RF Receive Section Characteristics (continued)

VDD= 1.8 V to 3.3 V, Forward error correction disabled, All voltages refer to GND (unless otherwise noted). Typical values at TA= 25°C, VDD= 3 V. Receive parameters valid for CC1101 and CC1131 only.

PARAMETER TEST CONDITIONS T

1.2 kBaud / 2-FSK, 1% packet error rate, TX deviation 5.2 –40°C to 105°C –111 kHz, 58-kHz RX bandwidth, high-sensitivity mode (MDMCFG2.DEM_DCFILT_OFF = 0)

1.2 kBaud / 2-FSK, 1% packet error rate, TX deviation 5.2 –40°C to 105°C –107 kHz, 58-kHz RX bandwidth, low-current mode (MDMCFG2.DEM_DCFILT_OFF = 1)

Receiver sensitivity, 915 MHz

Receiver adjacent 19 kHz, 100-kHz RX bandwidth, low-current mode channel rejection, (MDMCFG2.DEM_DCFILT_OFF = 1), Channel spacing dB 315 MHz/433 MHz 200 kHz, Desired channel 3 dB above sensitivity level,

Receiver alternate 19 kHz, 100-kHz RX bandwidth, low-current mode channel rejection, (MDMCFG2.DEM_DCFILT_OFF = 1), Channel spacing dB 315 MHz/433 MHz 200 kHz, Desired channel 3 dB above sensitivity level,

Receiver blocking 19 kHz, 100-kHz RX bandwidth, low-current mode ±2 MHz, (MDMCFG2.DEM_DCFILT_OFF = 1), Channel spacing dBm 315 MHz/433 MHz 200 kHz, Desired channel 3 dB above sensitivity level,

Receiver blocking ±10 MHz, dBm 315 MHz/433 MHz

Receiver image 19 kHz, 100-kHz RX bandwidth, low-current mode channel rejection, (MDMCFG2.DEM_DCFILT_OFF = 1), Channel spacing dB 315 MHz/433 MHz 200 kHz, Desired channel 3 dB above sensitivity level,

Receiver adjacent 19 kHz, 100-kHz RX bandwidth, low-current mode channel rejection, (MDMCFG2.DEM_DCFILT_OFF = 1), Channel spacing dB 868 MHz/915 MHz 200 kHz, Desired channel 3 dB above sensitivity level,

Receiver alternate 19 kHz, 100-kHz RX bandwidth, low-current mode channel rejection, (MDMCFG2.DEM_DCFILT_OFF = 1), Channel spacing dB 868 MHz/915 MHz 200 kHz, Desired channel 3 dB above sensitivity level,

Receiver blocking, 868 MHz ± 2 MHz

Receiver blocking, 868 MHz ± 10 MHz

38.4 kBaud / 2-FSK, 1% packet error rate, TX deviation –40°C to 105°C –100 –107 19 kHz, 100-kHz RX bandwidth, high-sensitivity mode dBm (MDMCFG2.DEM_DCFILT_OFF = 0)

38.4 kBaud / 2-FSK, 1% packet error rate, TX deviation –40°C to 105°C –97 –103 19 kHz, 100-kHz RX bandwidth, low-current mode (MDMCFG2.DEM_DCFILT_OFF = 1)

250 kBaud / 2-FSK, 1% packet error rate, TX deviation –40°C to 105°C –98 127 kHz, 540-kHz RX bandwidth, high-sensitivity mode (MDMCFG2.DEM_DCFILT_OFF = 0)

38.4 kBaud / 2-FSK, 1% packet error rate, TX deviation –40°C to 105°C –56

Signal level at ±200 kHz

38.4 kBaud / 2-FSK, 1% packet error rate, TX deviation –40°C to 105°C –55

Signal level at ±400 kHz

38.4 kBaud / 2-FSK, 1% packet error rate, TX deviation –40°C to 105°C –46

Signal level at ±2 MHz

38.4 kBaud / 2-FSK, 1% packet error rate, TX deviation –40°C to 105°C –40 19 kHz, 100-kHz RX bandwidth, low-current mode (MDMCFG2.DEM_DCFILT_OFF = 1), Desired channel 3 dB above sensitivity level, Signal level at ±10 MHz

38.4 kBaud / 2-FSK, 1% packet error rate, TX deviation –40°C to 105°C –65

Signal level at f

38.4 kBaud / 2-FSK, 1% packet error rate, TX deviation –40°C to 105°C –64

Signal level at ±200 kHz

38.4 kBaud / 2-FSK, 1% packet error rate, TX deviation –40°C to 105°C –58

Signal level at ±400 kHz

38.4 kBaud / 2-FSK, 1% packet error rate, TX deviation –40°C to 105°C –44 19 kHz, 100-kHz RX bandwidth, low-current mode (MDMCFG2.DEM_DCFILT_OFF = 1), Wanted signal 3 dB dBm above sensitivity limit, level of unmodulated signal at ±2 MHz is recorded

38.4 kBaud / 2-FSK, 1% packet error rate, TX deviation –40°C to 105°C –38 19 kHz, 100-kHz RX bandwidth, low-current mode (MDMCFG2.DEM_DCFILT_OFF = 1), Wanted signal 3 dB dBm above sensitivity limit, Level of unmodulated signal at ±10 MHz is recorded

Signal

– 608 kHz

125°C –109

125°C –102

125°C –100

125°C –93

125°C –52

125°C –50

125°C –41

125°C –33

125°C –61

125°C –54

125°C –40

125°C –33

MIN TYP MAX UNIT

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-20

-10

-1.0 -0.9 -0.8 -0.7 -0.5 -0.4 -0.2 -0.1 0.1 0.2 0.4 0.6 0.7 0.8 0.9 1. 0

Freque ncy offset [MHz]

Selectivity [dB]

-20.0

-10.0

0.0

10.0

20.0

30.0

40.0

50.0

-1.0 -0.8 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.4 0. 5 0.8 1.0

Freque ncy offset [MHz]

Selectivity [dB]

CC11x1-Q1

SWRS076B–11-07-22-013 - APRIL 2009–REVISED APRIL 2010

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RF Receive Section Characteristics (continued)

VDD= 1.8 V to 3.3 V, Forward error correction disabled, All voltages refer to GND (unless otherwise noted). Typical values at TA= 25°C, VDD= 3 V. Receive parameters valid for CC1101 and CC1131 only.

PARAMETER TEST CONDITIONS T

38.4 kBaud / 2-FSK, 1% packet error rate, TX deviation –40°C to 105°C –60 Receiver image 19 kHz, 100-kHz RX bandwidth, low-current mode channel rejection, (MDMCFG2.DEM_DCFILT_OFF = 1), Channel spacing dB 868 MHz/915 MHz 200 kHz, Desired channel 3 dB above sensitivity level,

Signal level at f

Signal

– 608 kHz

38.4 kBaud / 2-FSK, 1% packet error rate, 25 MHz to Receiver spurious TX deviation 19 kHz, 100-kHz RX 1 GHz emission bandwidth, low-current mode

(MDMCFG2.DEM_DCFILT_OFF = 1)

> 1 GHz –40°C to 105°C –47

125°C –55

–40°C to 105°C –57

MIN TYP MAX UNIT

dBm

2.6 Selectivity

Figure 2-1 to Figure 2-3 show the typical selectivity performance (adjacent and alternate rejection).

Figure 2-1. Typical Selectivity at 1.2-kBaud Data Rate, 868.3 MHz, GFSK, 5.2-kHz Deviation,

IF Frequency 152.3 kHz, Digital Channel Filter Bandwidth 58 kHz

Figure 2-2. Typical Selectivity at 38.4-kBaud Data Rate, 868 MHz, GFSK, 20-kHz Deviation,

IF Frequency 152.3 kHz, Digital Channel Filter Bandwidth 100 kHz

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-20.0

-10.0

0.0

10.0

20.0

30.0

40.0

50.0

-3.00 -2.25 1.50 -1.00 -0.75 0.00 0.75 1. 00 1.50 2.25 3.00

Freque ncy offset [MHz]

Selectivity [dB]

CC11x1-Q1

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SWRS076B–11-07-22-013 - APRIL 2009–REVISED APRIL 2010

Selectivity (continued)

Figure 2-3. Typical Selectivity at 250-kBaud Data Rate, 868 MHz, GFSK,

IF Frequency 304 kHz, Digital Channel Filter Bandwidth 540 kHz

2.7 RSSI Section Characteristics

VDD= 1.8 V to 3.3 V, All voltages refer to GND (unless otherwise noted). Typical values at TA= 25°C, VDD= 3 V. Receive parameters valid for CC1101 and CC1131 only.

PARAMETER TEST CONDITIONS T

RX mode, 100-kHz RX bandwidth, Reference signal –40°C to 105°C –90 CW , –90-dBm power level. Read RSSI status register

RSSI accuracy, 310 MHz dBm

RSSI accuracy, 928 MHz CW , –55-dBm power level. Read RSSI status register dBm

(1) RSSI tolerances can be compensated by an offset correction for each device.

and calculate measured RSSI level. RX mode, 100-kHz RX bandwidth, Reference signal –40°C to 105°C –20

CW , –20-dBm power level. Read RSSI status register and calculate measured RSSI level.

RX mode, 100-kHz RX bandwidth, Reference signal –40°C to 105°C –97 –89 –82 CW , –90-dBm power level. Read RSSI status register and calculate measured RSSI level.

RX mode, 100-kHz RX bandwidth, Reference signal –40°C to 105°C –62 –54 –45 and calculate measured RSSI level.

RX mode, 100-kHz RX bandwidth, Reference signal –40°C to 105°C –27 –19 –10 CW , –20-dBm power level. Read RSSI status register and calculate measured RSSI level.

(1)

MIN TYP MAX UNIT

125°C

125°C –91

125°C –56

125°C –21

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2.8 RF Transmit Section Characteristics

VDD= 1.8 V to 3.3 V, All voltages refer to GND (unless otherwise noted). Typical values at TA= 25°C, VDD= 3 V. Transmit parameters valid for CC1101 and CC1151 only.

PARAMETER TEST CONDITIONS T

Differential load RF port RF_N and RF_P towards the 433 MHz 116 + j41 impedance antenna. For matching follow the

TX output power, setting: 0 dBm 315 MHz CW, Delivered into a 50-Ω load, including matching

TX output power, setting: 0 dBm 433 MHz CW, Delivered into a 50-Ω load, including matching

TX output power, setting: 0 dBm 868 MHz CW, Delivered into a 50-Ω load, including matching

TX output power, setting: 0 dBm 915 MHz CW, Delivered into a 50-Ω load, including matching

Second-order harmonics, 315 MHz

Third-order harmonics, 315 MHz

Load impedance as seen from the

reference design.

38.4 kBaud / GFSK, TX deviation 19 kHz, Output power –40°C to 105°C 9 11 12.5 setting: 10 dBm CW, Delivered into a 50-Ω load, including matching network as outlined

38.4 kBaud / GFSK, TX deviation 19 kHz, Output power –40°C to 105°C –3 –0.5 2.5

network as outlined

38.4 kBaud / GFSK, TX deviation 19 kHz, Output power –40°C to 105°C –8.5 –5.7 –2.5 setting: –5 dBm CW, Delivered into a 50-Ω load, including matching network as outlined

38.4 kBaud / GFSK, TX deviation 19 kHz, Output power –40°C to 105°C 9 10.8 12 setting: 10 dBm CW, Delivered into a 50-Ω load, including matching network as outlined

38.4 kBaud / GFSK, TX deviation 19 kHz, Output power –40°C to 105°C –4.5 –0.2 4

network as outlined

38.4 kBaud / GFSK, TX deviation 19 kHz, Output power –40°C to 105°C –8 –5.3 –2.5 setting: –5 dBm CW, Delivered into a 50-Ω load, including matching network as outlined

38.4 kBaud / GFSK, TX deviation 19 kHz, Output power –40°C to 105°C 8 10.4 12 setting: 10 dBm CW, Delivered into a 50-Ω load, including matching network as outlined

38.4 kBaud / GFSK, TX deviation 19 kHz, Output power –40°C to 105°C –4 –0.5 3.5

network as outlined

38.4 kBaud / GFSK, TX deviation 19 kHz, Output power –40°C to 105°C –9 –5 –2.5 setting: –5 dBm CW, Delivered into a 50-Ω load, including matching network as outlined

38.4 kBaud / GFSK, TX deviation 19 kHz, Output power –40°C to 105°C 7.5 9.6 12 setting: 10 dBm CW, Delivered into a 50-Ω load, including matching network as outlined

38.4 kBaud / GFSK, TX deviation 19 kHz, Output power –40°C to 105°C –4 –0.3 4

network as outlined

38.4 kBaud / GFSK, TX deviation 19 kHz, Output power –40°C to 105°C –8 –5 –1.5 setting: –5 dBm CW, Delivered into a 50-Ω load, including matching network as outlined

Conducted measurement on reference design with CW –40°C to 105°C –50 and maximum output-power settings dBm Note: PA output matching impacts harmonics level

Conducted measurement on reference design with CW –40°C to 105°C –32 and maximum output-power settings dBm Note: PA output matching impacts harmonics level

315 MHz 122 + j31

868 MHz/ 915 MHz

–40°C to 105°C Ω

125°C 10

125°C –1.5

125°C –6.7

125°C 10.3

125°C –1.1

125°C –6.2

125°C 9.7

125°C –1.9

125°C –7

125°C 9.4

125°C –0.9

125°C –5.6

125°C –53

125°C –40

MIN TYP MAX UNIT

87 + j43

dBm

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RF Transmit Section Characteristics (continued)

VDD= 1.8 V to 3.3 V, All voltages refer to GND (unless otherwise noted). Typical values at TA= 25°C, VDD= 3 V. Transmit parameters valid for CC1101 and CC1151 only.

PARAMETER TEST CONDITIONS T

Second-order harmonics, 433 MHz

Third-order harmonics, 433 MHz

Second-order harmonics, 868 MHz

Third-order harmonics, 868 MHz

Second-order harmonics, 915 MHz

Third-order harmonics, 915 MHz

Conducted measurement on reference design with CW –40°C to 105°C –40 and maximum output power settings dBm Note: PA output matching impacts harmonics level

Conducted measurement on reference design with CW –40°C to 105°C –26 and maximum output power settings dBm Note: PA output matching impacts harmonics level

Conducted measurement on reference design with CW –40°C to 105°C –48 and maximum output power settings dBm Note: PA output matching impacts harmonics level

Conducted measurement on reference design with CW –40°C to 105°C –45 and maximum output power settings dBm Note: PA output matching impacts harmonics level

Conducted measurement on reference design with CW –40°C to 105°C –50 and maximum output power settings dBm Note: PA output matching impacts harmonics level

Conducted measurement on reference design with CW –40°C to 105°C –45 and maximum output power settings dBm Note: PA output matching impacts harmonics level

125°C –41

125°C –27

125°C –44

125°C –45

125°C –53

125°C –46

MIN TYP MAX UNIT

2.9 Crystal Oscillator Characteristics

VDD= 1.8 V to 3.3 V, TA= –40°C to 105°C, without forward error correction (unless otherwise noted). All voltages refer to GND. Typical values at TA= 25°C, VDD= 3 V.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Reference frequency MHz

Tolerances RX/TX bandwidth, channel spacing, clock synchronization between RX/TX ±20 ppm

ESR 100 Ω Start-up time 150 µs

Load capacitors Simulated over operating conditions pF

Depending on the UHF operating frequency a 26-MHz or 27-MHz crystal 26 to should be used. 27

The acceptable crystal tolerance depend on the system requirements e.g., units

Measured on the reference design. Parameter depends on the crystal that is used. Time does not include POR of the device

10 to

2.10 Low-Power RC Oscillator Characteristics

VDD= 1.8 V to 3.3 V, TA= –40°C to 105°C, without forward error correction (unless otherwise noted). All voltages refer to GND. Typical values at TA= 25°C, VDD= 3 V.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Nominal, calibrated frequency

Frequency accuracy after calibration

Calibration time 2 ms

After calibration: fRC= f

Time to calibrate RC oscillator, Calibration is continuously done in the background as long as the crystal oscillator is running

/750, f

REF

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= 26 MHz 34 34.666 35 kHz

REF

±0.3 %

CC11x1-Q1

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2.11 Frequency Synthesizer Characteristics

VDD= 1.8 V to 3.3 V, f Typical values at TA= 25°C, VDD= 3 V.

PARAMETER TEST CONDITIONS T

Synthesizer frequency 26-MHz or 27-MHz f resolution is equal for all frequency bands

Phase noise at 50-kHz offset

Phase noise at 100-kHz offset

Phase noise at 200-kHz offset

Phase noise at 500-kHz offset

Phase noise at 1-MHz offset

Synthesizer turn-on time / hop time

Synthesizer turn-on time until arriving the RX, FSTXON, or TX state, –40°C to 105°C 850 µs

Synthesizer RX/TX settling time

Synthesizer TX/RX settling time

Synthesizer calibration Manual triggered calibration before entering or time after leaving the RX/TX state

= 26 MHz, without forward error correction (unless otherwise noted). All voltages refer to GND.

REF

, Frequency resolution

REF

Single sideband noise power in dBc/Hz measured at nominal supply over all frequency –40°C to 105°C –80 dBc/Hz bands at maximum power setting

Single sideband noise power in dBc/Hz measured at nominal supply over all frequency –40°C to 105°C –85 dBc/Hz bands at maximum power setting

Single sideband noise power in dBc/Hz measured at nominal supply over all frequency –40°C to 105°C –92 dBc/Hz bands at maximum power setting

Single sideband noise power in dBc/Hz measured at nominal supply over all frequency –40°C to 105°C –100 dBc/Hz bands at maximum power setting

Time from IDLE state crystal oscillator running until arriving the RX, FSTXON, or TX state, –40°C to 105°C 110 µs RC oscillator calibration disabled

Time from IDLE state crystal oscillator running with synthesizer calibration Time to switch from RX to TX –40°C to 105°C 10 µs

Time to switch from TX to RX –40°C to 105°C 25 µs

–40°C to 105°C f

–40°C to 105°C 18739 f

MIN TYP MAX UNIT

REF/216

REF

cycles

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2.12 Analog Temperature Sensor Characteristics

VDD= 1.8 V to 3.3 V, TA= –40°C to 105°C, without forward error correction (unless otherwise noted). All voltages refer to GND. Typical values at TA= 25°C, VDD= 3 V. Note that it is necessary to write 0xBF to the PTEST register to use the analog temperature sensor in the IDLE state.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

TA= –40°C 0.60 0.70 0.80 TA= 0°C 0.775 TA= 25°C 0.815

Output voltage TA= 70°C 0.880 V

TA= 85°C 0.912 TA= 105°C 0.88 0.96 1.07

TA= 125°C 0.968 Temperature coefficient Fitted from TA= –20°C to 80°C 1.6 mV/ C Error in calculated temperature, From TA= –20°C to 80°C when using 2.44 mV/°C, after 1-point

calibrated calibration at 25°C temperature

±2 °C

2.13 Digital Input/Output DC Characteristics

VDD= 1.8 V to 3.3 V, TA= –40°C to 105°C, without forward error correction (unless otherwise noted). All voltages refer to GND. Typical values at TA= 25°C, VDD= 3 V.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input voltage V

Output voltage V

Input current nA

Logic 0 0 0.7

Logic 1 VDD– 0.7 V

Logic 0 0 0.5

Logic 1 VDD– 0.3 V

Logic 0, Input equals 0 V –50

Logic 1, Input equals VDD 50

2.14 Power-On Reset Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Power-up ramp-up time From 0 V to 3 V 1 ms

(1) When the power supply complies with the requirements shown here, proper power-on-reset functionality is assured. Otherwise, the chip

should be assumed to have unknown state until it transmits an SRES strobe over the SPI interface. See Power-On Startup Sequence for further details.

(1)

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2.15 SPI Interface Timing

MIN TYP MAX UNIT

f t t t t t

SCLK frequency 6 MHz

SCLK

Clock high time 80 ns

Clock low time 80 ns

Setup time, data (negative SCLK edge) to positive edge on SCLK

Hold time, data after positive edge on SCLK 50 ns

Negative edge on SCLK to CS high 50 ns

(1)

80 ns

(1) tsdapplies between address and data bytes, and between data bytes.

2.16 Typical State Transition Timing

PARAMETER

IDLE to RX, no calibration 2298 88.4 µs IDLE to RX, with calibration ~21037 809 µs IDLE to TX/FSTXON, no calibration 2298 88.4 µs IDLE to TX/FSTXON, with calibration ~21037 809 µs TX to RX switch 560 21.5 µs RX to TX switch 250 9.6 µs RX or TX to IDLE, no calibration 2 0.1 µs RX or TX to IDLE, with calibration ~18739 721 µs Manual calibration ~18739 721 µs

XOSC 26-MHz

PERIODS CRYSTAL

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2 3

5 6

SI AGND_GUARD AVDD_GUARD RBIAS GND AVDD_CHP NC

RHB PACKAGE

(TOP VIEW)

DCOUPL2

GDO0 (ATEST)

XOSC_Q1

AVDD_IF

XOSC_Q2

GND

DVDD2

DVDD1

GND

GDO2

TEST_MODE

SO (GDO1)

SCLK

DCOUPL1

23 22

20 19

AVDD_RF1

AVDD_RF3

GND

RF_N

RF_P

AVDD_RF2

GND

262728293031

NC – No internal connection

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3 Detailed Description

3.1 Terminal Assignments

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Table 3-1. Terminal Functions

TERMINAL

NO. NAME

1 GND Ground (Analog) Analog ground connection 2 DCOUPL2 1.6-V to 2-V digital power supply input for decoupling

3 GDO0 (ATEST) Digital I/O

4 CS Digital Input Serial configuration interface, chip select 5 XOSC_Q1 Analog I/O Crystal oscillator pin 1, or external clock input 6 AVDD_IF Power (Analog) 1.8-V to 3.6-V analog power supply connection 7 XOSC_Q2 Analog I/O Crystal oscillator pin 2 8 GND Ground (Analog) Analog ground connection

9 AVDD_RF1 Power (Analog) 1.8-V to 3.6-V analog power supply connection 10 GND Ground (Analog) Analog ground connection 11 AVDD_RF2 Power (Analog) 1.8-V to 3.6-V analog power supply connection

12 RF_P RF I/O

13 RF_N RF I/O 14 GND Ground (Analog) Analog ground connection

15 AVDD_RF3 Power (Analog) 1.8-V to 3.6-V analog power supply connection 16 NC Not connected 17 NC Not connected 18 AVDD_CHP Power (Analog) 1.8-V to 3.6-V analog power supply connection 19 GND Ground (Analog) Analog ground connection 20 RBIAS Analog I/O External precision bias resistor for reference current 21 AVDD_GUARD Power (Digital) Power supply connection for digital noise isolation 22 AGND_GUARD Ground (Digital) Ground connection for digital noise isolation 23 SI Digital Input Serial configuration interface, data input 24 NC Not connected 25 SCLK Digital Input Serial configuration interface, clock input 26 SO (GDO1) Digital Output Serial configuration interface, data output. Optional general output pin when CS is high. 27 TEST_MODE Digital Input GND enables and NC disables on-chip data scrambling. Internal pullup resistor.

28 GDO2 Digital Output

29 GND Ground (Analog) Analog ground connection 30 DVDD1 31 DVDD2

32 DCOUPL1 NOTE: This pin is intended to supply only the CC11x1-Q1 chip. It cannot be used to provide

TYPE DESCRIPTION

Power Input

(Digital )

Digital output pin for general use:

• Test signals

• FIFO status signals

• Clear Channel Indicator

• Clock output, down-divided from XOSC

• Serial output RX data

• Serial input TX data Also used as analog test I/O for prototype and production testing.

Positive RF input signal to LNA in receive mode. Positive RF output signal from PA in transmit mode

Negative RF input signal to LNA in receive mode. Negative RF output signal from PA in transmit mode

Digital output pin for general use:

• Test signals

• FIFO status signals

• Clear channel indicator

• Clock output, down-divided from XOSC

• Serial output RX data

Power (Digital) 1.8-V to 3.6-V digital power supply for digital I/Os and for digital core voltage regulator

Output regulator

digital core

1.6-V to 1.8-V digital power supply output for digital core / decoupling. supply voltage to other devices.

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SCLK SO (GDO1)

CS GDO0 (ATEST)

GDO2

Radio Control

ADC

Frequency Synthesizer

XOSCBIASRC OSC

RBIAS

XOSC_Q1

XOSC_Q2

RF_P

RF_N

LNA

Modulator

Demodulator

FEC / Interleaver

Packet Handler

TXFIFO

RXFIFO

Digital Interface to MCU

CC11x1-Q1

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3.2 Block Diagram

A simplified block diagram of CC11x1-Q1 is shown in Figure 3-1. The CC11x1-Q1 devices feature a low intermediate frequency (IF) receiver. The received radio frequency (RF) signal is amplified by the low-noise amplifier (LNA) and down-converted in a quadrature (I and Q) to the IF. At IF, the I/Q signals are digitized by the analog-to-digital converters (ADCs). Automatic gain control (AGC), fine channel filtering, and demodulation bit/packet synchronization is performed digitally.

The transmitter part of CC11x1-Q1 is based on direct synthesis of the RF frequency. The frequency synthesizer includes a completely on-chip LC voltage-controlled oscillator (VCO) and a 90° phase shifter for generating the I and Q signals, and it is also used for the down-conversion mixers in receive mode. A crystal must be connected to XOSC_Q1 and XOSC_Q2. The crystal oscillator generates the reference frequency for the synthesizer as well as the clocks for the ADC and the digital part.

A 4-wire SPI serial interface is used for the register configuration and data buffer access. The digital base band modem includes support for channel configuration, packet handling, Forward Error Correction and data buffering.

In the CC1131-Q1 devices, the TX path is not available. In the CC1151-Q1 devices, the RX path is not available.

SWRS076B–11-07-22-013 - APRIL 2009–REVISED APRIL 2010

Figure 3-1. Simplified Block Diagram

CC11x1-Q1 features a low intermediate frequency (IF) receiver. The received RF signal is amplified by the low-noise amplifier (LNA) and down-converted in quadrature (I and Q) to the IF. At IF, the I/Q signals are digitized by the ADCs. Automatic gain control (AGC), fine channel filtering and demodulation bit/packet synchronization are performed digitally.

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synthesizer includes a completely on-chip LC VCO and a 90° phase shifter for generating the I and Q LO signals to the down-conversion mixers in receive mode.

A crystal is to be connected to XOSC_Q1 and XOSC_Q2. The crystal oscillator generates the reference

The transmitter part of CC11x1-Q1 is based on direct synthesis of the RF frequency. The frequency

frequency for the synthesizer, as well as clocks for the ADC and the digital part. A 4-wire SPI serial interface is used for configuration and data buffer access. The digital baseband includes support for channel configuration, packet handling, and data buffering.

CC11x1-Q1

SWRS076B–11-07-22-013 - APRIL 2009–REVISED APRIL 2010

3.3 Application Circuit

Only a few external components are required for using the CC11x1-Q1. The recommended application circuits are shown in Figure 3-2 and Figure 3-3. Typical values for the external components are given in

Table 3-2.

Bias Resistor

The bias resistor R171 is used to set an accurate bias current.

Balun and RF Matching

The components between the RF_N/RF_P pins and the point where the two signals are joined together (C131, C122, L121, and L131 for the 315/433-MHz reference design [5], or L101, L111, C111, L121, C131, C122, and L131 for the 868/915-MHz reference design [6]) form a balun that converts the differential RF signal on CC11x1-Q1 to a single-ended RF signal. C125 is needed for dc blocking. Together with an appropriate LC network, the balun components also transform the impedance to match a 50-Ω antenna or cable. Suggested values for 315 MHz, 433 MHz, and 868/915 MHz are listed in

Table 3-2.

Crystal

The reference oscillator uses an external 26-MHz or 27-MHz crystal with two loading capacitors (C81 and C101). See Section 3.22 for details.

Additional Filtering

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Additional external components (e.g., an RF SAW filter) may be used to improve the performance in specific applications.

Power Supply Decoupling

The power supply must be properly decoupled close to the supply pins. A short and proper GND connection is also essential for the functionality of the device.

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VDD

R171

C121

L121

C122

L131

C131

C81 C101

XTAL

C41

NC 16

AVDD_RF1 9

RF_P 12

RF_N 13

AVDD_RF3 15

7 XOSC_Q2

6 AVDD_IF

5 XOSC_Q1

4 CS

3 GDO0(ATEST)

29 GND

28 GDO2

27 NC/GND

26 SO (GDO1)

25 SCLK

NC 24

NC 17

RBIAS 20

AVDD_GUARD 21

SI 23

L122

C123

L123

C124

C125

Antenna

(50 )W

SCLK

SO (GDO1)

GDO2

GDO0

32 DCOUPL1

31 DVDD2

30 DVDD1

1 GND

2 DCOUPL2

8 GND

GND 10

AVDD_RF2 11

GND 14

AVDD_CHP 18

GND 19

AGND_GUARD 22

C21

C51

C31

CC11x1-Q1

C131

C125

Antenna

(50 )W

L122

L123

C123

L111 L131

C111

L101

C122

L121

C121

VDD

R171

C81 C101

XTAL

NC 16

AVDD_RF1 9

RF_P 12

RF_N 13

AVDD_RF3 15

7 XOSC_Q2

6 AVDD_IF

5 XOSC_Q1

4 CS

3 GDO0(ATEST)

29 GND

28 GDO2

27 NC/GND

26 SO (GDO1)

25 SCLK

NC 24

NC 17

RBIAS 20

AVDD_GUARD 21

SI 23

SCLK

SO (GDO1)

GDO2

GDO0

32 DCOUPL1

31 DVDD2

30 DVDD1

1 GND

2 DCOUPL2

8 GND

GND 10

AVDD_RF2 11

GND 14

AVDD_CHP 18

GND 19

AGND_GUARD 22

C21

C31

C51

CC11x1-Q1

C41

C126

L125

See Note A

CC11x1-Q1

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Figure 3-2. Typical Application Circuit for 315 MHz/433 MHz

Figure 3-3. Typical Application Circuit for 868 MHz/915 MHz

A. C126 and L125 may be added to build an optional filter to reduce emission at 699 MHz.

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CC11x1-Q1

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Table 3-2. Bill of Materials for the Application Circuit

COMPONENT VALUE AT 315 MHz VALUE AT 433 MHz VALUE AT 868 MHz VALUE AT 915 MHz

C21 100 nF ± 10%, 0402 X5R C31 100 nF ± 10%, 0402 X5R C41 100 nF ± 10%, 0402 X5R C51 100 nF ± 10%, 0402 X5R

C81 27 pF ± 5%, 0402 NP0 C101 27 pF ± 5%, 0402 NP0 C111 — — 1 pF ± 0.25 pF, 0402 NP0 1 pF ± 0.25 pF, 0402 NP0 C121 220 pF ± 5%, 0402 NP0 220 pF ± 5%, 0402 NP0 100 pF ± 5%, 0402 NP0 100 pF ± 5%, 0402 NP0 C122 6.8 pF ± 0.5 pF, 0402 NP0 3.9 pF ± 0.25 pF, 0402 NP0 1.5 pF ± 0.25 pF, 0402 NP0 1.5 pF ± 0.25 pF, 0402 NP0 C123 12 pF ± 5%, 0402 NP0 8.2 pF ± 0.5 pF, 0402 NP0 3.3 pF ± 0.25 pF, 0402 NP0 3.3 pF ± 0.25 pF, 0402 NP0 C124 6.8 pF ± 0.5 pF, 0402 NP0 5.6 pF ± 0.5 pF, 0402 NP0 — — C125 220 pF ± 5%, 0402 NP0 220 pF ± 5%, 0402 NP0 100 pF ± 5%, 0402 NP0 100 pF ± 5%, 0402 NP0 C126 — — 47 pF ± 5%, 0402 NP0 — C131 6.8 pF ± 0.5 pF, 0402 NP0 3.9 pF ± 0.25 pF, 0402 NP0 1.5 pF ± 0.25 pF, 0402 NP0 1.5 pF ± 0.25 pF, 0402 NP0

L101 — —

L111 — —

L121

L122

L123

L125 — — —

L131 R171 56 kΩ ± 1%, 0402

XTAL 26 MHz 27 MHz 27 MHz 26 MHz

33 nH ± 5%, 0402 / muRata 27 nH ± 5%, 0402 / muRata 18 nH ± 5%, 0402 / muRata 18 nH ± 5%, 0402 / muRata LQW15A LQW15A LQW15A LQW15A

18 nH ± 5%, 0402 / muRata 22 nH ± 5%, 0402 / muRata 12 nH ± 5%, 0402 / muRata 12 nH ± 5%, 0402 / muRata LQW15A LQW15A LQW14A LQW14A

33 nH ± 5%, 0402 / muRata 27 nH ± 5%, 0402 / muRata 12 nH ± 5%, 0402 / muRata 12 nH ± 5%, 0402 / muRata LQW15A LQW15A LQW15A LQW15A

33 nH ± 5%, 0402 / muRata 27 nH ± 5%, 0402 / muRata 18 nH ± 5%, 0402 / muRata 18 nH ± 5%, 0402 / muRata LQW15A LQW15A LQW15A LQW15A

12 nH ± 5%, 0402 / muRata 12 nH ± 5%, 0402 / muRata LQW15A LQW15A

12 nH ± 5%, 0402 / muRata 12 nH ± 5%, 0402 / muRata LQW14A LQW15A

3.3 nH ± 5%, 0402 / muRata LQW15A

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3.4 Configuration Overview

CC11x1-Q1 can be configured to achieve optimum performance for many different applications. Configuration is done using the SPI interface. The following key parameters can be programmed:

<br/>

• Power-down / power-up mode • RF output power

• Crystal oscillator power up / power down • Data buffering with separate 64-byte

• Receive / transmit mode

• RF channel selection

• Data rate

• Modulation format

• RX channel filter bandwidth

Details of each configuration register are in Section 4.

Figure 3-4 shows a simplified state diagram that explains the main CC11x1-Q1 states, together with

typical usage and current consumption. For detailed information on controlling the CC11x1-Q1 state machine, and a complete state diagram, see Section 3.15.

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receive and transmit FIFOs

• Packet radio hardware support

• Forward error correction (FEC) with interleaving

• Data whitening

• Wake-on-radio (WOR)

Transmit mode Receive mode

IDLE

RX FIFO

overflow

TX FIFO

underflow

Frequency

synthesizer on

SFSTXON

SRXor wake-on-radio(WOR)

STX

STXor RXOFF_MODE=10

RXOFF_MODE = 00

SFTX

SRX or TXOFF_MODE = 11

SIDLE

SCAL

SFRX

IDLE

TXOFF_MODE =00

SFSTXONorRXOFF_MODE= 01

SRX or STX or SFSTXON or wake-on-radio(WOR)

SPWDorwake-on-radio(WOR)

Crystal

oscillator off

SXOFF

CSn=0

CSn= 0

TXOFF_MODE= 01

Frequency

synthesizer startup,

optional calibration,

settling

Optional freq.

synth. calibration

All register values are retained. Typ current consumption 160 µA

Frequency synthesize r is turned on, can optionally be calibrated, and then settles to the correct frequency. Transitional state. Typ current consumption: 9 mA

Frequency synthesizer is on, ready to start transmitting. Transmission starts very quickly after receiving the STX command strobe. Typ current consumption: 9 mA

Typ current consumption:

12.2 mA at -5 dBm output

14.6 mA at 0 dBm output

29.5 mA at +10 dBm output

Typ current consumption: 15.5 mA

Optional transitional state. Typ current consumption: 8 mA

In FIFO-based modes, transmission is turned off and this state entered if the TX FIFO becomes empty in the middle of a packet. Typ current consumption: 1.8 mA

In FIFO-based modes, reception is turned off and this state entered if the RX FIFO overflows. Typ current consumption: 1.8 mA

Default state when the radio is not receiving or transmitting. Typ current consumption: 1.8 mA

Used for calibrating frequency synthesizer up front (entering receive or transmit mode can then be done more quickly). Transitional state. Typ current consumption: 9 mA

Manual

frequency

synthesizer

calibration

Lowest power mode. Most register values are retained. Typ current consumption: 700 nA (2 µA when wake-on-radio (WOR) is enabled)

Sleep

CC11x1-Q1

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SWRS076B–11-07-22-013 - APRIL 2009–REVISED APRIL 2010

Figure 3-4. Simplified State Diagram, With Typical Current Consumption at 1.2-kBaud Data Rate and

3.5 Configuration Software

CC11x1-Q1 can be configured using the SmartRF®Studio software. The SmartRF Studio software is highly recommended for obtaining optimum register settings and for evaluating performance and functionality. A screenshot of the SmartRF Studio user interface for CC11x1-Q1 is shown in Figure 3-5.

After chip reset, all the registers have default values as shown in Section 4. The optimum register setting might differ from the default value. Therefore, after a reset, all registers that are different from the default value need to be programmed through the SPI interface. For the CC11x1-Q1 device, the settings of the CC1101 are valid.

MDMCFG2.DEM_DCFILT_OFF = 1 (Current Optimized), Frequency Band = 315 MHz

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Figure 3-5. SmartRF Studio User Interface

3.6 4-Wire Serial Configuration and Data Interface

CC11x1-Q1 is configured via a simple 4-wire SPI-compatible interface (SI, SO, SCLK, and CS) where CC11x1-Q1 is the slave. This interface is also used to read and write buffered data. All transfers on the SPI interface are done most significant bit first.

All transactions on the SPI interface start with a header byte containing a R/W bit, a burst access bit (B), and a 6-bit address (A5to A0).

The CS pin must be kept low during transfers on the SPI bus. If CS goes high during the transfer of a header byte or during read/write from/to a register, the transfer is canceled. The timing for the address and data transfer on the SPI interface is shown in Figure 3-6 with reference to Section 2.15.

When CS is pulled low, the MCU must wait until CC11x1-Q1 SO pin goes low before starting to transfer the header byte. This indicates that the crystal is running. Unless the chip was in the SLEEP or XOFF states, the SO pin goes low immediately after taking CS low.

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Note: See Section 2.15 for SPI interface timing specifications.

Figure 3-6. Configuration Registers Write and Read Operations

3.6.1 Chip Status Byte

When the header byte, data byte, or command strobe is sent on the SPI interface, the chip status byte is sent by the CC11x1-Q1 on the SO pin. The status byte contains key status signals, useful for the MCU. The first bit, s7, is the CHIP_RDYn signal. This signal must go low before the first positive edge of SCLK. The CHIP_RDYn signal indicates that the crystal is running.

SWRS076B–11-07-22-013 - APRIL 2009–REVISED APRIL 2010

The STATE value comprises bits 6, 5, and 4. This value reflects the state of the chip. The XOSC and power to the digital core is on in the IDLE state, but all other modules are in power down. The frequency and channel configuration should be updated only when the chip is in this state. The RX state is active when the chip is in receive mode. Likewise, TX is active when the chip is transmitting.

The last four bits (3:0) in the status byte contain FIFO_BYTES_AVAILABLE. For read operations (the R/W bit in the header byte is set to 1), the FIFO_BYTES_AVAILABLE field contains the number of bytes available for reading from the RX FIFO. For write operations (the R/W bit in the header byte is set to 0), the FIFO_BYTES_AVAILABLE field contains the number of bytes that can be written to the TX FIFO. When FIFO_BYTES_AVAILABLE = 15, 15 or more bytes are available/free.

Table 3-3 gives a status byte summary.

Table 3-3. Status Byte Summary

BITS NAME DESCRIPTION

7 CHIP_RDYn Stays high until power and crystal have stabilized. Should always be low when using the SPI

06:04 STATE[2:0] Indicates the current main state machine mode

03:00 FIFO_BYTES_AVAILABLE[3:0] The number of bytes available in the RX FIFO or free bytes in the TX FIFO

interface.

Value State Description

0 IDLE (Also reported for some transitional states instead of

1 RX Receive mode 10 TX Transmit mode 11 FSTXON Fast TX ready

100 CALIBRATE Frequency synthesizer calibration is running 101 SETTLING PLL is settling

110 RXFIFO_OVERFLOW 111 TXFIFO_UNDERFLOW TX FIFO has underflowed. Acknowledge with SFTX.

IDLE state SETTLING or CALIBRATE)

RX FIFO has overflowed. Read out any useful data, then flush the FIFO with SFRX.

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SI Header

SRES

Header

Addr

Data

CSn

CC11x1-Q1

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3.6.2 Register Access

The configuration registers on the CC11x1-Q1 are located on SPI addresses from 0x00 to 0x2E. Table 4-2 lists all configuration registers. SmartRF Studio should be used to generate optimum register settings. The detailed description of each register is found in Section 4.2. All configuration registers can be both written to and read. The R/W bit controls if the register should be written to or read. When writing to registers, the status byte is sent on the SO pin each time a header byte or data byte is transmitted on the SI pin. When reading from registers, the status byte is sent on the SO pin each time a header byte is transmitted on the SI pin.

Registers with consecutive addresses can be accessed efficiently by setting the burst bit (B) in the header byte. The address bits (A5 to A0) set the start address in an internal address counter. This counter is incremented by one each new byte (every 8 clock pulses). The burst access is either a read or a write access and must be terminated by setting CS high.

For register addresses in the range 0x30 to 0x3D, the burst bit is used to select between status registers, burst bit is one, and command strobes, burst bit is zero (see 10.4 below). Because of this, burst access is not available for status registers and they must be accessed one at a time. The status registers can only be read.

3.6.3 SPI Read

When reading register fields over the SPI interface while the register fields are updated by the radio hardware (e.g., MARCSTATE or TXBYTES), there is a small, but finite, probability that a single read from the register is being corrupt. As an example, the probability of any single read from TXBYTES being corrupt, assuming the maximum data rate is used, is approximately 80 ppm. See the CC1101 errata notes (SWRZ020) for more details.

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3.6.4 Command Strobes

Command strobes may be viewed as single byte instructions to CC11x1-Q1. By addressing a command strobe register, internal sequences are started. These commands are used to disable the crystal oscillator, enable receive mode, enable wake-on-radio etc. The 13 command strobes are listed in Table 4-1.

The command strobe registers are accessed by transferring a single header byte (no data is being transferred). That is, only the R/W bit, the burst access bit (set to 0), and the six address bits (in the range 0x30 through 0x3D) are written. The R/W bit can be either one or zero and determines how the FIFO_BYTES_AVAILABLE field in the status byte should be interpreted.

When writing command strobes, the status byte is sent on the SO pin. A command strobe may be followed by any other SPI access without pulling CS high. However, if an

SRES strobe is being issued, wait for SO to go low again before the next header byte is issued, as shown in Figure 3-7. The command strobes are executed immediately, with the exception of the SPWD and the SXOFF strobes that are executed when CS goes high.

3.6.5 FIFO Access

Figure 3-7. SRES Command Strobe

The 64-byte TX FIFO and the 64-byte RX FIFO are accessed through the 0x3F address. When the R/W bit is zero, the TX FIFO is accessed, and the RX FIFO is accessed when the R/W bit is one.

The TX FIFO is write-only, while the RX FIFO is read-only.

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The burst bit is used to determine if the FIFO access is a single byte access or a burst access. The single byte access method expects a header byte with the burst bit set to zero and one data byte. After the data byte a new header byte is expected; hence, CS can remain low. The burst access method expects one header byte and then consecutive data bytes until terminating the access by setting CS high.

The following header bytes access the FIFOs:

• 0x3F: Single byte access to TX FIFO

• 0x7F: Burst access to TX FIFO

• 0xBF: Single byte access to RX FIFO

• 0xFF: Burst access to RX FIFO When writing to the TX FIFO, the status byte (see Section 3.6.1) is output for each new data byte on SO,

as shown in Figure 3-6. This status byte can be used to detect TX FIFO underflow while writing data to the TX FIFO. Note that the status byte contains the number of bytes free before writing the byte in progress to the TX FIFO. When the last byte that fits in the TX FIFO is transmitted on SI, the status byte received concurrently on SO indicates that one byte is free in the TX FIFO.

The TX FIFO may be flushed by issuing a SFTX command strobe. Similarly, a SFRX command strobe flushes the RX FIFO. A SFTX or SFRX command strobe can only be issued in the IDLE, TXFIFO_UNDERFLOW, or RXFIFO_OVERFLOW states. Both FIFOs are flushed when going to the SLEEP state.

Figure 3-8 gives a brief overview of different register access types possible.

SWRS076B–11-07-22-013 - APRIL 2009–REVISED APRIL 2010

Figure 3-8. Register Access Types

3.6.6 PATABLE Access

The 0x3E address is used to access the PATABLE, which is used for selecting PA power control settings. The SPI expects up to eight data bytes after receiving the address. By programming the PATABLE, controlled PA power ramp-up and ramp-down can be achieved, as well as ASK modulation shaping for reduced bandwidth. See SmartRF Studio for recommended shaping / PA ramping sequences.

See Section 3.20 for details on output power programming. The PATABLE is an 8-byte table that defines the PA control settings to use for each of the eight PA power

values (selected by the 3-bit value FREND0.PA_POWER). The table is written and read from the lowest setting (0) to the highest (7), one byte at a time. An index counter is used to control the access to the table. This counter is incremented each time a byte is read or written to the table, and set to the lowest index when CS is high. When the highest value is reached the counter restarts at zero.

The access to the PATABLE is either single byte or burst access depending on the burst bit. When using burst access the index counter counts up; when reaching 7 the counter restarts at 0. The R/W bit controls whether the access is a read or a write access.

If one byte is written to the PATABLE and this value is to be read out then CS must be set high before the read access to set the index counter back to zero.

Note that the content of the PATABLE is lost when entering the SLEEP state, except for the first byte (index 0).

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3.7 Microcontroller Interface and Pin Configuration

In a typical system, CC11x1-Q1 interfaces to a microcontroller. This microcontroller must be able to:

• Program CC11x1-Q1 into different modes

• Read and write buffered data

• Read back status information via the 4-wire SPI-bus configuration interface (SI, SO, SCLK and CS).

3.7.1 Configuration Interface

The microcontroller uses four I/O pins for the SPI configuration interface (SI, SO, SCLK and CS). The SPI is described in Section 3.6.

3.7.2 General Control and Status Pins

The CC11x1-Q1 has two dedicated configurable pins (GDO0 and GDO2) and one shared pin (GDO1) that can output internal status information useful for control software. These pins can be used to generate interrupts on the MCU. See Section 3.25 for more details on the signals that can be programmed. GDO1 is shared with the SO pin in the SPI interface. The default setting for GDO1/SO is 3-state output. By selecting any other of the programming options, the GDO1/SO pin becomes a generic pin. When CS is low, the pin functions as a normal SO pin.

In the synchronous and asynchronous serial modes, the GDO0 pin is used as a serial TX data input pin while in transmit mode.

The GDO0 pin can also be used for an on-chip analog temperature sensor. By measuring the voltage on the GDO0 pin with an external ADC, the temperature can be calculated. Specifications for the temperature sensor are found in Section 2.12.

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With default PTEST register setting (0x7F) the temperature sensor output is available only when the frequency synthesizer is enabled (e.g., the MANCAL, FSTXON, RX, and TX states). It is necessary to write 0xBF to the PTEST register to use the analog temperature sensor in the IDLE state. Before leaving the IDLE state, the PTEST register should be restored to its default value (0x7F).

3.7.3 Optional Radio-Control Feature

The CC11x1-Q1 has an optional way of controlling the radio by reusing SI, SCLK, and CS from the SPI interface. This allows simple three-pin control of the major states of the radio: SLEEP, IDLE, RX, and TX.

This optional functionality is enabled with the MCSM0.PIN_CTRL_EN configuration bit. State changes are commanded as follows: When CS is high, the SI and SCLK is set to the desired state

according to Table 3-4. When CS goes low, the state of SI and SCLK is latched and a command strobe is generated internally according to the pin configuration. It is only possible to change state with this functionality. That means that, for instance, RX is not restarted if SI and SCLK are set to RX and CS toggles. When CS is low, the SI and SCLK has normal SPI functionality.

All pin control command strobes are executed immediately, except the SPWD strobe, which is delayed until CS goes high.

Table 3-4. Optional Pin Control Coding

CS SCLK SI FUNCTION

1 X X Chip unaffected by SCLK/SI

↓ 0 0 Generates SPWD strobe ↓ 0 1 Generates STX strobe ↓ 1 0 Generates SIDLE strobe ↓ 1 1 Generates SRX strobe

0 SPI mode SPI mode SPI mode (wakes up into IDLE if in SLEEP/XOFF)

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256

DRATE_M

logDRATE_E

DRATE_E

XOSC

DATA

XOSC

DATA

ú û

ê ë

÷ ø

ç è

BW =

channel

XOSC

8 × (4 + CHANBW_M) × 2

CHANBW_E

CC11x1-Q1

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3.8 Data Rate Programming

The data rate used when transmitting, or the data rate expected in receive is programmed by the MDMCFG3.DRATE_M and the MDMCFG4.DRATE_E configuration registers. The data rate is given by the formula below. As the formula shows, the programmed data rate depends on the crystal frequency.

The following approach can be used to find suitable values for a given data rate:

If DRATE_M is rounded to the nearest integer and becomes 256, increment DRATE_E and use DRATE_M = 0.

The data rate can be set from 1.2 kBaud to 500 kBaud with the minimum step size shown in Table 3-5.

MINIMUM TYPICAL MAXIMUM

0.8 1.2 / 2.4 3.17 0.0062

3.17 4.8 6.35 0.0124

6.35 9.6 12.7 0.0248

12.7 19.6 25.4 0.0496

25.4 38.4 50.8 0.0992

50.8 76.8 101.6 0.1984

101.6 153.6 203.1 0.3967

203.1 250 406.3 0.7935

SWRS076B–11-07-22-013 - APRIL 2009–REVISED APRIL 2010

(1)

(2)

Table 3-5. Data Rate Step Size

DATA RATE (kBaud) DATA RATE

STEP SIZE

(kBaud)

3.9 Receiver Channel Filter Bandwidth

To meet different channel width requirements, the receiver channel filter is programmable. The MDMCFG4.CHANBW_E and MDMCFG4.CHANBW_M configuration registers control the receiver channel filter bandwidth, which scales with the crystal oscillator frequency. Equation 3 gives the relation between the register settings and the channel filter bandwidth:

The CC11x1-Q1 supports the channel filter bandwidths shown in Table 3-6.

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+ 65 hidden pages

TEXAS INSTRUMENTS CC11x1-Q1 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Introduction

1.1 Features

1.2 Applications

1.3 Advantages

1.4 Family Members

1.5 Description

1.6 Abbreviations

2 Electrical Specifications

2.1 Absolute Maximum Ratings

2.2 Recommended Operating Conditions

2.3 General Characteristics

2.4 Current Consumption

2.5 RF Receive Section Characteristics

2.6 Selectivity

2.7 RSSI Section Characteristics

2.8 RF Transmit Section Characteristics

2.9 Crystal Oscillator Characteristics

2.10 Low-Power RC Oscillator Characteristics

2.11 Frequency Synthesizer Characteristics

2.12 Analog Temperature Sensor Characteristics

2.13 Digital Input/Output DC Characteristics

2.14 Power-On Reset Characteristics

2.15 SPI Interface Timing

2.16 Typical State Transition Timing

3 Detailed Description

3.1 Terminal Assignments

3.2 Block Diagram

3.3 Application Circuit

3.4 Configuration Overview

3.5 Configuration Software

3.6 4-Wire Serial Configuration and Data Interface

3.6.1 Chip Status Byte

3.6.2 Register Access

3.6.3 SPI Read

3.6.4 Command Strobes

3.6.5 FIFO Access

3.6.6 PATABLE Access

3.7 Microcontroller Interface and Pin Configuration

3.7.1 Configuration Interface

3.7.2 General Control and Status Pins

3.7.3 Optional Radio-Control Feature

3.8 Data Rate Programming

3.9 Receiver Channel Filter Bandwidth