Texas Instruments CC1020-RTB1, CC1020 Datasheet

CC1020

SWRS046A Page 1 of 91

CC1020

Low-Power RF Transceiver for Narrowband Systems

Applications

• Narrowband low power UHF wireless

data transmitters and receivers with channel spacing as low as 12.5 and 25 kHz

• 402 / 424 / 426 / 429 / 433 / 447 / 449 /

469 / 868 and 915 MHz ISM/SRD band systems

• AMR - Automatic Meter Reading

• Wireless alarm and security systems

• Home automation

• Low power telemetry

Product Description

CC1020

is a true single-chip UHF transceiver designed for very low power and very low voltage wireless applications. The circuit is mainly intended for the ISM (Industrial, Scientific and Medical) and SRD (Short Range Device) frequency bands at 402, 424, 426, 429, 433, 447, 449, 469, 868 and 915 MHz, but can easily be programmed for multi-channel operation at other frequencies in the 402 470 and 804 - 940 MHz range.

The

CC1020

is especially suited for narrow-

band systems with channel spacings of

12.5 or 25 kHz complying with ARIB STD T-67 and EN 300 220.

The

CC1020

main operating parameters can be programmed via a serial bus, thus making

CC1020

a very flexible and easy to

use transceiver.

In a typical system

CC1020

will be used together with a microcontroller and a few external passive components.

Features

• True single chip UHF RF transceiver

• Frequency range 402 MHz - 470 MHz

and 804 MHz - 940 MHz

• High sensitivity (up to -118 dBm for a

12.5 kHz channel)

• Programmable output power

• Low current consumption (RX: 19.9

mA)

• Low supply voltage (2.3 V to 3.6 V)

• No external IF filter needed

• Low-IF receiver

• Very few external components required

• Small size (QFN 32 package)

• Pb-free package

• Digital RSSI and carrier sense indicator

• Data rate up to 153.6 kBaud

• OOK, FSK and GFSK data modulation

• Integrated bit synchronizer

• Image rejection mixer

• Programmable frequency and AFC

make crystal temperature drift compensation possible without TCXO

• Suitable for frequency hopping systems

• Suited for systems targeting

compliance with EN 300 220, FCC CFR47 part 15 and ARIB STD T-67

• Development kit available

• Easy-to-use software for generating the

CC1020

configuration data

CC1020

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Table of Contents

1. Abbreviations................................................................................................................ 4

2. Absolute Maximum Ratings......................................................................................... 5

3. Operating Conditions ................................................................................................... 5

4. Electrical Specifications .............................................................................................. 5

4.1. RF Transmit Section ............................................................................................ 6

4.2. RF Receive Section ............................................................................................. 8

4.3. RSSI / Carrier Sense Section ............................................................................ 11

4.4. IF Section........................................................................................................... 11

4.5. Crystal Oscillator Section................................................................................... 12

4.6. Frequency Synthesizer Section ......................................................................... 13

4.7. Digital Inputs / Outputs....................................................................................... 14

4.8. Current Consumption......................................................................................... 15

5. Pin Assignment........................................................................................................... 15

6. Circuit Description...................................................................................................... 17

7. Application Circuit...................................................................................................... 18

8. Configuration Overview ............................................................................................. 21

8.1. Configuration Software ...................................................................................... 21

9. Microcontroller Interface............................................................................................ 22

9.1. 4-wire Serial Configuration Interface ................................................................. 23

9.2. Signal Interface .................................................................................................. 25

10. Data Rate Programming............................................................................................. 27

11. Frequency Programming ........................................................................................... 28

11.1. Dithering ......................................................................................................... 29

12. Receiver....................................................................................................................... 30

12.1. IF Frequency .................................................................................................. 30

12.2. Receiver Channel Filter Bandwidth................................................................ 30

12.3. Demodulator, Bit Synchronizer and Data Decision........................................ 31

12.4. Receiver Sensitivity versus Data Rate and Frequency Separation ............... 32

12.5. RSSI ............................................................................................................... 33

12.6. Image Rejection Calibration ........................................................................... 35

12.7. Blocking and Selectivity ................................................................................. 36

12.8. Linear IF Chain and AGC Settings................................................................. 37

12.9. AGC Settling................................................................................................... 38

12.10. Preamble Length and Sync Word .................................................................. 39

12.11. Carrier Sense ................................................................................................. 39

12.12. Automatic Power-up Sequencing................................................................... 40

12.13. Automatic Frequency Control......................................................................... 41

12.14. Digital FM ....................................................................................................... 42

CC1020

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13. Transmitter .................................................................................................................. 43

13.1. FSK Modulation Formats ............................................................................... 43

13.2. Output Power Programming........................................................................... 45

13.3. TX Data Latency............................................................................................. 46

13.4. Reducing Spurious Emission and Modulation Bandwidth.............................. 46

14. Input / Output Matching and Filtering....................................................................... 46

15. Frequency Synthesizer .............................................................................................. 50

15.1. VCO, Charge Pump and PLL Loop Filter....................................................... 50

15.2. VCO and PLL Self-Calibration ....................................................................... 51

15.3. PLL Turn-on Time versus Loop Filter Bandwidth........................................... 52

15.4. PLL Lock Time versus Loop Filter Bandwidth................................................ 53

16. VCO and LNA Current Control .................................................................................. 53

17. Power Management .................................................................................................... 54

18. On-Off Keying (OOK).................................................................................................. 57

19. Crystal Oscillator ........................................................................................................ 58

20. Built-in Test Pattern Generator ................................................................................. 59

21. Interrupt on Pin DCLK ................................................................................................ 60

21.1. Interrupt upon PLL Lock................................................................................. 60

21.2. Interrupt upon Received Signal Carrier Sense .............................................. 60

22. PA_EN and LNA_EN Digital Output Pins ................................................................. 61

22.1. Interfacing an External LNA or PA ................................................................. 61

22.2. General Purpose Output Control Pins............................................................ 61

22.3. PA_EN and LNA_EN Pin Drive...................................................................... 61

23. System Considerations and Guidelines................................................................... 62

24. PCB Layout Recommendations ................................................................................ 64

25. Antenna Considerations ............................................................................................ 65

26. Configuration Registers............................................................................................. 65

26.1. CC1020 Register Overview............................................................................ 66

27. Package Description (QFN 32) .................................................................................. 86

27.1. Package Marking............................................................................................ 87

27.2. Recommended PCB Footprint for Package (QFN 32)................................... 88

27.3. Package Thermal Properties.......................................................................... 88

27.4. Soldering Information ..................................................................................... 88

27.5. Plastic Tube Specification .............................................................................. 89

27.6. Carrier Tape and Reel Specification .............................................................. 89

28. Ordering Information.................................................................................................. 89

29. General Information.................................................................................................... 90

CC1020

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1. Abbreviations

ACP Adjacent Channel Power ACR Adjacent Channel Rejection ADC Analog-to-Digital Converter AFC Automatic Frequency Control AGC Automatic Gain Control AMR Automatic Meter Reading ASK Amplitude Shift Keying BER Bit Error Rate BOM Bill Of Materials bps bits per second BT Bandwidth-Time product (for GFSK) ChBW Receiver Channel Filter Bandwidth CW Continuous Wave DAC Digital-to-Analog Converter DNM Do Not Mount ESR Equivalent Series Resistance FHSS Frequency Hopping Spread Spectrum FM Frequency Modulation FS Frequency Synthesizer FSK Frequency Shift Keying GFSK Gaussian Frequency Shift Keying IC Integrated Circuit IF Intermediate Frequency IP3 Third Order Intercept Point ISM Industrial Scientific Medical kbps kilo bits per second LNA Low Noise Amplifier LO Local Oscillator (in receive mode) MCU Micro Controller Unit NRZ Non Return to Zero OOK On-Off Keying PA Power Amplifier PD Phase Detector / Power Down PER Packet Error Rate PCB Printed Circuit Board PN9 Pseudo-random Bit Sequence (9-bit) PLL Phase Locked Loop PSEL Program Select RF Radio Frequency RSSI Received Signal Strength Indicator RX Receive (mode) SBW Signal Bandwidth SPI Serial Peripheral Interface SRD Short Range Device TBD To Be Decided/Defined T/R Transmit/Receive (switch) TX Transmit (mode) UHF Ultra High Frequency VCO Voltage Controlled Oscillator VGA Variable Gain Amplifier XOSC Crystal oscillator XTAL Crystal

CC1020

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2. Absolute Maximum Ratings

The absolute maximum ratings given Table 1 should under no circumstances be violated. Stress exceeding one or more of the limiting values may cause permanent damage to the device.

Parameter Min Max Unit Condition

Supply voltage, VDD -0.3 5.0 V All supply pins must have the

same voltage Voltage on any pin -0.3 VDD+0.3, max 5.0 V Input RF level 10 dBm Storage temperature range -50 150

°C

Package body temperature 260

°C

Norm: IPC/JEDEC J-STD-020D 1 Humidity non-condensing 5 85 % ESD

(Human Body Model)

±1

±0.4

kV kV

All pads except RF RF Pads

Table 1. Absolute maximum ratings

1

The reflow peak soldering temperature (body temperature) is specified according to

IPC/JEDEC J-STD_020D “Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices”.

Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage.

3. Operating Conditions

The operating conditions for

CC1020

are listed in Table 2.

Parameter

Min Typ Max Unit Condition / Note

RF Frequency Range 402

804

470 940

MHz MHz

Programmable in <300 Hz steps Programmable in <600 Hz steps

Operating ambient temperature range -40 85

°C

Supply voltage

2.3 3.0 3.6 V

The same supply voltage should be used for digital (DVDD) and analog (AVDD) power.

A 3.0 ±0.1 V supply is recommended to meet the ARIB STD T-67 selectivity and output power tolerance requirements.

Table 2. Operating conditions

4. Electrical Specifications

Table 3 to Table 10 gives the

CC1020

electrical specifications. All measurements were

performed using the 2 layer PCB CC1020EMX reference design. This is the same test circuit as shown in Figure 3. Temperature = 25°C, supply voltage = AVDD = DVDD = 3.0 V if nothing else stated. Crystal frequency = 14.7456 MHz.

The electrical specifications given for 868 MHz are also applicable for the 902 - 928 MHz frequency range.

CC1020

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4.1. RF Transmit Section

Parameter

Min Typ Max Unit Condition / Note

Transmit data rate

0.45

153.6 kBaud The data rate is programmable. See section 10 on page 27 for details.

NRZ or Manchester encoding can be used. 153.6 kBaud equals

153.6 kbps using NRZ coding and 76.8 kbps using Manchester coding. See section 9.2 on page 25 for details

Minimum data rate for OOK is 2.4 kBaud

Binary FSK frequency separation

0 0

108

216

kHz kHz

in 402 - 470 MHz range in 804 - 940 MHz range

108/216 kHz is the maximum guaranteed separation at 1.84 MHz reference frequency. Larger separations can be achieved at higher reference frequencies.

Output power

433 MHz

868 MHz

-20 to +10

-20 to +5

dBm

Delivered to 50 Ω single-ended load. The output power is programmable and should not be programmed to exceed +10/+5 dBm at 433/868 MHz under any operating conditions (refer to CC1020 Errata Note 003). See section 14 on page 46 for details.

Output power tolerance

-4

+3

dB dB

At maximum output power At 2.3 V, +85

o

C

At 3.6 V, -40

o

C

Harmonics, radiated CW

2

nd

harmonic, 433 MHz, +10 dBm

3

rd

harmonic, 433 MHz, +10 dBm

2

nd

harmonic, 868 MHz, +5 dBm

3

rd

harmonic, 868 MHz, +5 dBm

-50

dBc dBc

Harmonics are measured as EIRP values according to EN 300

220. The antenna (SMAFF-433 and SMAFF-868 from R.W. Badland) plays a part in attenuating the harmonics.

Adjacent channel power (GFSK)

12.5 kHz channel spacing, 433 MHz

25 kHz channel spacing, 433 MHz

25 kHz channel spacing, 868 MHz

-46

-52

-49

dBc

For 12.5 kHz channel spacing ACP is measured in a ±4.25 kHz bandwidth at ±12.5 kHz offset. Modulation: 2.4 kBaud NRZ PN9 sequence, ±2.025 kHz frequency deviation.

For 25 kHz channel spacing ACP is measured in a ±8.5 kHz bandwidth at ±25 kHz offset. Modulation: 4.8 kBaud NRZ PN9 sequence, ±2.475 kHz frequency deviation.

CC1020

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Parameter

Min Typ Max Unit Condition / Note

Occupied bandwidth (99.5%,GFSK)

12.5 kHz channel spacing, 433 MHz

25 kHz channel spacing, 433 MHz

25 kHz channel spacing, 868 MHz

7.5

9.6

kHz

Bandwidth for 99.5% of total average power.

Modulation for 12.5 channel spacing: 2.4 kBaud NRZ PN9 sequence, ±2.025 kHz frequency deviation.

Modulation for 25 kHz channel spacing: 4.8 kBaud NRZ PN9 sequence, ±2.475 kHz frequency deviation.

Modulation bandwidth, 868 MHz

19.2 kBaud, ±9.9 kHz frequency deviation

38.4 kBaud, ±19.8 kHz frequency deviation

48

106

kHz

Bandwidth where the power envelope of modulation equals

-36 dBm. Spectrum analyzer RBW = 1 kHz.

Spurious emission, radiated CW

47-74, 87.5-118, 174-230, 470-862 MHz

9 kHz - 1 GHz

1 - 4 GHz

-54

-36

-30

dBm

At maximum output power, +10/+5 dBm at 433/868 MHz.

To comply with EN 300 220, FCC CFR47 part 15 and ARIB STD T-67 an external (antenna) filter, as implemented in the application circuit in Figure 25, must be used and tailored to each individual design to reduce out-of-band spurious emission levels.

Spurious emissions can be measured as EIRP values according to EN 300 220. The antenna (SMAFF-433 and SMAFF-868 from R.W. Badland) plays a part in attenuating the spurious emissions.

If the output power is increased using an external PA, a filter must be used to attenuate spurs below 862 MHz when operating in the 868 MHz frequency band in Europe. Application Note AN036

CC1020/1021 Spurious Emission

presents and discusses a solution that reduces the TX mode spurious emission close to 862 MHz by increasing the REF_DIV from 1 to 7.

Optimum load impedance

433 MHz

868 MHz

915 MHz

54 + j44

15 + j24

20 + j35

Ω

Transmit mode. For matching details see section 14 on page

46.

Table 3. RF transmit parameters

CC1020

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4.2. RF Receive Section

Parameter

Min Typ Max Unit Condition / Note

Receiver Sensitivity, 433 MHz, FSK

12.5 kHz channel spacing, optimized selectivity, ±2.025 kHz freq. deviation

12.5 kHz channel spacing, optimized sensitivity, ±2.025 kHz freq. deviation

25 kHz channel spacing

500 kHz channel spacing

Receiver Sensitivity, 868 MHz, FSK

12.5 kHz channel spacing, ±2.475 kHz freq. deviation

25 kHz channel spacing

500 kHz channel spacing

-114

-118

-112

-96

-116

-111

-94

dBm

Sensitivity is measured with PN9 sequence at BER = 10

-3

12.5 kHz channel spacing:

2.4 kBaud, Manchester coded data.

25 kHz channel spacing:

4.8 kBaud, NRZ coded data, ±2.475 kHz frequency deviation.

500 kHz channel spacing:

153.6 kBaud, NRZ coded data, ±72 kHz frequency deviation.

See Table 19 and Table 20 for typical sensitivity figures at other data rates.

Receiver sensitivity, 433 MHz, OOK

2.4 kBaud

153.6 kBaud

Receiver sensitivity, 868 MHz, OOK

4.8 kBaud

153.6 kBaud

-116

-81

-107

-87

dBm dBm

Sensitivity is measured with PN9 sequence at BER = 10

-3

Manchester coded data.

See Table 27 for typical sensitivity figures at other data rates.

Saturation (maximum input level) FSK and OOK

10

dBm FSK: Manchester/NRZ coded

data OOK: Manchester coded data BER = 10

-3

System noise bandwidth 9.6

to

307.2

kHz The receiver channel filter 6 dB

bandwidth is programmable from

9.6 kHz to 307.2 kHz. See section 12.2 on page 30 for details.

Noise figure, cascaded 433 and 868 MHz

7

dB NRZ coded data

Input IP3

433 MHz, 12.5 kHz channel spacing

868 MHz, 25 kHz channel spacing

-23

-18

-16

-18

-15

-13

dBm dBm dBm

Two tone test (+10 MHz and +20 MHz)

LNA2 maximum gain LNA2 medium gain LNA2 minimum gain

CC1020

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Parameter

Min Typ Max Unit Condition / Note

Co-channel rejection, FSK and OOK

12.5 kHz channel spacing, 433 MHz

25 kHz channel spacing, 433 MHz

25 kHz channel spacing, 868 MHz

-11

dB

Wanted signal 3 dB above the sensitivity level, FM jammer (1 kHz sine, ± 2.5 kHz deviation) at operating frequency, BER = 10

-3

Adjacent channel rejection (ACR)

12.5 kHz channel spacing, 433 MHz

25 kHz channel spacing, 433 MHz

25 kHz channel spacing, 868 MHz

32

37

32

dB

Wanted signal 3 dB above the sensitivity level, FM jammer (1 kHz sine, ± 2.5 kHz deviation) at adjacent channel. BER = 10

-3

Image channel rejection 433/868 MHz

No I/Q gain and phase calibration

I/Q gain and phase calibrated

26/31

49/52

dB

Wanted signal 3 dB above the sensitivity level, CW jammer at image frequency. BER = 10

-3

.

Image rejection after calibration will depend on temperature and supply voltage. Refer to section

12.6 on page 35.

Selectivity*

12.5 kHz channel spacing, 433 MHz

25 kHz channel spacing, 433 MHz

25 kHz channel spacing, 868 MHz

(*Close-in spurious response rejection)

41

39

dB

Wanted signal 3 dB above the sensitivity level. CW jammer is swept in 12.5 kHz/25 kHz steps to within ± 1 MHz from wanted channel. BER = 10

-3

. Adjacent channel and image channel are excluded.

Blocking / Desensitization* 433/868 MHz

± 1 MHz ± 2 MHz ± 5 MHz ± 10 MHz

(*Out-of-band spurious response rejection)

50/57 64/71 64/71 75/78

dB dB dB dB

Wanted signal 3 dB above the sensitivity level, CW jammer at ± 1, 2, 5 and 10 MHz offset. BER = 10

-3

. 12.5 kHz/25 kHz

channel spacing at 433/868 MHz.

Complying with EN 300 220, class 2 receiver requirements.

Image frequency suppression, 433/868 MHz

No I/Q gain and phase calibration

I/Q gain and phase calibrated

36/41

59/62

dB

Ratio between sensitivity for a signal at the image frequency to the sensitivity in the wanted channel. Image frequency is RF2 IF. The signal source is a 2.4 kBaud, Manchester coded data, ±2.025 kHz frequency deviation, signal level for BER = 10

-3

Spurious reception

40 dB Ratio between sensitivity for an

unwanted frequency to the sensitivity in the wanted channel. The signal source is a 2.4 kBaud, Manchester coded data, ±2.025 kHz frequency deviation, swept over all frequencies 100 MHz - 2 GHz. Signal level for BER = 10

-3

Intermodulation rejection (1)

12.5 kHz channel spacing, 433 MHz

25 kHz channel spacing, 868 MHz

30

dB

Wanted signal 3 dB above the sensitivity level, two CW jammers at +2Ch and +4Ch where Ch is channel spacing 12.5 kHz or 25 kHz. BER = 10

-2

CC1020

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Parameter

Min Typ Max Unit Condition / Note

Intermodulation rejection (2)

12.5 kHz channel spacing, 433 MHz

25 kHz channel spacing, 868 MHz

56

55

dB

Wanted signal 3 dB above the sensitivity level, two CW jammers at +10 MHz and +20 MHz offset. BER = 10

-2

LO leakage, 433/868 MHz <-80/-66 dBm

VCO leakage -64 dBm VCO frequency resides between

1608 - 1880 MHz

Spurious emission, radiated CW

9 kHz - 1 GHz

1 - 4 GHz

<-60

dBm

Complying with EN 300 220, FCC CFR47 part 15 and ARIB STD T-67.

Spurious emissions can be measured as EIRP values according to EN 300 220.

Input impedance

433 MHz

868 MHz

58 - j10

54 - j22

Ω

Receive mode. See section 14 on page 46 for details.

Matched input impedance, S11

433 MHz

868 MHz

-14

-12

dB

Using application circuit matching network. See section 14 on page 46 for details.

Matched input impedance

433 MHz

868 MHz

39 - j14

32 - j10

Ω

Using application circuit matching network. See section 14 on page 46 for details.

Bit synchronization offset 8000 ppm The maximum bit rate offset

tolerated by the bit synchronization circuit for 6 dB degradation (synchronous modes only)

Data latency

NRZ mode

Manchester mode

4

8

Baud

Time from clocking the data on the transmitter DIO pin until data is available on receiver DIO pin

Table 4. RF receive parameters

CC1020

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4.3. RSSI / Carrier Sense Section

Parameter

Min Typ Max Unit Condition / Note

RSSI dynamic range

55 dB 12.5 and 25 kHz channel spacing

RSSI accuracy

± 3

dB See section 12.5 on page 33 for

details.

RSSI linearity

± 1

dB

RSSI attach time

2.4 kBaud, 12.5 kHz channel spacing

4.8 kBaud, 25 kHz channel spacing

153.6 kBaud, 500 kHz channel spacing

3.8

1.9

140

ms

µs

Shorter RSSI attach times can be traded for lower RSSI accuracy. See section 12.5 on page 33 for details.

Shorter RSSI attach times can also be traded for reduced sensitivity and selectivity by increasing the receiver channel filter bandwidth.

Carrier sense programmable range

40 dB Accuracy is as for RSSI

Adjacent channel carrier sense

12.5 kHz channel spacing

25 kHz channel spacing

-72

dBm

At carrier sense level −110 dBm, FM jammer (1 kHz sine, ±2.5 kHz deviation) at adjacent channel.

Adjacent channel carrier sense is measured by applying a signal on the adjacent channel and observe at which level carrier sense is indicated.

Spurious carrier sense

-70 dBm At carrier sense level −110 dBm, 100 MHz - 2 GHz. Adjacent channel and image channel are excluded.

Table 5. RSSI / Carrier sense parameters

4.4. IF Section

Parameter

Min Typ Max Unit Condition / Note

Intermediate frequency (IF)

307.2 kHz See section 12.1 on page 30 for details.

Digital channel filter bandwidth

9.6

to

307.2

kHz The channel filter 6 dB bandwidth

is programmable from 9.6 kHz to

307.2 kHz. See section 12.2 on page 30 for details.

AFC resolution

150 Hz At 2.4 kBaud

Given as Baud rate/16. See section 12.13 on page 41 for details.

Table 6. IF section parameters

CC1020

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4.5. Crystal Oscillator Section

Parameter

Min Typ Max Unit Condition / Note

Crystal Oscillator Frequency

4.9152 14.7456 19.6608 MHz Recommended frequency is

14.7456 MHz. See section 19 on page 58 for details.

Reference frequency accuracy requirement

+/- 5.7

+/- 2.8

+/- 4

ppm

433 MHz (EN 300 220) 868 MHz (EN 300 220) Must be less than ±5.7 / ±2.8 ppm to comply with EN 300 220 25 kHz channel spacing at 433/868 MHz.

Must be less than ±4 ppm to comply with Japanese 12.5 kHz channel spacing regulations (ARIB STD T-67).

NOTE: The reference frequency accuracy (initial tolerance) and drift (aging and temperature dependency) will determine the frequency accuracy of the transmitted signal.

Crystal oscillator temperature compensation can be done using the fine step PLL frequency programmability and the AFC feature. See section 12.13 on page 41 for details.

Crystal operation

Parallel C4 and C5 are loading

capacitors. See section 19 on page 58 for details.

Crystal load capacitance

12 12 12

22 16 16

30 30 16

pF pF pF

4.9-6 MHz, 22 pF recommended 6-8 MHz, 16 pF recommended 8-19.6 MHz, 16 pF recommended

Crystal oscillator start-up time 1.55

1.0

0.90

0.95

0.60

0.63

ms

ms ms ms ms ms

4.9152 MHz, 12 pF load

7.3728 MHz, 12 pF load

9.8304 MHz, 12 pF load

14.7456 MHz, 16 pF load

17.2032 MHz, 12 pF load

19.6608 MHz, 12 pF load

External clock signal drive, sine wave

300

mVpp

The external clock signal must be connected to XOSC_Q1 using a DC block (10 nF). Set

XOSC_BYPASS = 0 in the INTERFACE register when using

an external clock signal with low amplitude or a crystal.

External clock signal drive, full-swing digital external clock

0 - VDD

V The external clock signal must be

connected to XOSC_Q1. No DC block shall be used. Set

XOSC_BYPASS = 1 in the INTERFACE register when using

a full-swing digital external clock.

Table 7. Crystal oscillator parameters

CC1020

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4.6. Frequency Synthesizer Section

Parameter

Min Typ Max Unit Condition / Note

Phase noise, 402 - 470 MHz

12.5 kHz channel spacing

-90

-100

-105

-110

-114

dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz

Unmodulated carrier

At 12.5 kHz offset from carrier At 25 kHz offset from carrier At 50 kHz offset from carrier At 100 kHz offset from carrier At 1 MHz offset from carrier

Measured using loop filter components given in Table 13. The phase noise will be higher for larger PLL loop filter bandwidth.

Phase noise, 804 - 940 MHz

25 kHz channel spacing

-85

-95

-101

-109

-118

dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz

Unmodulated carrier

At 12.5 kHz offset from carrier At 25 kHz offset from carrier At 50 kHz offset from carrier At 100 kHz offset from carrier At 1 MHz offset from carrier

Measured using loop filter components given in Table 13. The phase noise will be higher for larger PLL loop filter bandwidth.

PLL loop bandwidth

12.5 kHz channel spacing, 433 MHz

25 kHz channel spacing, 868 MHz

2.7

8.3

kHz

After PLL and VCO calibration. The PLL loop bandwidth is programmable.

PLL lock time (RX / TX turn time)

12.5 kHz channel spacing, 433 MHz

25 kHz channel spacing, 868 MHz

500 kHz channel spacing

900

640

14

us

307.2 kHz frequency step to RF frequency within ±10% of channel spacing. Depends on loop filter component values and PLL_BW register setting. See Table 26 on page 53 for more details.

PLL turn-on time. From power down mode with crystal oscillator running.

12.5 kHz channel spacing, 433 MHz

25 kHz channel spacing, 868 MHz

500 kHz channel spacing

3.2

2.5

700

ms

us

Time from writing to registers to RF frequency within ±10% of channel spacing. Depends on loop filter component values and PLL_BW register setting. See Table 25 on page 53 for more details.

Table 8. Frequency synthesizer parameters

CC1020

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4.7. Digital Inputs / Outputs

Parameter

Min Typ Max Unit Condition / Note

Logic « 0 » input voltage

0 0.3*

VDD

V

Logic « 1 » input voltage

0.7*

VDD

VDD V

Logic « 0 » output voltage 0

0.4 V Output current −2.0 mA,

3.0 V supply voltage

Logic « 1 » output voltage 2.5

VDD V Output current 2.0 mA,

3.0 V supply voltage

Logic “0” input current

NA −1

µA

Input signal equals GND.

PSEL has an internal pull-up resistor and during configuration the current will be -350 µA.

Logic “1” input current

NA 1

µA

Input signal equals VDD

DIO setup time 20 ns TX mode, minimum time DIO

must be ready before the positive edge of DCLK. Data should be set up on the negative edge of DCLK.

DIO hold time

10 ns TX mode, minimum time DIO

must be held after the positive edge of DCLK. Data should be set up on the negative edge of DCLK.

Serial interface (PCLK, PDI, PDO and PSEL) timing specification

See Table 14 on page 24 for

more details

Pin drive, LNA_EN, PA_EN

0.90

0.87

0.81

0.69

0.93

0.92

0.89

0.79

mA mA mA mA

Source current 0 V on LNA_EN, PA_EN pins

0.5 V on LNA_EN, PA_EN pins

1.0 V on LNA_EN, PA_EN pins

1.5 V on LNA_EN, PA_EN pins

Sink current

3.0 V on LNA_EN, PA_EN pins

2.5 V on LNA_EN, PA_EN pins

2.0 V on LNA_EN, PA_EN pins

1.5 V on LNA_EN, PA_EN pins

See Figure 35 on page 62 for more details.

Table 9. Digital inputs / outputs parameters

CC1020

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4.8. Current Consumption

Parameter

Min Typ Max Unit Condition / Note

Power Down mode

0.2 1.8

µA

Oscillator core off

Current Consumption, receive mode 433 and 868 MHz

19.9 mA

Current Consumption, transmit mode 433/868 MHz :

P = -20 dBm

P = -5 dBm

P = 0 dBm

P = +5 dBm

P = +10 dBm (433 MHz only)

12.3/14.5

14.4/17.0

16.2/20.5

20.5/25.1

27.1

mA

The output power is delivered to a 50 Ω single-ended load.

See section 13.2 on page 45 for more details.

Current Consumption, crystal oscillator

Current Consumption, crystal oscillator and bias

Current Consumption, crystal oscillator, bias and synthesizer

77

500

7.5

µA

mA

14.7456 MHz, 16 pF load crystal

Table 10. Current consumption

5. Pin Assignment

Table 11 provides an overview of the

CC1020

pinout.

The

CC1020

comes in a QFN32 type

package (see page 86 for details).

PCLK 1

VC24

AVDD

23

AVDD

22

RF_OUT

21

AVDD

20

RF_IN

19

AVDD

18

R_BIAS

17

AVDD16

PA_EN

15

LNA_EN

14

AVDD

13

AVDD

12

XOSC_Q2

11

XOSC_Q1

10

LOCK

9

DIO 8

DCLK

7

DGND

6

DVDD

5

DGND

4

PDO

3

PDI

2

32PSEL

31DVDD

30DGND

29AVDD

28CHP_OUT

27AVDD

26AD_REF

25AGND

AGND Exposed die attached pad

Figure 1.

CC1020

package (top view)

CC1020

SWRS046A Page 16 of 91

Pin no. Pin name Pin type Description

- AGND Ground (analog) Exposed die attached pad. Must be soldered to a solid ground plane as this is the ground connection for all analog modules. See page 64 for more details.

1 PCLK Digital input Programming clock for SPI configuration interface 2 PDI Digital input Programming data input for SPI configuration interface 3 PDO Digital output Programming data output for SPI configuration interface 4 DGND Ground (digital) Ground connection (0 V) for digital modules and digital I/O 5 DVDD Power (digital) Power supply (3 V typical) for digital modules and digital I/O 6 DGND Ground (digital) Ground connection (0 V) for digital modules (substrate) 7 DCLK Digital output Clock for data in both receive and transmit mode.

Can be used as receive data output in asynchronous mode

8 DIO Digital input/output Data input in transmit mode; data output in receive mode

Can also be used to start power-up sequencing in receive

9 LOCK Digital output PLL Lock indicator, active low. Output is asserted (low) when PLL is in

lock. The pin can also be used as a general digital output, or as receive data output in synchronous NRZ/Manchester mode

10 XOSC_Q1 Analog input Crystal oscillator or external clock input 11 XOSC_Q2 Analog output Crystal oscillator 12 AVDD Power (analog) Power supply (3 V typical) for crystal oscillator 13 AVDD Power (analog) Power supply (3 V typical) for the IF VGA 14 LNA_EN Digital output General digital output. Can be used for controlling an external LNA if

higher sensitivity is needed.

15 PA_EN Digital output General digital output. Can be used for controlling an external PA if

higher output power is needed.

16 AVDD Power (analog) Power supply (3 V typical) for global bias generator and IF anti-alias

filter

17 R_BIAS Analog output

Connection for external precision bias resistor (82 kΩ, ± 1%)

18 AVDD Power (analog) Power supply (3 V typical) for LNA input stage 19 RF_IN RF Input RF signal input from antenna (external AC-coupling) 20 AVDD Power (analog) Power supply (3 V typical) for LNA 21 RF_OUT RF output RF signal output to antenna 22 AVDD Power (analog) Power supply (3 V typical) for LO buffers, mixers, prescaler, and first PA

stage

23 AVDD Power (analog) Power supply (3 V typical) for VCO 24 VC Analog input VCO control voltage input from external loop filter 25 AGND Ground (analog) Ground connection (0 V) for analog modules (guard) 26 AD_REF Power (analog) 3 V reference input for ADC 27 AVDD Power (analog) Power supply (3 V typical) for charge pump and phase detector 28 CHP_OUT Analog output PLL charge pump output to external loop filter 29 AVDD Power (analog) Power supply (3 V typical) for ADC 30 DGND Ground (digital) Ground connection (0 V) for digital modules (guard) 31 DVDD Power (digital) Power supply connection (3 V typical) for digital modules 32 PSEL Digital input Programming chip select, active low, for configuration interface. Internal

pull-up resistor.

Table 11. Pin assignment overview

Note:

DCLK, DIO and LOCK are highimpedance (3-state) in power down (BIAS_PD = 1 in the MAIN register).

The exposed die attached pad must be soldered to a solid ground plane as this is the main ground connection for the chip.

CC1020

SWRS046A Page 17 of 91

6. Circuit Description

RF_IN

LNA

FREQ

SYNTH

DIGITAL

DEMODULATOR

- Digital RSSI

- Gain Control

- Image Suppression

- Channel Filtering

- Demodulation

DIGITAL

MODULATOR

- Modulation

- Data shaping

- Power Control

BIAS

Power

Control

DIGITAL

INTERFACE

TO µC

CONTROL

LOGIC

PA

ADC

RF_OUT

R_BIAS

XOSC_Q1 XOSC_Q2

PDO

XOSC

VC

CHP_OUT

LNA 2

0

90

:2

0

90

:2

Multiplexer

PA_EN

LNA_EN

PCLK

PDI

PSEL

Figure 2.

CC1020

simplified block diagram

A simplified block diagram of

CC1020

is shown in Figure 2. Only signal pins are shown.

CC1020

features a low-IF receiver. The received RF signal is amplified by the lownoise amplifier (LNA and LNA2) and down-converted in quadrature (I and Q) to the intermediate frequency (IF). At IF, the I/Q signal is complex filtered and amplified, and then digitized by the ADCs. Automatic gain control, fine channel filtering, demodulation and bit synchronization is performed digitally.

CC1020

outputs the digital demodulated data on the DIO pin. A synchronized data clock is available at the DCLK pin. RSSI is available in digital format and can be read via the serial interface. The RSSI also features a programmable carrier sense indicator.

In transmit mode, the synthesized RF frequency is fed directly to the power

amplifier (PA). The RF output is frequency shift keyed (FSK) by the digital bit stream that is fed to the DIO pin. Optionally, a Gaussian filter can be used to obtain Gaussian FSK (GFSK).

The frequency synthesizer includes a completely on-chip LC VCO and a 90 degrees phase splitter for generating the LO_I and LO_Q signals to the downconversion mixers in receive mode. The VCO operates in the frequency range

1.608-1.880 GHz. The CHP_OUT pin is the charge pump output and VC is the control node of the on-chip VCO. The external loop filter is placed between these pins. A crystal is to be connected between XOSC_Q1 and XOSC_Q2. A lock signal is available from the PLL.

The 4-wire SPI serial interface is used for configuration.

CC1020

SWRS046A Page 18 of 91

7. Application Circuit

Very few external components are required for the operation of

CC1020

. The recommended application circuit is shown in Figure 3. The external components are described in Table 12 and values are given in Table 13.

Input / output matching

L1 and C1 are the input match for the receiver. L1 is also a DC choke for biasing. L2 and C3 are used to match the transmitter to 50 Ω. Internal circuitry makes it possible to connect the input and output together and match the

CC1020

to

50 Ω in both RX and TX mode. However, it is recommended to use an external T/R switch for optimum performance. See section

14 on page 46 for details.

Component values for the matching network are easily found using the SmartRF

®

Studio software.

Bias resistor

The precision bias resistor R1 is used to set an accurate bias current.

PLL loop filter

The loop filter consists of two resistors (R2 and R3) and three capacitors (C6-C8). C7 and C8 may be omitted in applications where high loop bandwidth is desired. The

values shown in Table 13 can be used for data rates up to 4.8 kBaud. Component values for higher data rates are easily found using the SmartRF

®

Studio

software.

Crystal

An external crystal with two loading capacitors (C4 and C5) is used for the crystal oscillator. See section

19 on page

58 for details.

Additional filtering

Additional external components (e.g. RF LC or SAW filter) may be used in order to improve the performance in specific applications. See section

14 on page 46

for further information.

Power supply decoupling and filtering

Power supply decoupling and filtering must be used (not shown in the application circuit). The placement and size of the decoupling capacitors and the power supply filtering are very important to achieve the optimum performance for narrowband applications. TI provides a reference design that should be followed very closely.

Ref Description

C1 LNA input match and DC block, see page 46 C3 PA output match and DC block, see page 46 C4 Crystal load capacitor, see page 58 C5 Crystal load capacitor, see page 58 C6 PLL loop filter capacitor C7 PLL loop filter capacitor (may be omitted for highest loop bandwidth) C8 PLL loop filter capacitor (may be omitted for highest loop bandwidth) C60 Decoupling capacitor L1 LNA match and DC bias (ground), see page 46 L2 PA match and DC bias (supply voltage), see page 46 R1 Precision resistor for current reference generator R2 PLL loop filter resistor R3 PLL loop filter resistor R10 PA output match, see page 46 XTAL Crystal, see page 58

Table 12. Overview of external components (excluding supply decoupling capacitors)

CC1020

SWRS046A Page 19 of 91

1

PCLK

PDI

PDO

DGND

DCLK

DIO

DVDD

2

3

4

6

5

7

8

CC1020

9

LOCK

10

XOSC_Q111XOSC_Q2

12

AVDD

13

AVDD

14

LNA_EN

15

PA_EN

16

AVDD

32

PSEL

31

DVDD

30

DGND

29

AVDD

28

CHP_OUT

27

AVDD

26

AD_REF

25

AGND

24

VC

AVDD

RF_OUT

RF_IN

AVDD

R_BIAS

AVDD

23

22

21

19

20

18

17

C5

C4

XTAL

LC Filter

Monopole

antenna

(50 Ohm)

L2

C3

AVDD=3V

L1

C1

R1

AVDD=3V

DVDD=3V

AVDD=3V

Microcontroller configuration int erface and signal interface

C7 R3

C8

C6

R2

AVDD=3V

T/R Switch

C60

R10

1

PCLK

PDI

PDO

DGND

DCLK

DIO

DVDD

2

3

4

6

5

7

8

CC1020

9

LOCK

10

XOSC_Q111XOSC_Q2

12

AVDD

13

AVDD

14

LNA_EN

15

PA_EN

16

AVDD

32

PSEL

31

DVDD

30

DGND

29

AVDD

28

CHP_OUT

27

AVDD

26

AD_REF

25

AGND

24

VC

AVDD

RF_OUT

RF_IN

AVDD

R_BIAS

AVDD

23

22

21

19

20

18

17

C5C5

C4C4

XTALXTAL

LC FilterLC Filter

Monopole

antenna

(50 Ohm)

L2

C3

AVDD=3V

L1

C1

R1

AVDD=3V

DVDD=3V

AVDD=3V

Microcontroller configuration int erface and signal interface

C7 R3

C8

C6

R2

AVDD=3V

T/R Switch

C60

R10

Figure 3. Typical application and test circuit (power supply decoupling not shown)

Item 433 MHz 868 MHz 915 MHz

C1 10 pF, 5%, NP0, 0402 47 pF, 5%, NP0, 0402 47 pF, 5%, NP0, 0402 C3 5.6 pF, 5%, NP0, 0402 10 pF, 5%, NP0, 0402 10 pF, 5%, NP0, 0402 C4 22 pF, 5%, NP0, 0402 22 pF, 5%, NP0, 0402 22 pF, 5%, NP0, 0402 C5 12 pF, 5%, NP0, 0402 12 pF, 5%, NP0, 0402 12 pF, 5%, NP0, 0402 C6 220 nF, 10%, X7R, 0603 100 nF, 10%, X7R, 0603 100 nF, 10%, X7R, 0603 C7 8.2 nF, 10%, X7R, 0402 3.9 nF, 10%, X7R, 0402 3.9 nF, 10%, X7R, 0402 C8 2.2 nF, 10%, X7R, 0402 1.0 nF, 10%, X7R, 0402 1.0 nF, 10%, X7R, 0402 C60 220 pF, 5%, NP0, 0402 220 pF, 5%, NP0, 0402 220 pF, 5%, NP0, 0402 L1 33 nH, 5%, 0402 82 nH, 5%, 0402 82 nH, 5%, 0402 L2 22 nH, 5%, 0402 3.6 nH, 5%, 0402 3.6 nH, 5%, 0402 R1

82 kΩ, 1%, 0402 82 kΩ, 1%, 0402 82 kΩ, 1%, 0402

R2

1.5 kΩ, 5%, 0402 2.2 kΩ, 5%, 0402 2.2 kΩ, 5%, 0402

R3

4.7 kΩ, 5%, 0402 6.8 kΩ, 5%, 0402 6.8 kΩ, 5%, 0402

R10

82 Ω, 5%, 0402 82 Ω, 5%, 0402 82 Ω, 5%, 0402

XTAL 14.7456 MHz crystal,

16 pF load

14.7456 MHz crystal, 16 pF load

Note: Items shaded vary for different frequencies. For 433 MHz, 12.5 kHz channel, a loop filter with

lower bandwidth is used to improve adjacent and alternate channel rejection.

Table 13. Bill of materials for the application circuit in Figure 3

Note:

The PLL loop filter component values in Table 13 (R2, R3, C6-C8) can be used for data rates up to 4.8 kBaud. The SmartRF

®

Studio software provides component values for other data rates using the equations on page 50.

In the CC1020EMX reference design LQG15HS series inductors from Murata have been used. The switch is SW-456 from M/A-COM.

CC1020

SWRS046A Page 20 of 91

The LC filter in Figure 3 is inserted in the TX path only. The filter will reduce the emission of harmonics and the spurious emissions in the TX path. An alternative is to insert the LC filter between the antenna and the T/R switch as shown in Figure 4.

The filter will reduce the emission of harmonics and the spurious emissions in the TX path as well as increase the receiver selectivity. The sensitivity will be slightly reduced due to the insertion loss of the LC filter.

1

PCLK

PDI

PDO

DGND

DCLK

DIO

DVDD

2

3

4

6

5

7

8

CC1020

9

LOCK

10

XOSC_Q111XOSC_Q2

12

AVDD

13

AVDD

14

LNA_EN

15

PA_EN

16

AVDD

32

PSEL

31

DVDD

30

DGND

29

AVDD

28

CHP_OUT

27

AVDD

26

AD_REF

25

AGND

24

VC

AVDD

RF_OUT

RF_IN

AVDD

R_BIAS

AVDD

23

22

21

19

20

18

17

C5

C4

XTAL

LC Filter

Monopole

antenna

(50 Ohm)

L2

C3

AVDD=3V

L1

C1

R1

AVDD=3V

DVDD=3V

AVDD=3V

Microcontroller configuration int erface and signal int erface

C7 R3

C8

C6

R2

AVDD=3V

T/R Switch

C60

R10

1

PCLK

PDI

PDO

DGND

DCLK

DIO

DVDD

2

3

4

6

5

7

8

CC1020

9

LOCK

10

XOSC_Q111XOSC_Q2

12

AVDD

13

AVDD

14

LNA_EN

15

PA_EN

16

AVDD

32

PSEL

31

DVDD

30

DGND

29

AVDD

28

CHP_OUT

27

AVDD

26

AD_REF

25

AGND

24

VC

AVDD

RF_OUT

RF_IN

AVDD

R_BIAS

AVDD

23

22

21

19

20

18

17

C5C5

C4C4

XTALXTAL

LC FilterLC Filter

Monopole

antenna

(50 Ohm)

L2

C3

AVDD=3V

L1

C1

R1

AVDD=3V

DVDD=3V

AVDD=3V

Microcontroller configuration int erface and signal int erface

C7 R3

C8

C6

R2

AVDD=3V

T/R Switch

C60

R10

Figure 4. Alternative application circuit (power supply decoupling not shown)

CC1020

SWRS046A Page 21 of 91

8. Configuration Overview

CC1020

can be configured to achieve optimum performance for different applications. Through the programmable configuration registers the following key parameters can be programmed:

• Receive / transmit mode

• RF output power

• Frequency synthesizer key parameters:

RF output frequency, FSK frequency

separation, crystal oscillator reference frequency

• Power-down / power-up mode

• Crystal oscillator power-up / power-

down

• Data rate and data format (NRZ,

Manchester coded or UART interface)

• Synthesizer lock indicator mode

• Digital RSSI and carrier sense

• FSK / GFSK / OOK modulation

8.1. Configuration Software

TI provides users of

CC1020

with a

software program, SmartRF

®

Studio (Windows interface) that generates all necessary

CC1020

configuration data based on the user’s selections of various parameters. These hexadecimal numbers will then be the necessary input to the microcontroller for the configuration of

CC1020

. In addition, the program will provide the user with the component values needed for the input/output matching circuit, the PLL loop filter and the LC filter.

Figure 5 shows the user interface of the

CC1020

configuration software.

Figure 5. SmartRF

®

Studio user interface

CC1020

SWRS046A Page 22 of 91

9. Microcontroller Interface

Used in a typical system,

CC1020

will interface to a microcontroller. This microcontroller must be able to:

• Program

CC1020

into different modes via the 4-wire serial configuration interface (PDI, PDO, PCLK and PSEL)

• Interface to the bi-directional

synchronous data signal interface (DIO and DCLK)

• Optionally, the microcontroller can do

data encoding / decoding

• Optionally, the microcontroller can

monitor the LOCK pin for frequency lock status, carrier sense status or other status information.

• Optionally, the microcontroller can read

back the digital RSSI value and other status information via the 4-wire serial interface

Configuration interface

The microcontroller interface is shown in Figure 6. The microcontroller uses 3 or 4 I/O pins for the configuration interface (PDI, PDO, PCLK and PSEL). PDO should be connected to a microcontroller input. PDI, PCLK and PSEL must be microcontroller outputs. One I/O pin can be saved if PDI and PDO are connected together and a bi-directional pin is used at the microcontroller.

The microcontroller pins connected to PDI, PDO and PCLK can be used for other purposes when the configuration interface is not used. PDI, PDO and PCLK are high impedance inputs as long as PSEL is not activated (active low).

PSEL has an internal pull-up resistor and should be left open (tri-stated by the microcontroller) or set to a high level during power down mode in order to prevent a trickle current flowing in the pullup.

Signal interface

A bi-directional pin is usually used for data (DIO) to be transmitted and data received. DCLK providing the data timing should be connected to a microcontroller input.

As an option, the data output in receive mode can be made available on a

separate pin. See section

9.2 on page for

25 further details.

PLL lock signal

Optionally, one microcontroller pin can be used to monitor the LOCK signal. This signal is at low logic level when the PLL is in lock. It can also be used for carrier sense and to monitor other internal test signals.

PDI

PCLK

PSEL

DIO

LOCK

Microcontroller

DCLK

(Optional)

PDO (Optional)

PDI

PCLK

PSEL

DIO

LOCK

Microcontroller

DCLK

(Optional)

PDO (Optional)

Figure 6. Microcontroller interface

CC1020

SWRS046A Page 23 of 91

9.1. 4-wire Serial Configuration Interface

CC1020

is configured via a simple 4-wire SPI-compatible interface (PDI, PDO, PCLK and PSEL) where

CC1020

is the slave. There are 8-bit configuration registers, each addressed by a 7-bit address. A Read/Write bit initiates a read or write operation. A full configuration of

CC1020

requires sending 33 data frames of 16 bits each (7 address bits, R/W bit and 8 data bits). The time needed for a full configuration depends on the PCLK frequency. With a PCLK frequency of 10 MHz the full configuration is done in less than 53 µs. Setting the device in power down mode requires sending one frame only and will in this case take less than 2 µs. All registers are also readable.

During each write-cycle, 16 bits are sent on the PDI-line. The seven most significant bits of each data frame (A6:0) are the address-bits. A6 is the MSB (Most Significant Bit) of the address and is sent as the first bit. The next bit is the R/W bit (high for write, low for read). The 8 databits are then transferred (D7:0). During address and data transfer the PSEL (Program SELect) must be kept low. See Figure 7.

The timing for the programming is also shown in Figure 7 with reference to Table

14. The clocking of the data on PDI is done on the positive edge of PCLK. Data should be set up on the negative edge of PCLK by the microcontroller. When the last bit, D0, of the 8 data-bits has been loaded, the data word is loaded into the internal configuration register.

The configuration data will be retained during a programmed power down mode, but not when the power supply is turned off. The registers can be programmed in any order.

The configuration registers can also be read by the microcontroller via the same configuration interface. The seven address bits are sent first, then the R/W bit set low to initiate the data read-back.

CC1020

then returns the data from the addressed register. PDO is used as the data output and must be configured as an input by the microcontroller. The PDO is set at the negative edge of PCLK and should be sampled at the positive edge. The read operation is illustrated in Figure 8.

PSEL must be set high between each read/write operation.

PCLK

PDI

PSEL

Address Write mode

6543210

7 6 5 4 3 2 1 0

Data byte

T

HD

T

SS

T

CL,min

T

CH,min

T

HS

W

T

SD

PDO

Figure 7. Configuration registers write operation

CC1020

SWRS046A Page 24 of 91

PCLK

PDI

PSEL

A

ddress

Read mode

6 5 4

3 2 1 0

T

SS

T

CL,min

T

CH,min

T

HS

R

PDO

7 6 5 4 3

2 1 0

Data byte

T

SH

Figure 8. Configuration registers read operation

Parameter Symbol Min Max Unit Conditions

PCLK, clock frequency

F

PCLK

10 MHz

PCLK low pulse duration

T

CL,min

50 ns The minimum time PCLK must be low.

PCLK high pulse duration

T

CH,min

50 ns The minimum time PCLK must be high.

PSEL setup time

T

SS

25 ns The minimum time PSEL must be low before

positive edge of PCLK.

PSEL hold time

THS 25 ns The minimum time PSEL must be held low after

the negative edge of PCLK.

PSEL high time

TSH 50 ns The minimum time PSEL must be high.

PDI setup time

T

SD

25 ns The minimum time data on PDI must be ready

before the positive edge of PCLK.

PDI hold time

THD 25 ns The minimum time data must be held at PDI, after

the positive edge of PCLK.

Rise time T

rise

100 ns The maximum rise time for PCLK and PSEL

Fall time T

fall

100 ns The maximum fall time for PCLK and PSEL

Note: The setup and hold times refer to 50% of VDD. The rise and fall times refer to 10% / 90% of VDD. The maximum load that this table is valid for is 20 pF.

Table 14. Serial interface, timing specification

CC1020

SWRS046A Page 25 of 91

9.2. Signal Interface

The

CC1020

can be used with NRZ (NonReturn-to-Zero) data or Manchester (also known as bi-phase-level) encoded data.

CC1020

can also synchronize the data from the demodulator and provide the data clock at DCLK. The data format is controlled by the DATA_FORMAT[1:0] bits in the MODEM register.

CC1020

can be configured for three different data formats:

Synchronous NRZ mode

In transmit mode

CC1020

provides the data clock at DCLK and DIO is used as data input. Data is clocked into

CC1020

at the rising edge of DCLK. The data is modulated at RF without encoding.

In receive mode

CC1020

performs the synchronization and provides received data clock at DCLK and data at DIO. The data should be clocked into the interfacing circuit at the rising edge of DCLK. See Figure 9.

Synchronous Manchester encoded mode

In transmit mode

CC1020

provides the data clock at DCLK and DIO is used as data input. Data is clocked into

CC1020

at the rising edge of DCLK and should be in NRZ format. The data is modulated at RF with Manchester code. The encoding is done by

CC1020

. In this mode the effective bit rate is half the baud rate due to the coding. As an example, 4.8 kBaud Manchester encoded data corresponds to

2.4 kbps.

In receive mode

CC1020

performs the synchronization and provides received data clock at DCLK and data at DIO.

CC1020

performs the decoding and NRZ data is presented at DIO. The data should be clocked into the interfacing circuit at the rising edge of DCLK. See Figure 10.

In synchronous NRZ or Manchester mode the DCLK signal runs continuously both in RX and TX unless the DCLK signal is gated with the carrier sense signal or the

PLL lock signal. Refer to section

21 and

section

21.2 for more details.

If SEP_DI_DO = 0 in the INTERFACE register, the DIO pin is the data output in

receive mode and data input in transmit mode.

As an option, the data output can be made available at a separate pin. This is done by setting SEP_DI_DO = 1 in the INTERFACE register. Then, the LOCK pin will be used as data output in synchronous mode, overriding other use of the LOCK pin.

Transparent Asynchronous UART mode

In transmit mode DIO is used as data input. The data is modulated at RF without synchronization or encoding.

In receive mode the raw data signal from the demodulator is sent to the output (DIO). No synchronization or decoding of the signal is done in

CC1020

and should be

done by the interfacing circuit.

If SEP_DI_DO = 0 in the INTERFACE register, the DIO pin is the data output in receive mode and data input in transmit mode. The DCLK pin is not active and can be set to a high or low level by DATA_FORMAT[0].

If SEP_DI_DO = 1 in the INTERFACE register, the DCLK pin is the data output in receive mode and the DIO pin is the data input in transmit mode. In TX mode the DCLK pin is not active and can be set to a high or low level by DATA_FORMAT[0]. See Figure 11.

Manchester encoding and decoding In the Synchronous Manchester encoded mode

CC1020

uses Manchester coding

when modulating the data. The

CC1020

also performs the data decoding and synchronization. The Manchester code is based on transitions; a “0” is encoded as a low-to-high transition, a “1” is encoded as a high-to-low transition. See Figure 12.

The Manchester code ensures that the signal has a constant DC component, which is necessary in some FSK demodulators. Using this mode also ensures compatibility with CC400/CC900 designs.

CC1020

SWRS046A Page 26 of 91

Clock provided by CC1020

FSK modulating signal (NRZ), internal in CC1020

Data provided by microcontroller

Transmitter side:

Clock provided by CC1020

Demodulated signal (NRZ), internal in CC1020

Data provided by CC1020

DCLK

DIO

“RF”

DCLK

DIO

Receiver side:

Clock provided by CC1020

FSK modulating signal (NRZ), internal in CC1020

Data provided by microcontroller

Transmitter side:

Clock provided by CC1020

Demodulated signal (NRZ), internal in CC1020

Data provided by CC1020

DCLK

DIO

“RF”

DCLK

DIO

Receiver side:

Figure 9. Synchronous NRZ mode (SEP_DI_DO = 0)

Clock provided by CC1020

FSK modulating signal (Manchester encoded), internal in CC1020

Data provided by microcontr oller

Transmitter side:

Clock provided by CC1020

Demodulated signal (Manchester encoded), internal in CC1020

Data provided by CC1020

DCLK

DIO

“RF”

DCLK

DIO

Receiver side:

Clock provided by CC1020

FSK modulating signal (Manchester encoded), internal in CC1020

Data provided by microcontr oller

Transmitter side:

Clock provided by CC1020

Demodulated signal (Manchester encoded), internal in CC1020

Data provided by CC1020

DCLK

DIO

“RF”

DCLK

DIO

Receiver side:

Figure 10. Synchronous Manchester encoded mode (SEP_DI_DO = 0)

CC1020

SWRS046A Page 27 of 91

DCLK is not used in transmit mode, and is used as data output in receive mode. It can be set to default high or low in transmit mode.

FSK modulating signal, internal in CC1020

Data provided by UART (TXD)

Transmitter side:

DCLK is used as data output provided by CC1020. Connect to UART (RXD)

Demodulated signal (NRZ), internal in CC1020

DIO is not used in receive mode. Used o nly as data input in transmit mode

DCLK

DIO

“RF”

DCLK

DIO

Receiver side:

DCLK is not used in transmit mode, and is used as data output in receive mode. It can be set to default high or low in transmit mode.

FSK modulating signal, internal in CC1020

Data provided by UART (TXD)

Transmitter side:

DCLK is used as data output provided by CC1020. Connect to UART (RXD)

Demodulated signal (NRZ), internal in CC1020

DIO is not used in receive mode. Used o nly as data input in transmit mode

DCLK

DIO

“RF”

DCLK

DIO

Receiver side:

Figure 11. Transparent Asynchronous UART mode (SEP_DI_DO = 1)

Time

1 0 1 1 0 0 0 1 1 0 1

Tx data

Time

1 0 1 1 0 0 0 1 1 0 1

Tx data

Figure 12. Manchester encoding

10. Data Rate Programming

The data rate (baud rate) is programmable and depends on the crystal frequency and the programming of the CLOCK (CLOCK_A and CLOCK_B) registers.

The baud rate (B.R) is given by

21)1_(8

..

DIVDIVDIVREF

f

RB

xosc

⋅⋅+⋅

=

where DIV1 and DIV2 are given by the value of MCLK_DIV1 and MCLK_DIV2.

Table 17 shows some possible data rates as a function of crystal frequency in synchronous mode. In asynchronous transparent UART mode any data rate up to 153.6 kBaud can be used.

MCLK_DIV2[1:0] DIV2

00 1 01 2 10 4 11 8

Table 15. DIV2 for different settings of

MCLK_DIV2

MCLK_DIV1[2:0] DIV1

000 2.5 001 3 010 4 011 7.5 100 12.5 101 40 110 48 111 64

Table 16. DIV1 for different settings of

MCLK_DIV1

CC1020

SWRS046A Page 28 of 91

Crystal frequency [MHz] Data rate

[kBaud]

4.9152 7.3728 9.8304 12.288 14.7456 17.2032 19.6608

0.45 X X

0.5 X

0.6 X X X X X X X

0.9 X X 1 X

1.2 X X X X X X X

1.8 X X 2 X

2.4 X X X X X X X

3.6 X X 4 X

4.096 X X

4.8 X X X X X X X

7.2 X X 8 X

8.192 X X

9.6 X X X X X X X

14.4 X X 16 X

16.384 X X

19.2 X X X X X X X

28.8 X X 32 X

32.768 X X

38.4 X X X X X X X

57.6 X X 64 X

65.536 X

76.8 X X X X X X X

115.2 X X 128 X

153.6 X X X X X

Table 17. Some possible data rates versus crystal frequency

11. Frequency Programming

Programming the frequency word in the configuration registers sets the operation frequency. There are two frequency words registers, termed FREQ_A and FREQ_B, which can be programmed to two different frequencies. One of the frequency words can be used for RX (local oscillator frequency) and the other for TX (transmitting carrier frequency) in order to be able to switch very fast between RX mode and TX mode. They can also be used for RX (or TX) at two different channels. The F_REG bit in the MAIN register selects frequency word A or B.

The frequency word is located in

FREQ_2A:FREQ_1A:FREQ_0A and FREQ_2B:FREQ_1B:FREQ_0B for the FREQ_A and FREQ_B word respectively.

The LSB of the FREQ_0 registers are used to enable dithering, section

11.1.

The PLL output frequency is given by:

⎟ ⎠

⎞

⎜ ⎝

⎛

⋅+

+⋅=

32768

5.0

4

3

DITHERFREQ

ff

refc

in the frequency band 402 - 470 MHz, and

⎟ ⎠

⎞

⎜ ⎝

⎛

⋅+

+⋅=

16384

5.0

2

3

DITHERFREQ

ff

refc

in the frequency band 804 - 940 MHz.

The BANDSELECT bit in the ANALOG register controls the frequency band used. BANDSELECT = 0 gives 402 - 470 MHz, and BANDSELECT = 1 gives 804 - 940 MHz.

The reference frequency is the crystal oscillator clock frequency divided by REF_DIV (3 bits in the CLOCK_A or

Texas Instruments CC1020-RTB1, CC1020 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual