TEXAS INSTRUMENTS bq24180 Technical data

VBUS

VBUS

GND

HOST

bq24180

SW

PSEL

SCL

DCOUT

C1

1 µF

C2

10µF

C3

4.7µF

R3

4 kW

SYSTEM

PMID

SDA

D+
D-

USBPHY

BOOT

PGND

CSIN

CSOUT

VAUX

STAT

POWERFOR
ACCESSORY

C4

10nF

C 6

1 µF

C 5

0.1µF

RSNS
68 mW

R1

10kW

R2

VBUS

TS

TEMP

PACK+

PACK-

DRV

C7

1 µF

VBUS

INT

R4

C 8

1 µF

CD

HardwareDisable

10kW 10kW

bq24180

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SLUSA02 A –FEBRUARY 2010–REVISED FEBRUARY 2010

Fully Integrated Switch-Mode One-Cell Li-Ion Charger with Full USB Compliance and

Accessory Power Connection

Check for Samples: bq24180

1

FEATURES

2

• Charge Faster than Linear Chargers From
Current Limited Input Sources • Programmable Charge Parameters through

• High-Accuracy Voltage and Current Regulation
– Input Current Regulation Accuracy: ±5%

(100mA, 500mA)

– Charge Voltage Regulation Accuracy:

±0.5% (25°C), ±1% (0–125°C)

– Charge Current Regulation Accuracy: ±5%

• Accessory Power Output (DCOUT)

• Input Voltage Based Dynamic Power
Management

• Safety Limit Register for Maximum Charge
Voltage and Current Limiting

• High-Efficiency Mini-USB/AC Battery Charger
for Single-Cell Li-Ion and Li-Polymer Battery
Packs

• 20-V Absolute Maximum and 16.5V Operation
Input Voltage Rating

• Built-in Input Current Sensing and Limiting

• Integrated Power FETs for Up to 1.5-A Charge
Rate

I2C™ compatible Interface (up to 3.4 Mbps)

• Synchronous Fixed-Frequency PWM
Controller Operating at 3 MHz With 0% to

99.5% Duty Cycle

• Safety Timer and Software Watchdog

• Reverse Leakage Protection Prevents Battery
Drainage

• Thermal Regulation and Protection

• Status Outputs for Charging and Faults

• 25-Pin WCSP Package

APPLICATIONS

• Mobile Phones and Smart Phones

• Portable Media Players

• Handheld Devices

DESCRIPTION

The bq24180 is a compact, flexible, high-efficiency, USB-friendly switch-mode charge management device for
single-cell Li-ion and Li-polymer batteries used in a wide range of portable applications. The charge parameters
is programmable using an I2C compatible interface. The bq24180 integrates a synchronous PWM controller,
power MOSFETs, input current sensing and overvoltage protection, high-accuracy current and voltage regulation,
and charge termination, into a small WCSP package.

1

2

2I

C is a trademark of Phillips Electronics.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright © 2010, Texas Instruments Incorporated

bq24180

SLUSA02 A –FEBRUARY 2010–REVISED FEBRUARY 2010

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

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DESCRIPTION (CONTINUED)

The bq24180 charges the battery in three phases: conditioning, constant current and constant voltage. Charge
current is programmable using the I2C interface. Additionally, the input current can be limited to a host
programmable threshold to maintain maximum charge current from current-limited sources, such as USB ports.
Charge is terminated based on user-selectable minimum current level. A software watchdog provides a safety
backup for I2C interface while a safety timer prevents overcharging the battery. During normal operation,
bq24180 automatically restarts the charge cycle if the battery voltage falls below an internal threshold and
automatically enters sleep mode or high impedance mode when the input supply is removed. The charge status
is reported to the host using the I2C interface. During the charging process, the bq24180 monitors its junction
temperature (TJ) and reduces the charge current if TJincreases to 125°C. The bq24180 is available in 25-pin
WCSP package.

ORDERING INFORMATION

PART NUMBER

bq24180YFFR 16.5 V 6B
bq24180YFFT 16.5 V 6B

(1) The YFF package is available in the following options:

R – taped and reeled in quantities of 3,000 devices per reel.
T – taped and reeled in quantities of 250 devices per reel.

(2) This product is RoHS compatible, including a lead concentration that does not exceed 0.1% of total product weight, and is suitable for

use in specified lead-free soldering processes. In addition, this product uses package materials that do not contain halogens, including
bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(1)(2)

V

OVP

I2C ADDRESS

ABSOLUTE MAXIMUM RATINGS

(1)(2)

over operating free-air temperature range (unless otherwise noted)

LIMITS UNIT

Supply voltage range (with respect to PGND) VBUS –2 to 20 V
Input voltage range (with respect to and PGND) SCL, SDA, PSEL, CSIN, CSOUT, DRV, DCOUT, INT –0.3 to 7 V

Output voltage range (with respect to and PGND) V

Voltage difference between CSIN and CSOUT inputs (VCSIN –VCSOUT) ±7 V
Voltage difference between BOOT and SW inputs (VBOOT –VSW) –0.3 to 7 V

Output sink mA

Output current DCOUT 1.5 A

Output current (average) SW 2 A
T

A

T

J

T

stg

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging

Section of the data book for thermal limitations and considerations of packages.

Operating free-air temperature range –30 to +85 °C
Junction temperature range –40 to +125 °C
Storage temperature –45 to +150 °C

PMID, STAT –0.3 to 20
SW, BOOT –0.7 to 20

INT 5
STAT 10

DRV 10 mA

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SLUSA02 A –FEBRUARY 2010–REVISED FEBRUARY 2010

DISSIPATION RATINGS

PACKAGE R

WCSP-25 60°C/W

(1) Using JEDEC 2s2p PCB standard.

qJA

R

qJC

(1)

1.57°C/W 540 mW 5.4 mW/°C

TA< 25°C DERATING FACTOR

POWER RATING ABOVE TA= 25°C

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

Supply voltage, VBUS 4.0 16
Operating junction temperature range, T

J

0 125 °C

(1) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BOOT or SW pins. A tight

layout minimizes switching noise.

(1)

ELECTRICAL CHARACTERISTICS

Circuit of Figure 2, V
noted)

INPUT CURRENTS

I

VBUS

I

VBUS_LEAK

I

BAT_DCOUT

I

BAT_HIZ

VOLTAGE REGULATION

V

OREG

CURRENT REGULATION - FAST CHARGE

I

OCHARGE

PSEL, CD LOGIC LEVEL

V

IL

V

IH

CHARGE TERMINATION DETECTION

I

TERM

I

TERM_dgl

INPUT BASED DYNAMIC POWER MANAGEMENT

V

VBUS

Leakage current from battery to VBUS pin 0°C< TJ< 85°C, V
Battery Current when using DCOUT 800 µA

Battery discharge current in High Impedance
mode, (CSIN, CSOUT, SW pins)

Output charge voltage programmable range Operating in voltage regulation, programmable 3.5 4.44 V

Voltage regulation accuracy

Output charge current programmable range 550 1550 mA
Regulation accuracy for charge current V

across RSNS
V

IREG

Input low threshold level PSEL, CD falling 0.4 V
Input high threshold level PSEL, CD rising 1.2 V

Termination charge current 25 200 mA

Deglitch time for charge termination 30 ms

Regulation accuracy for termination current
across R
V

IREG_TERM

Battery Detection sink current before charge
done

= 5V, HZ_MODE=0, CD=0, TJ= –40°C to 125°C and TJ= 25°C for typical values (unless otherwise

VBUS

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

supply current for control V

VBUS
VBUS

> V
> V

, PWM switching 10 mA

VBUS(min)

, PWM NOT switching 5 mA

VBUS(min)

0°C< TJ< 85°C, EN=0 or HZ_MODE=1 650 µA

= 4.2 V, No input connected 5 µA

CSOUT

DCOUT = enabled, V
I

=750mA

DCOUT

0°C< TJ< 85°C, V
DCOUT disabled SCL,SDA=0V or 1.8V

= 4.2V, DCOUT_ILIM=1A,

BAT

= 4.2 V, No Input connected,

CSOUT

30 µA

0°C< TJ < 85°C, VCSOUT = 4.2 V, High Impedance
mode, DCOUT disabled, V
SCL,SDA=0V or 1.8V

= 5V, 60 µA

VBUS

TA= 25°C –0.5% 0.5%

–1% 1%

V

= I

OCHARGE

× R

SNS

≤ V

PRECHG

R

= 68 mΩ, Programmable

SNS

= 37.4 mV to 44.2 mV –3.5% 3.5%

ICHRG

V

> 44.2 mV –3.0% 3.0%

ICHRG

V

> V

CSOUT

R

= 68 MΩ, Programmable

SNS

< V

CSOUT

OREG–VRCH

OREG

, V

VBUS>VSLP

, V

VBUS>VSLP

,

,

Both rising and falling, 2-mV over- drive,
t

, t

= 100 ns

FALL

= 1.7 mV –40% 40%

TERM

= 3.4 mV to 6.8 mV –16% 16%

TERM

= 6.8 mV to 13.6 mV –11% 11%

TERM

≥ 13.6 mV –5.5% 5.5%

TERM

SNS

= I

OTERM

× R

SNS

RISE

V
V
V
V

–550 µA

V

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bq24180

SLUSA02 A –FEBRUARY 2010–REVISED FEBRUARY 2010

ELECTRICAL CHARACTERISTICS (continued)

Circuit of Figure 2, V
noted)

V

IN_DPM

FAULTY ADAPTER PROTECTION

V

VBUS (MIN)

t

INT

INPUT CURRENT LIMITING

I

IN_LIMIT

DCOUT

R

DCOUT

I

LIM_DCOUT

t

DGL_DCOUT

I

LIM_DCOUT

BATTERY RECHARGE THRESHOLD

V

RCH

STAT OUTPUTS

V

OL(STAT)

V

OL(INT)

I2C BUS LOGIC LEVELS AND TIMING CHARACTERISTICS

V

OL

I

(bias)

f

SCL

SLEEP COMPARATOR

V

SLP

V

SLP-EXIT

UVLO

V

UVLO

V

UVLO_HYS

PWM

The threshold when input based DPM loop
kicks in

DPM loop kick-in threshold tolerance –2% 2%

Faulty adapter threshold 3.6 3.8 4.0 V
Deglitch time for Faulty adapter 30 ms
Hysteresis for faulty adapter protection V
Current source for faulty adapter protection 20 30 40 mA
Detection Interval 2 s

Input current limiting threshold I

DCOUT Pass FET on-resistance I
DCOUT current limit programmable range 350 1400 mA
Deglitch time from DCOUT current-limit event

to DCOUT latch-off

DCOUT current limit range mA

Recharge threshold voltage Below VOREG 100 120 150 mV
Deglitch time 130 ms

Low-level output saturation voltage, STAT IO= 10 mA, sink current 0.5 V
High-level leakage current Voltage on STAT pin is 5V 1 µA
Low-level output saturation voltage, INT IO= 1 mA, sink current 0.4 V
High-level leakage current Voltage on INT pin is 5V 1 µA

Output low threshold level IO= 10 mA, sink current 0.4 V
Input low threshold level V
Input high threshold level V
Input bias current V
SCL clock frequency 3.4 MHz

Sleep-mode entry threshold,
V

BUS-VCSOUT

Sleep-mode exit hysteresis 2.3 V ≤ V
Deglitch time for VBUS rising above

V

SLP+VSLP_EXIT

IC active threshold voltage V
IC active hysteresis V

Internal top reverse blocking MOSFET
on-resistance

Internal top N-channel Switching MOSFET
on-resistance

= 5V, HZ_MODE=0, CD=0, TJ= –40°C to 125°C and TJ= 25°C for typical values (unless otherwise

VBUS

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Charge mode, programmable 4.15 4.71 V

Rising 100 200 mV

VBUS

USB charge mode, current
pulled from PMID

= 500 mA 300 mΩ

DCOUT

Programmable via I2C

Programmable via I2C

V

decreasing below threshold,

CSOUT

t

= 100 ns, 10-mV overdrive

FALL

= 1.8 V, SDA and SCL 0.4 V

(pull-up)

= 1.8 V, SDA and SCL 1.2 V

(pull-up)

= 1.8 V, SDA and SCL 1 µA

(pull-up)

2.3 V ≤ V

CSOUT

CSOUT

Rising voltage, 2-mV over drive, t

rising 3.05 3.3 3.55 V

VBUS

falling from above V

VBUS

I

= 500 mA, Measured from V

IN_LIMIT

Measured from PMID to SW 130 250 mΩ

≤ V
< V

OREG

OREG

I

= 100 mA 90 95 100

IN_LIMIT

= 500 mA 450 475 500 mA

IN_LIMIT

I

= 800 mA 700 755 800

IN_LIMIT

14.5 ms

I

LIM_DCOUT

I

LIM_DCOUT

I

LIM_DCOUT

I

LIM_DCOUT

, V

falling 0 40 100 mV

VBUS

= 350mA 270 350
= 750mA 650 750
= 1050mA 800 1050
= 1400mA 1050 1400

140 200 260 mV

= 100 ns 30 ms

RISE

UVLO

to PMID 110 210 mΩ

VBUS

120 150 mV

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SLUSA02 A –FEBRUARY 2010–REVISED FEBRUARY 2010

ELECTRICAL CHARACTERISTICS (continued)

Circuit of Figure 2, V
noted)

Internal bottom N-channel MOSFET
on-resistance

f

OSC

D

MAX

D

MIN

V

DRV

I

DRV

V

DO_DRV

PROTECTION

V

OVP

V

IN_HIGH

t

OVP-dgl

I

LIMIT

V

PRECHG

I

PRECHG

T

SHTDWN

T

CF

t

WATCHDOG

V

HOT

V

WARM

V

COLD

I

TS

(1) Bottom N-channel MOSFET always turns on for ~60 ns and then turns off if current is too low.

Oscillator frequency 3.0 MHz
Frequency accuracy –10% 10%
Maximum duty cycle 99.5%
Minimum duty cycle 0
Synchronous mode to non-synchronous

mode transition current threshold
Internal bias voltage regulator I
DRV Output Current External load on DRV 10 mA

DRV Dropout Voltage (V

Input OVP threshold voltage Threshold over V
V

hysteresis V

OVP

Input High threshold V
VIN_HIGH_USB hysteresis V
OVP deglitch time V
Cycle-by-cycle current limit for charge Charge mode operation 1.8 2.4 3.0 A
Precharge to fast charge threshold V
VPRECHG hysteresis V
Precharge charge charging current V
Thermal trip 165 °C
Thermal hysteresis 10 °C
Thermal regulation threshold Charge current begins to taper down 120 °C
Timeout for the watchdog timer Watchdog timer 12 s
Safety timer accuracy –20% 20%
TS Hot Threshold Corresponds to 55°C, VTSFalling 0.153 0.160 0.169 V
TS Hot Threshold Hysteresis VTS Rising 12.5 mV
TS Warm Threshold Corresponds to 45°C VTSFalling 0.210 0.225 0.240 V
TS Warm Threshold Hysteresis VTSRising 12.5 mV
TS Cold Threshold Corresponds to 5°C, VTSRising 1.06 1.10 1.14 V
TS Cold Threshold Hysteresis VTSFalling 75 mV
TS Bias Current 95 100 105 µA
TS Open Resistance Resistance on TS that translates to open circuit on TS 200 kΩ

= 5V, HZ_MODE=0, CD=0, TJ= –40°C to 125°C and TJ= 25°C for typical values (unless otherwise

VBUS

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Measured from SW to PGND 125 210 mΩ

Low-side MOSFET cycle-by-cycle current sensing 100 mA

= 10 mA 5 5.2 5.45 V

DRV

I

= 1A, V

VBUS

V

< V

UVLO

falling from above V

VBUS

Rising, Threshold where I

VBUS

falling from above V

VBUS

rising or falling 32 ms

VBUS

rising 1.9 2.0 2.1 V

CSOUT

falling from above V

CSOUT

≤ V

CSOUT

VBUS

VBUS<VSLP

VBUS

and V

SHORT

= 5 V, I

= 10 mA 340

DRV

to turn off converter during charge 16 16.5 17 V

OVP

falls to 50 mA 9.5 9.8 10.1 V

BAT

IN_HIGH

PRECHG

< V

IN_HIGH

VBUS

< V

OVP

VBUS

(1)

– V

) mV

DRV

750

185 mV

150 mV

100 mV

33.5 50.0 66.5 mA

Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 5

Product Folder Link(s): bq24180

VBUS

SW

+

+

BOOT

DRV

VDRV

CSIN

CSOUT

V

PRECHG

+ -

+

InputCurrentLimit

Amplifier

INT

+

+

+

REF

TS

TSHOT

TSWARM

TSCOLD

DISABLE

V

PRECHG

Comparator

+

V

BATREG

Amplifier

PMID

DC-DC

CONVERTER

PWMLOGIC

AND

COMPENSATION

400mA

maxcharge

V

OREG

I

IN_LIMIT

Gm
amp

I

OUTREG

Amplifier

Charge

Pump

+

Sleep

Comparator

V

BAT

V

IN

5.2V

Reference

+

Recharge

Comparator

Termination
Comparator

I2Cand

CHARGE

CONTROLLER

PGND

PSEL

SDA

SCL

DCOUT

+

V

IN

50mA Precharge

CurrentSource

-

+

130mV

V

ICHRG

V

ITERM

VDRV

Charge

Pump

+

16.5V

OVP

Comparator

High-Input

Comparator

9.8V

+

VIN-DPM
Amplifier

V

INDPM

V

HIGH

Comparator

+

DCOUT _ILIM

TMR

SAFETY
TIMERS

2X

TIMER
FAULT

Q1

Q2

Q3

Q4

Q5

REF

100uA

+

+

ThermalReg

Amplifier

125°C

T

J

STAT

CD

bq24180

SLUSA02 A –FEBRUARY 2010–REVISED FEBRUARY 2010

SIMPLIFIED BLOCK DIAGRAM

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6 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated

Figure 1. Simplified Block Diagram

Product Folder Link(s): bq24180

VBUS VBUS BOOT SCL

PMID PMID PMID CD

SW SW SW PSEL

PGND PGND PGND

STAT

DRV

DCOUT

CSIN CSOUT

SDA

INT

DCOUT

CSOUTTS

1 2 3 4 5

A

B

C

D

E

2.2mmx2.4mm25-pinWCSP

TOP VIEW

bq24180

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SLUSA02 A –FEBRUARY 2010–REVISED FEBRUARY 2010

DEVICE INFORMATION

PIN CONFIGURATION

PIN FUNCTIONS

NAME PIN NO. I/O DESCRIPTION

VBUS A1, A2 I/O Charger Input Voltage. Connect to an input supply up to 16V. Bypass VBUS to PGND with a 1µF ceramic

BOOT A3 O High-Side MOSFET Gate Driver Supply. Connect a 10nF ceramic capacitor (voltage rating above 10V) from

SCL A4 I I2C interface clock. Connect SCL to the logic rail through a 10kΩ resistor.
SDA A5 I/O I2C interface data. Connect SCL to the logic rail through a 10kΩ resistor.
PMID B1, B2, B3 O Connection Point Between Reverse Blocking MOSFET and High-Side Switching MOSFET. Bypass PMID to

INT B4 O Host Interface Status Output. INT is a low voltage open drain output used to signal charge status to the host

CD B5 O Hardware Disable Input. Connect CD to GND to enable charge. Drive CD high to disable charge and place

SW C1, C2, O Inductor Connection. Connect the switched side of the inductor to SW.

C3

PSEL C4 I USB Source Detection Input. Drive PSEL high to indicate a USB source is connected to the input and the PC

STAT C5 O Status Output. STAT is an open drain output that is pulled low during charging. When charging is complete or

PGND D1, D2, Power ground. Connect to the ground plane for the circuit.

D3

DCOUT D4, D5 O Accessory Power Output. DCOUT is connected to the battery through an internal pass FET. When enabled

CSIN E1 I Charge Current-Sense Input. Battery current is sensed via the voltage drop across an external sense resistor.

Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 7

capacitor.

BOOT pin to SW pin to supply the gate drive for the high side MOSFET.

PGND with a minimum of 3.3µF ceramic capacitor. Use caution when connecting an external load to PMID.
The PMID output is not current limited. Any short on PMID will result in damage to the IC.

processor. INT is pulled low during charging. When charging is complete or when charging is disabled, INT is
high impedance. When a fault occurs, a 128µs pulse is sent out as an interrupt for the host. INT is
enabled/disabled using the EN_STAT bit in the control register. Connect INT to a logic rail through a 10kΩ
resistor to communicate with the host processor.

the bq24180 into high impedance mode. Toggling CD resets the safety timer when in DEFAULT mode, but
does not reset the timer when in host mode. CD is pulled to PGND through a 100kΩ internal resistor.

mode default values should be used. When PSEL is high, the IC starts up with a 100mA input current limit.
Drive PSEL low to indicate that an AC Adapter is connected to the input. When PSEL is low, the IC starts up
with no input current limit and a 1A charge current. PSEL has an internal 100kΩ pullup resistor.

when charging is disabled, STAT is high impedance. When a fault occurs, a 128µs pulse is sent out as an
interrupt for the host. STAT is enabled/disabled using the EN_STAT bit in the control register. Connect STAT
to a logic rail using an LED for visual indication or through a 10kΩ resistor to communicate with the host
processor.

through I2C, DCOUT is connected to the battery. When disabled, DCOUT is high-impedance. Bypass DCOUT
to PGND with at least a 1µF ceramic capacitor.

Bypass CSIN to PGND with a 0.1µF ceramic capacitor.

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SLUSA02 A –FEBRUARY 2010–REVISED FEBRUARY 2010

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PIN FUNCTIONS (continued)

NAME PIN NO. I/O DESCRIPTION

TS E2 I Battery Pack NTC Monitor. Connect TS to a 4.7kΩ NTC thermistor. During DEFAULT mode, when VTS>

DRV E3 O Gate Drive Supply. DRV is the supply for the gate drive of the internal MOSFETs. Bypass DRV to PGND with

CSOUT E4, E5 I Battery voltage and Current Sense Input. Connect to the positive terminal of the battery pack. CSOUT is also

V

or VTS<V

COLD

reported by the I2C interface. During host mode, the TS function is active, but does not affect charging. The

charging is suspended. If V

HOT

HOT

< VTS< V

charging current is reduced. The faults are

WARM

faults are only reported by the I2C interface.

a 1µF ceramic capacitor. DRV may be used to drive external loads up to 10mA. DRV is active whenever the
input is connected.

the supply for the DCOUT output. Bypass CSOUT to PGND with 1µF ceramic capacitor.

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VBUS

VBUS

GND

HOST

bq24180

SW

PSEL

SCL

DCOUT

C1

1 µF

C2

10 µF

C3

4.7 µF

R3

4 kW

SYSTEM

PMID

SDA

D+

D-

USBPHY

BOOT

PGND

CSIN

CSOUT

VAUX

STAT

POWERFOR
ACCESSORY

C4

10 nF

C6

1 µF

C5

0.1 µF

RSNS
68 mW

R1

10kW

R2

VBUS

TS

TEMP

PACK+

PACK-

DRV

C7

1 µF

VBUS

INT

R4

C8

1µF

CD

HardwareDisable

10kW

10kW

bq24180

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TYPICAL APPLICATION CIRCUITS

VBUS = 5V, I

IN_LIMIT

12 seconds watchdog

= 500mA, I

CHARGE

= 1A, V

SLUSA02 A –FEBRUARY 2010–REVISED FEBRUARY 2010

= 3.5--4.44V (Adjustable), Safety Timer = 27 minute default w/

BAT

Figure 2. I2C Controlled 1-Cell USB Charger Application Circuit

Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 9

Product Folder Link(s): bq24180

t-Time-4ms/div

V

VBUS

V

BAT

I

OUT

V

INT/ STAT

5V/div

500mA/div

5V/div

2V/div

“NoBattery” FaultInterrupt

V

BAT

I

OUT

V

INT/ STAT

5V/div

200mA/div

2V/div

t-Time-2s/div

t-Time-4ms/div

V

VBUS

V

INT/ STAT

20mA/div

1V/div

2V/div

V

VBUS

<3.8V

"Faulty Adapter"FaultInterrupt

I

VBUS

t-Time-4ms/div

V

VBUS

V

BAT

I

OUT

V

INT/ STAT

5V/div

500mA/div

5V/div

2V/div

V

VBUS

V

INT/ STAT

20mA/div

1V/div

2V/div

t-Time-1s/div

I

VBUS

"Faulty Adapter"FaultInterrupt

V

SW

I

L

500mA/div

2V/div

t-Time-2 s/divm

V =5V,
V =3.6V

VBUS

BAT

bq24180

SLUSA02 A –FEBRUARY 2010–REVISED FEBRUARY 2010

TYPICAL CHARACTERISTICS

Figure 3. Adapter Insertion Figure 4. Battery Insertion/Removal

www.ti.com

Figure 5. PWM Charging Waveforms Figure 6. Faulty Adapter Detection

Figure 7. Faulty Adapter Detection Figure 8. Cycle by Cycle Current Limit

(Showing Continuous Detection)

Product Folder Link(s): bq24180

10 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated

I

VBUS

V

SW

V

BAT

1V/div

200mA/div

2V/div

t-Time-400 s/divm

I

VBUS

V

SW

1V/div

200mA/div

2V/div

t-Time-400 s/divm

V

BAT

V

SCL

I

OUT

200mA/div

1V/div

t-Time-200 s/divm

I

VBUS

V

SW

V

BAT

1V/div

200mA/div

2V/div

t-Time-400 s/divm

V

PSEL

V

BAT

200mA/div

1V/div

2V/div

t-Time-1ms/div

I

VBUS

V

VBUS

V

BAT

50mA/div

2V/div

1V/div

t-Time-10ms/div

I

VBUS

Faulty Adapter
Detection

bq24180

www.ti.com

SLUSA02 A –FEBRUARY 2010–REVISED FEBRUARY 2010

TYPICAL CHARACTERISTICS (continued)

Figure 9. Input Current Limit Transition Figure 10. Input Current Limit Transition

USB500 to USB100 USB100 to USB500

Figure 11. Input Current Limit Transition Figure 12. Charge Current Transition

USB500 to 750mA

Figure 13. Startup Into Default Mode Figure 14. PSEL Transition

No Battery Connected

Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 11

Product Folder Link(s): bq24180

550mA to 1.05A Using I2C

I

DCOUT

V

DCOUT

500mA/div

1V/div

t-Time-4ms/div

R =11 to1 ,
V =4V

LOAD

BAT

W W

I

VBUS

V

CD

V

BAT

1V/div

200mA/div

2V/div

t-Time-10ms/div

I

DCOUT

V

DCOUT

500mA/div

1V/div

t-Time-2ms/div

I

SW

I

OUT

5V/div

500mA/div

10V/div

t-Time-10 s/divm

V

VBUS

V

VBUS

=5.5Vto17V

V

SW

5V/div

500mA/div

5V/div

t-Time-10 s/divm

V

VBUS

I

OUT

TrickleCharge

USB100

V

VBUS

=5.5Vto10.5V

100

150

200

250

300

350

400

-40 -20 0 20 40 60 80 100 120 140

V -V

DO(VBUS-DRV)

T -Free-AirTemperature-°C

A

V =5V,
I =1 A,
I =10mA

VBUS

VBUS

DRV

bq24180

SLUSA02 A –FEBRUARY 2010–REVISED FEBRUARY 2010

TYPICAL CHARACTERISTICS (continued)

Figure 15. Enable/Disable Using CD Figure 16. DCOUT OCP Response

www.ti.com

Figure 17. Hotplug 1000µF Capacitor into DCOUT Figure 18. OVP Response

12 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated

Figure 19. VINHIGH Response Figure 20. DRV Dropout vs T

A

Product Folder Link(s): bq24180

V

VBUS

V

DRV

2V/div

t-Time-2ms/div

2V/div

V

VBUS

=0Vto5.5Vto0V

I

DRV

10mA/div

t-Time-20 s/divm

V

DRV

5.1VOffset

10mV/div

0

10

20

30

40

50

60

70

80

90

100

0.01 0.1 1 10

Current- A

Efficiency-%

V

VBUS

=5V

V =3.5V

OUT

V =4.45V

OUT

5.05

5.07

5.09

5.11

5.13

5.15

0 1 2 3 4 5 6 7 8 9 10

I -mA

DRV

V -V

DRV

V =5.5V

BUS

bq24180

www.ti.com

SLUSA02 A –FEBRUARY 2010–REVISED FEBRUARY 2010

TYPICAL CHARACTERISTICS (continued)

Figure 21. DRV Startup/Shutdown Figure 22. DRV Load Transient

Figure 23. DRV Load Regulation Figure 24. Charger Efficiency

Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 13

Product Folder Link(s): bq24180