TEXAS INSTRUMENTS bq20z75 Technical data

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bq20z75

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SBS 1.1-COMPLIANT GAS GAUGE AND PROTECTION-ENABLED IC

WITH IMPEDANCE TRACK™

FEATURES

• Next Generation Patented Impedance Track™

Technology accurately Measures Available Charge in Li-Ion and Li-Polymer Batteries

– Better than 1% Error Over Lifetime of the

Battery

– Instant Accuracy – No Learning Cycle

Required

• Supports the Smart Battery Specification

SBS V1.1

• Flexible Configuration for 2 to 4 Series Li-Ion

and Li-Polymer Cells

• Powerful 8-Bit RISC CPU With Ultra-Low

Power Modes

• Full Array of Programmable Protection

Features – Voltage, Current and Temperature

• Supports SHA-1 Authentication

• small 38-Pin TSSOP (DBT) Package

APPLICATIONS

• Notebook PCs

• Medical and Test Equipment

• Portable Instrumentation

SLUS723 – JULY 2007

DESCRIPTION

The bq20z75 SBS-compliant gas gauge and protection IC is a single IC solution designed for battery-pack or in-system installation. The bq20z75 measures and maintains an accurate record of available charge in Li-ion or Li-polymer batteries using its integrated high-performance analog peripherals, monitors capacity change, battery impedance, open-circuit voltage, and other critical parameters of the battery pack as well and reports the information to the system host controller over a serial-communication bus. Together with the integrated analog front-end (AFE) short-circuit and overload protection the bq20z75 maximizes functionality, safety and minimize external component count, cost and size in smart battery circuits.

The implemented Impedance Track™ gas gauging technology continuously analyzes the battery impedance, resulting in superior gas-gauging accuracy. This enables remaining capacity to be calculated with discharge rate, temperature, and cell aging all accounted for during each stage of every cycle with high accuracy.

AVAILABLE OPTIONS

PACKAGE

– 40 ° C to

85 ° C

(1) A single tube quantity is 50 units. (2) A single reel quantity is 2000 units

38-PIN TSSOP (DBT) 20-PIN TSSOP (DBT)

Tube Tape and Reel

bq20z75DBT

(1)

bq20z75DBTR

(2)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 IMPEDANCE TRACK is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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Coloumb

Counter

HWOver Current &

ShortCircuit

Protection

CellVoltage

Multiplexer

N-ChannelFET

Drive

PreChargeFET

& PGODDrive

PowerMode

Control

SMBD

GSRN

GSRP

ASRN

ASRP

GPOD

ZVCHG

CHG

DSG

VC5

VC4

VC3

VC2

VC1

¯¯¯¯¯

SMBC ¯¯¯¯¯¯

¯¯¯¯

CellBalancing

Temperature

Measurement

DataFlash

Memory

SMB 1.1

Impedance

Track™

GasGauging

SHA-1

Authentication

Over- & Under-

Voltage

Protection

Voltage

Measurement

OverCurrent

Protection

Oscillator

Charging Algorithm

FuseBlow

Detectionand

Logic

Over

Temperature

Protection

SAFE

PFIN

TS2

TS1

TOUT

PMS

Watchdog

Regulators

RESET

ALERT

¯¯¯¯¯¯

REG33

REG25

VCELL+

BAT

PACK

VSS

MSRT

RBI

SystemControl AFEHWControl

Pack -

RSNS 5mΩ – 20mΩ typical

Pack +

SMBC

SMBD

bq20z75

GNDVC4

VC3

VC2

VC1

VDD

OUT

bq294xx

DSG

PACK

VCC

ALERT

ZVCHG

PRES

PMS

TS2

VSS

PFIN

REG33

SAFE

TOUT

SMBD

18 19

VCELL+

SMBC

CHG

BAT

VC1

VSS

VC2

RBI

VC3

REG25

VC4

VSS

VC5

MRST

ASRP

GSRN

ASRN

GSRP

RESET

VSS VSS

GPOD

TS1

bq20z75

SLUS723 – JULY 2007

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

SYSTEM PARTITIONING DIAGRAM

TSSOP (PW)

(TOP VIEW)

Product Folder Link(s): bq20z75

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SLUS723 – JULY 2007

TERMINAL FUNCTIONS

TERMINAL

NO. NAME

1 DSG O High side N-channel discharge FET gate drive 2 PACK IA, P

3 VCC P 4 ZVCHG O P-channel pre-charge FET gate drive 5 GPOD OD

6 PMS I connected at CHG pin. Connect to VSS to disable 0V pre-charge using charge FET connected at

7 VSS P Negative device power supply input. Connect all VSS pins together for operation of device 8 REG33 P 3.3V regulator output. Connect at least a 2.2 µ F capacitor to REG33 and VSS 9 TOUT P Termistor bias supply output

10 VCELL+ - Internal cell voltage multiplexer and amplifier output. Connect a 0.1 µ F capacitor to VCELL+ and VSS 11 ALERT I/OD 12 PRES I/OD System / Host present input. Pull up to TOUT

13 TS1 IA Temperature sensor 1 input 14 TS2 IA Temperature sensor 2 input 15 PFIN I/OD Fuse blow detection input 16 SAFE I/OD blow fuse signal output 17 SMBD I/OD SMBus data line 18 SMBC I/OD SMBus clock line 19 NC - Not Connected 20 VSS P Negative device power supply input. Connect all VSS pins together for operation of device. 21 VSS P Negative device power supply input. Connect all VSS pins together for operation of device. 22 GSRP IA Coulomb counter differential input. Connect to one side of the sense resistor 23 GSRN IA Coulomb counter differential input. Connect to one side of the sense resistor 24 MRST I Reset input for internal CPU core. connect to RESET for correct operation of device. 25 VSS P Negative device power supply input. Connect all VSS pins together for operation of device. 26 REG25 P 2.5V regulator output. Connect at least a 1 µ F capacitor to REG25 and VSS

27 RBI P 28 VSS P Negative device power supply input. Connect all VSS pins together for operation of device

29 RESET O Reset output. Connect to MSRT. 30 ASRN IA Short-circuit and overload detection differential input 31 ASRP IA Short-circuit and overload detection differential input

32 VC5 IA,P

33 VC4 IA,P

34 VC3 IA,P

35 VC2 IA,P and the negative voltage of the highest cell in 4 cell applications. Connect to VC3 in 2 cell stack

36 VC1 IA,P

(1)

I/O

Battery pack input voltage sense input. It also serves as device wake up when device is in shutdown mode.

Positive device supply input. Connect to the center connection of the CHG FET and DSG FET to ensure device supply either from battery stack or battery pack input

High voltage general purpose open drain output. Can be configured to be used in pre-charge condition

Pre-charge mode setting input. Connect to PACK to enable 0v pre-charge using charge FET CHG pin.

Alert output. In case of short circuit condition, overload condition and watchdog time out this pin will be triggered.

RAM backup input. Connect a capacitor to this pin and VSS to protect loss of RAM data in case of short-circuit condition

Cell voltage sense input and cell balancing input for the negative voltage of the bottom cell in cell stack.

Cell voltage sense input and cell balancing input for the positive voltage of the bottom cell and the negative voltage of the second lowest cell in cell stack.

Cell voltage sense input and cell balancing input for the positive voltage of the second lowest cell in cell stack and the negative voltage of the second highest cell in 4 cell applications.

Cell voltage sense input and cell balancing input for the positive voltage of the second highest cell applications

Cell voltage sense input and cell balancing input for the positive voltage of the highest cell in cell stack in 4 cell applications. Connect to VC2 in 3 or 2 cell stack applications

DESCRIPTION

bq20z75

(1) I = Input, IA = Analog input, I/O = Input/output, I/OD = Input/Open-drain output, O = Output, OA = Analog output, P = Power

Product Folder Link(s): bq20z75

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bq20z75

SLUS723 – JULY 2007

TERMINAL FUNCTIONS (continued)

TERMINAL

NO. NAME

37 BAT O Battery stack voltage sense input 38 CHG O High side N-channel charge FET gate drive

(1)

I/O

DESCRIPTION

Absolute Maximum Ratings

Over Operating Free-Air Temperature (unless otherwise noted)

DESCRIPTION PIN UNIT

MAX

OUT

stg

sld

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

Supply voltage range VBAT, VCC – 0.3V to 34V

Input voltage range PFIN, SMBD, SMBC, – 0.3V to 6.0V

Output voltage range TOUT, ALERT, – 0.3 V to 6.0V

Maximum combined sink current for input pins PRES, PFIN, SMBD, 50mA

Operating free-air temperature range – 40 ° C to 85 ° C Functional temperature – 40 ° C to 100 ° C Storage temperature range – 65 ° C to 150 ° C Lead temperature (soldering, 10s) 300 ° C

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(1)

PACK, PMS – 0.3V to 34V VC(n)-VC(n+1); n = 1, – 0.3V to 8.5V

2, 3, 4 VC1, VC2, VC3, VC4 – 0.3V to 34V VC5 – 0.3V to 1.0V

DISP TS1, TS2, VCELL+, – 0.3 V to V

PRES; ALERT MRST, GSRN, GSRP, – 0.3 V to V

RBI ASRN, ASRP – 1.0V to 1.0V DSG, CHG, GPOD – 0.3V to 34V ZVCHG – 0.3V to V

REG33, RESET – 0.3 V to 7.0V REG25, SAFE, TOUT – 0.3V to 2.75V

SMBC

REG25

+ 0.3 V

BAT

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bq20z75

SLUS723 – JULY 2007

Recommeded Operating Conditions

over operating free-air temperature range (unless otherwise noted)

PARAMETER PIN MIN NOM MAX UNIT

SUP

V Minimum startup voltage VCC, BAT, PACK 5.5 V

STARTUP

GPOD

REG25

REG33

VCELL+

PACK

(1) Use external resitor to limit current to GPOD to 1mA in high voltage application. (2) External resistor to limit inrush current PACK pin required.

Supply voltage VCC, VBAT 4.5 25 V

VC(n) – VC(n+1); n = 1,2,3,4 0 5 V VC1, VC2, VC3, VC4 0 V

SUP

Input Voltage Range VC5 0 0.5 V

ASRN, ASRP – 0.5 0.5 V

PACK, PMS 0 25 V Output Voltage Range GPOD 0 25 V Drain Current

(1)

GPOD 1 mA

2.5V LDO Capacitor REG25 1 µF

3.3V LDO Capacitor REG33 2.2 µF Cell Voltage Output Capacitor VCELL+ 0.1 µF PACK input block resistor

(2)

PACK 1 k Ω

Electrical Characteristics

over operating free-air temperature range (unless otherwise noted), TA= – 40 ° C to 85 ° C, V 14V, C

SUPPLY CURRENT

NORMAL

SLEEP

SHUTDOW

SHUTDOWN WAKE; TA= 25 ° C (unless otherwise noted)

PACK

SRx WAKE FROM SLEEP; TA= 25 ° C (unless otherwise noted)

WAKE

WAKE_A

WAKE_T

WAKE

POWER-ON RESET

IT –

= 1µF, C

REG25

= 2.2µF; typical values at TA= 25 ° C (unless otherwise noted)

REG33

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Firmware running 550 µA Sleep Mode CHG FET on; DSG FET on 124 µA

CHG FET off; DSG FET on 90 µA CHG FET off; DSG FET off 52 µA

Shutdown Mode 0.1 1 µA

Shutdown exit at V

STARTUP

threshold 1 µA

Positive or negative wake threshold with

1.00 mV, 2.25 mV, 4.5 mV and 9 mV 1.25 10 mV programmable options

= 1.0mV;

WAKE

IWAKE=0, RSNS1=0, RSNS0=1; V

= 2.25mV;

WAKE

IWAKE =1, RSNS1=0, RSNS0=1; – 0.8 0.8

Accuracy of V

WAKE

IWAKE =0, RSNS1=1, RSNS0=0; V

= 4.5mV;

WAKE

IWAKE =1, RSNS1=1, RSNS0=1; – 1.0 1.0 IWAKE =0, RSNS1=1, RSNS0=0;

= 9mV;

WAKE

IWAKE =1, RSNS1=1, RSNS0=1;

Temperature drift of V

accuracy 0.5 %/ ° C

WAKE

Time from application of current and wake of bq20z75

Negative-going voltage input Voltage at REG25 pin 1.70 1.80 1.90 V

= 2.41 V to 2.59 V, V

REG25

– 0.7 0.7

– 1.4 1.4

1 10 ms

BAT

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bq20z75

SLUS723 – JULY 2007

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted), TA= – 40 ° C to 85 ° C, V 14V, C

hys

RST

WATCHDOG TIMER

WDTINT

WDWT

2.5V LDO; I

REG25

Δ V

REG25

TEMP

Δ V

REG25L

INE

Δ V

REG25L

OAD

REG25MA

3.3V LDO; I

REG33

Δ V

REG33

TEMP

Δ V

REG33L

INE

Δ V

REG33L

OAD

REG33MA

THERMISTOR DRIVE

TOUT

DS(ON)

VCELL+ HIGH VOLTAGE TRANSLATION

VCELL+O

VCELL+R

VCELL+P

ACK

VCELL+B

CMMR Common mode rejection ratio VCELL+ 40 dB

K Cell scale factor

= 1µF, C

REG25

= 2.2µF; typical values at TA= 25 ° C (unless otherwise noted)

REG33

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Hysteresis V RESET active low time 100 250 560 µs

– V

IT+

IT –

active low time after power up or watchdog reset

Watchdog start up detect time 250 500 1000 ms Watchdog detect time 50 100 150 µs

REG33OUT

Regulator output voltage 2.41 2.5 2.59 V Regulator output change with I

temperature 100 ° C Line regulation 3 10 mV

Load Regulation mV

Current Limit 5 40 75 mA

REG25OUT

Regulator output voltage 3 3.3 3.6 V Regulator output change with I

temperature 100 ° C Line regulation 3 17 mV

Load Regulation mV

Current Limit mA

Output voltage I TOUT pass element resistance 50 100 Ω

= 0mA; TA= 25 ° C (unless otherwise noted)

4.5 < VCC or BAT < 25V; I ≤ 16mA; TA= – 40 ° C to 100 ° C

REG25OUT

= 2mA; TA= – 40 ° C to

5.4 < VCC or BAT < 25V; I = 2mA

0.2mA ≤ I

REG25OUT REG25OUT

REG25OUT

≤ 2mA 7 25 ≤ 16mA 15 50

drawing current until REG25 = 2V to 0V

4.5 < VCC or BAT < 25V; I ≤ 25mA; TA= – 40 ° C to 100 ° C

REG33OUT

= 2mA; TA= – 40 ° C to

5.4 < VCC or BAT < 25V; I = 2mA

0.2mA ≤ I

REG33OUT REG33OUT

REG33OUT

≤ 2mA 7 17 ≤ 25mA 40 100

drawing current until REG33 = 3V 25 100 145 short REG33 to VSS, REG33 = 0V 12 65

= 0mA; TA= 25 ° C V

TOUT

= 1mA; R

TOUT

) / 1mA; TA= – 40 ° C to 100 ° C

TOUT

= (V

DS(ON)

–

REG25

VC(n) – VC(n+1) = 0V; TA= – 40 ° C to 100 ° C

VC(n) – VC(n+1) = 4.5V; TA= – 40 ° C to 100 ° C

Translation output 0.965 0.975 0.985 V

internal AFE reference voltage ; TA= – 40 ° C to 100 ° C

Voltage at PACK pin; TA= – 40 ° C to 0.98*V 100 ° C

Voltage at BAT pin; TA= – 40 ° C to 0.98*V 100 ° C 18

K= {VCELL+ output (VC5=0V; VC4=4.5V) – VCELL+ output 0.147 0.150 0.153 (VC5=0V; VC4=0V)}/4.5

K= {VCELL+ output (VC2=13.5V; VC1=18V) – VCELL+ output 0.147 0.150 0.153 (VC5=13.5V; VC1=13.5V)}/4.5

= 2.41 V to 2.59 V, V

REG25

50 150 250 mV

± 0.2 %

REG25

0.950 0.975 1

0.275 0.3 0.375

PAC

/18

BAT

PACK

/ 1.02*V

BAT

1.02*V

/18

BAT

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted), TA= – 40 ° C to 85 ° C, V 14V, C

VCELL+OU

VCELL+O

VCnL

CELL BALANCING

BAL

HARDWARE SHORT CIRCUIT AND OVERLOAD PROTECTION; TA= 25 ° C (unless otherwise noted)

(OL)

(SCC)

(SCD)

FET DRIVE CIRCUIT; TA= 25 ° C (unless otherwise noted)

DSGON

CHGON

DSGOFF

CHGOFF

ZVCHG

LOGIC; TA= – 40 ° C to 100 ° C (unless otherwise noted)

PULLUP

LOGIC SMBC, SMBD, PFIN, PRES, SAFE, ALERT

= 1µF, C

REG25

= 2.2µF; typical values at TA= 25 ° C (unless otherwise noted)

REG33

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Drive Current to VCELL+ capacitor 12 18 µ A

CELL offset error – 18 – 1 18 mV

VC(n) – VC(n+1) = 0V; VCELL+ = 0V; TA= – 40 ° C to 100 ° C

CELL ouput (VC2 = VC1 = 18V) – CELL output (VC2 = VC1 = 0V)

VC(n) pin leakage current VC1, VC2, VC3, VC4, VC5 = 3V – 1 0.01 1 µ A

for internal FET switch at V

internal cell balancing FET resistance 200 400 600 Ω

OL detection threshold voltage accuracy V

SCC detection threshold voltage accuracy

SCD detection threshold voltage accuracy

DS(on)

= 2V; TA= 25 ° C

= 25mV (min) 15 25 35

= 100mV; RSNS = 0, 1 90 100 110 mV

= 205mV (max) 185 205 225

= 50mV (min) 30 50 70

SCC

= 200mV; RSNS = 0, 1 180 200 220 mV

SCC

= 475mV (max) 428 475 523

SCC

= – 50mV (min) – 30 – 50 – 70

SCD

= – 200mV; RSNS = 0, 1 – 180 – 200 – 220 mV

SCD

= – 475mV (max) – 428 – 475 – 523

SCD

Delay time accuracy ± 15.25 µ s Protection circuit propagation delay 50 µ s

= V

– V

; V

DSG pin output on voltage 10M Ω ;DSG and CHG on; TA= 8 12 16 V

DSGON

DSG

PACK

– 40 ° C to 100 ° C V

= V

– V

; V

CHG pin output on voltage 10M Ω ;DSG and CHG on; TA= 8 12 16 V

CHGON

CHG

BAT

– 40 ° C to 100 ° C DSG pin output off voltage V CHG pin output off voltage V

CL=4700pF; V Rise time µ s

CL=4700pF; V

CL=4700pF; V Fall time µ s

≤ V

CL=4700pF; V

≤ V

= V

DSGOFF CHGOFF

+ 1V

PACK

+ 1V

BAT

– V

DSG

PACK

= V

– V

CHG

BAT

PACK

BAT PACK

BAT

≤ DSG ≤ V

≤ CHG ≤ V

+ V

DSGON

+ V

CHGON

PACK

+ 4V 400 1000

BAT

≤ DSG

≤ CHG

ZVCHG clamp voltage BAT = 4.5V 3.3 3.5 3.7 V

Internal pullup resistance k Ω

ALERT 60 100 200

RESET 1 3 6

ALERT 0.2 Logic low output voltage level 0.4 V

RESET; V

RESET

GPOD; I

= 7V; V

BAT

= 200 µ A

= 50 µ A 0.6

GPOD

= 1.5V;

REG25

High-level input voltage 2.0 V Low-level input voltage 0.8 V

= 2.41 V to 2.59 V, V

REG25

400 1000

40 200

bq20z75

SLUS723 – JULY 2007

0.2 V

BAT

Product Folder Link(s): bq20z75

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