TEXAS INSTRUMENTS bq20z75 Technical data

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bq20z75

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SBS 1.1-COMPLIANT GAS GAUGE AND PROTECTION-ENABLED IC

WITH IMPEDANCE TRACK™

FEATURES

• Next Generation Patented Impedance Track™

Technology accurately Measures Available Charge in Li-Ion and Li-Polymer Batteries

– Better than 1% Error Over Lifetime of the

Battery

– Instant Accuracy – No Learning Cycle

Required

• Supports the Smart Battery Specification

SBS V1.1

• Flexible Configuration for 2 to 4 Series Li-Ion

and Li-Polymer Cells

• Powerful 8-Bit RISC CPU With Ultra-Low

Power Modes

• Full Array of Programmable Protection

Features – Voltage, Current and Temperature

• Supports SHA-1 Authentication

• small 38-Pin TSSOP (DBT) Package

APPLICATIONS

• Notebook PCs

• Medical and Test Equipment

• Portable Instrumentation

SLUS723 – JULY 2007

DESCRIPTION

The bq20z75 SBS-compliant gas gauge and protection IC is a single IC solution designed for battery-pack or in-system installation. The bq20z75 measures and maintains an accurate record of available charge in Li-ion or Li-polymer batteries using its integrated high-performance analog peripherals, monitors capacity change, battery impedance, open-circuit voltage, and other critical parameters of the battery pack as well and reports the information to the system host controller over a serial-communication bus. Together with the integrated analog front-end (AFE) short-circuit and overload protection the bq20z75 maximizes functionality, safety and minimize external component count, cost and size in smart battery circuits.

The implemented Impedance Track™ gas gauging technology continuously analyzes the battery impedance, resulting in superior gas-gauging accuracy. This enables remaining capacity to be calculated with discharge rate, temperature, and cell aging all accounted for during each stage of every cycle with high accuracy.

AVAILABLE OPTIONS

PACKAGE

– 40 ° C to

85 ° C

(1) A single tube quantity is 50 units. (2) A single reel quantity is 2000 units

38-PIN TSSOP (DBT) 20-PIN TSSOP (DBT)

Tube Tape and Reel

bq20z75DBT

(1)

bq20z75DBTR

(2)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 IMPEDANCE TRACK is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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Coloumb

Counter

HWOver Current &

ShortCircuit

Protection

CellVoltage

Multiplexer

N-ChannelFET

Drive

PreChargeFET

& PGODDrive

PowerMode

Control

SMBD

GSRN

GSRP

ASRN

ASRP

GPOD

ZVCHG

CHG

DSG

VC5

VC4

VC3

VC2

VC1

¯¯¯¯¯

SMBC ¯¯¯¯¯¯

¯¯¯¯

CellBalancing

Temperature

Measurement

DataFlash

Memory

SMB 1.1

Impedance

Track™

GasGauging

SHA-1

Authentication

Over- & Under-

Voltage

Protection

Voltage

Measurement

OverCurrent

Protection

Oscillator

Charging Algorithm

FuseBlow

Detectionand

Logic

Over

Temperature

Protection

SAFE

PFIN

TS2

TS1

TOUT

PMS

Watchdog

Regulators

RESET

ALERT

¯¯¯¯¯¯

REG33

REG25

VCELL+

BAT

PACK

VSS

MSRT

RBI

SystemControl AFEHWControl

Pack -

RSNS 5mΩ – 20mΩ typical

Pack +

SMBC

SMBD

bq20z75

GNDVC4

VC3

VC2

VC1

VDD

OUT

bq294xx

DSG

PACK

VCC

ALERT

ZVCHG

PRES

PMS

TS2

VSS

PFIN

REG33

SAFE

TOUT

SMBD

18 19

VCELL+

SMBC

CHG

BAT

VC1

VSS

VC2

RBI

VC3

REG25

VC4

VSS

VC5

MRST

ASRP

GSRN

ASRN

GSRP

RESET

VSS VSS

GPOD

TS1

bq20z75

SLUS723 – JULY 2007

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

SYSTEM PARTITIONING DIAGRAM

TSSOP (PW)

(TOP VIEW)

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SLUS723 – JULY 2007

TERMINAL FUNCTIONS

TERMINAL

NO. NAME

1 DSG O High side N-channel discharge FET gate drive 2 PACK IA, P

3 VCC P 4 ZVCHG O P-channel pre-charge FET gate drive 5 GPOD OD

6 PMS I connected at CHG pin. Connect to VSS to disable 0V pre-charge using charge FET connected at

7 VSS P Negative device power supply input. Connect all VSS pins together for operation of device 8 REG33 P 3.3V regulator output. Connect at least a 2.2 µ F capacitor to REG33 and VSS 9 TOUT P Termistor bias supply output

10 VCELL+ - Internal cell voltage multiplexer and amplifier output. Connect a 0.1 µ F capacitor to VCELL+ and VSS 11 ALERT I/OD 12 PRES I/OD System / Host present input. Pull up to TOUT

13 TS1 IA Temperature sensor 1 input 14 TS2 IA Temperature sensor 2 input 15 PFIN I/OD Fuse blow detection input 16 SAFE I/OD blow fuse signal output 17 SMBD I/OD SMBus data line 18 SMBC I/OD SMBus clock line 19 NC - Not Connected 20 VSS P Negative device power supply input. Connect all VSS pins together for operation of device. 21 VSS P Negative device power supply input. Connect all VSS pins together for operation of device. 22 GSRP IA Coulomb counter differential input. Connect to one side of the sense resistor 23 GSRN IA Coulomb counter differential input. Connect to one side of the sense resistor 24 MRST I Reset input for internal CPU core. connect to RESET for correct operation of device. 25 VSS P Negative device power supply input. Connect all VSS pins together for operation of device. 26 REG25 P 2.5V regulator output. Connect at least a 1 µ F capacitor to REG25 and VSS

27 RBI P 28 VSS P Negative device power supply input. Connect all VSS pins together for operation of device

29 RESET O Reset output. Connect to MSRT. 30 ASRN IA Short-circuit and overload detection differential input 31 ASRP IA Short-circuit and overload detection differential input

32 VC5 IA,P

33 VC4 IA,P

34 VC3 IA,P

35 VC2 IA,P and the negative voltage of the highest cell in 4 cell applications. Connect to VC3 in 2 cell stack

36 VC1 IA,P

(1)

I/O

Battery pack input voltage sense input. It also serves as device wake up when device is in shutdown mode.

Positive device supply input. Connect to the center connection of the CHG FET and DSG FET to ensure device supply either from battery stack or battery pack input

High voltage general purpose open drain output. Can be configured to be used in pre-charge condition

Pre-charge mode setting input. Connect to PACK to enable 0v pre-charge using charge FET CHG pin.

Alert output. In case of short circuit condition, overload condition and watchdog time out this pin will be triggered.

RAM backup input. Connect a capacitor to this pin and VSS to protect loss of RAM data in case of short-circuit condition

Cell voltage sense input and cell balancing input for the negative voltage of the bottom cell in cell stack.

Cell voltage sense input and cell balancing input for the positive voltage of the bottom cell and the negative voltage of the second lowest cell in cell stack.

Cell voltage sense input and cell balancing input for the positive voltage of the second lowest cell in cell stack and the negative voltage of the second highest cell in 4 cell applications.

Cell voltage sense input and cell balancing input for the positive voltage of the second highest cell applications

Cell voltage sense input and cell balancing input for the positive voltage of the highest cell in cell stack in 4 cell applications. Connect to VC2 in 3 or 2 cell stack applications

DESCRIPTION

bq20z75

(1) I = Input, IA = Analog input, I/O = Input/output, I/OD = Input/Open-drain output, O = Output, OA = Analog output, P = Power

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bq20z75

SLUS723 – JULY 2007

TERMINAL FUNCTIONS (continued)

TERMINAL

NO. NAME

37 BAT O Battery stack voltage sense input 38 CHG O High side N-channel charge FET gate drive

(1)

I/O

DESCRIPTION

Absolute Maximum Ratings

Over Operating Free-Air Temperature (unless otherwise noted)

DESCRIPTION PIN UNIT

MAX

OUT

stg

sld

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

Supply voltage range VBAT, VCC – 0.3V to 34V

Input voltage range PFIN, SMBD, SMBC, – 0.3V to 6.0V

Output voltage range TOUT, ALERT, – 0.3 V to 6.0V

Maximum combined sink current for input pins PRES, PFIN, SMBD, 50mA

Operating free-air temperature range – 40 ° C to 85 ° C Functional temperature – 40 ° C to 100 ° C Storage temperature range – 65 ° C to 150 ° C Lead temperature (soldering, 10s) 300 ° C

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(1)

PACK, PMS – 0.3V to 34V VC(n)-VC(n+1); n = 1, – 0.3V to 8.5V

2, 3, 4 VC1, VC2, VC3, VC4 – 0.3V to 34V VC5 – 0.3V to 1.0V

DISP TS1, TS2, VCELL+, – 0.3 V to V

PRES; ALERT MRST, GSRN, GSRP, – 0.3 V to V

RBI ASRN, ASRP – 1.0V to 1.0V DSG, CHG, GPOD – 0.3V to 34V ZVCHG – 0.3V to V

REG33, RESET – 0.3 V to 7.0V REG25, SAFE, TOUT – 0.3V to 2.75V

SMBC

REG25

+ 0.3 V

BAT

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bq20z75

SLUS723 – JULY 2007

Recommeded Operating Conditions

over operating free-air temperature range (unless otherwise noted)

PARAMETER PIN MIN NOM MAX UNIT

SUP

V Minimum startup voltage VCC, BAT, PACK 5.5 V

STARTUP

GPOD

REG25

REG33

VCELL+

PACK

(1) Use external resitor to limit current to GPOD to 1mA in high voltage application. (2) External resistor to limit inrush current PACK pin required.

Supply voltage VCC, VBAT 4.5 25 V

VC(n) – VC(n+1); n = 1,2,3,4 0 5 V VC1, VC2, VC3, VC4 0 V

SUP

Input Voltage Range VC5 0 0.5 V

ASRN, ASRP – 0.5 0.5 V

PACK, PMS 0 25 V Output Voltage Range GPOD 0 25 V Drain Current

(1)

GPOD 1 mA

2.5V LDO Capacitor REG25 1 µF

3.3V LDO Capacitor REG33 2.2 µF Cell Voltage Output Capacitor VCELL+ 0.1 µF PACK input block resistor

(2)

PACK 1 k Ω

Electrical Characteristics

over operating free-air temperature range (unless otherwise noted), TA= – 40 ° C to 85 ° C, V 14V, C

SUPPLY CURRENT

NORMAL

SLEEP

SHUTDOW

SHUTDOWN WAKE; TA= 25 ° C (unless otherwise noted)

PACK

SRx WAKE FROM SLEEP; TA= 25 ° C (unless otherwise noted)

WAKE

WAKE_A

WAKE_T

WAKE

POWER-ON RESET

IT –

= 1µF, C

REG25

= 2.2µF; typical values at TA= 25 ° C (unless otherwise noted)

REG33

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Firmware running 550 µA Sleep Mode CHG FET on; DSG FET on 124 µA

CHG FET off; DSG FET on 90 µA CHG FET off; DSG FET off 52 µA

Shutdown Mode 0.1 1 µA

Shutdown exit at V

STARTUP

threshold 1 µA

Positive or negative wake threshold with

1.00 mV, 2.25 mV, 4.5 mV and 9 mV 1.25 10 mV programmable options

= 1.0mV;

WAKE

IWAKE=0, RSNS1=0, RSNS0=1; V

= 2.25mV;

WAKE

IWAKE =1, RSNS1=0, RSNS0=1; – 0.8 0.8

Accuracy of V

WAKE

IWAKE =0, RSNS1=1, RSNS0=0; V

= 4.5mV;

WAKE

IWAKE =1, RSNS1=1, RSNS0=1; – 1.0 1.0 IWAKE =0, RSNS1=1, RSNS0=0;

= 9mV;

WAKE

IWAKE =1, RSNS1=1, RSNS0=1;

Temperature drift of V

accuracy 0.5 %/ ° C

WAKE

Time from application of current and wake of bq20z75

Negative-going voltage input Voltage at REG25 pin 1.70 1.80 1.90 V

= 2.41 V to 2.59 V, V

REG25

– 0.7 0.7

– 1.4 1.4

1 10 ms

BAT

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SLUS723 – JULY 2007

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted), TA= – 40 ° C to 85 ° C, V 14V, C

hys

RST

WATCHDOG TIMER

WDTINT

WDWT

2.5V LDO; I

REG25

Δ V

REG25

TEMP

Δ V

REG25L

INE

Δ V

REG25L

OAD

REG25MA

3.3V LDO; I

REG33

Δ V

REG33

TEMP

Δ V

REG33L

INE

Δ V

REG33L

OAD

REG33MA

THERMISTOR DRIVE

TOUT

DS(ON)

VCELL+ HIGH VOLTAGE TRANSLATION

VCELL+O

VCELL+R

VCELL+P

ACK

VCELL+B

CMMR Common mode rejection ratio VCELL+ 40 dB

K Cell scale factor

= 1µF, C

REG25

= 2.2µF; typical values at TA= 25 ° C (unless otherwise noted)

REG33

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Hysteresis V RESET active low time 100 250 560 µs

– V

IT+

IT –

active low time after power up or watchdog reset

Watchdog start up detect time 250 500 1000 ms Watchdog detect time 50 100 150 µs

REG33OUT

Regulator output voltage 2.41 2.5 2.59 V Regulator output change with I

temperature 100 ° C Line regulation 3 10 mV

Load Regulation mV

Current Limit 5 40 75 mA

REG25OUT

Regulator output voltage 3 3.3 3.6 V Regulator output change with I

temperature 100 ° C Line regulation 3 17 mV

Load Regulation mV

Current Limit mA

Output voltage I TOUT pass element resistance 50 100 Ω

= 0mA; TA= 25 ° C (unless otherwise noted)

4.5 < VCC or BAT < 25V; I ≤ 16mA; TA= – 40 ° C to 100 ° C

REG25OUT

= 2mA; TA= – 40 ° C to

5.4 < VCC or BAT < 25V; I = 2mA

0.2mA ≤ I

REG25OUT REG25OUT

REG25OUT

≤ 2mA 7 25 ≤ 16mA 15 50

drawing current until REG25 = 2V to 0V

4.5 < VCC or BAT < 25V; I ≤ 25mA; TA= – 40 ° C to 100 ° C

REG33OUT

= 2mA; TA= – 40 ° C to

5.4 < VCC or BAT < 25V; I = 2mA

0.2mA ≤ I

REG33OUT REG33OUT

REG33OUT

≤ 2mA 7 17 ≤ 25mA 40 100

drawing current until REG33 = 3V 25 100 145 short REG33 to VSS, REG33 = 0V 12 65

= 0mA; TA= 25 ° C V

TOUT

= 1mA; R

TOUT

) / 1mA; TA= – 40 ° C to 100 ° C

TOUT

= (V

DS(ON)

–

REG25

VC(n) – VC(n+1) = 0V; TA= – 40 ° C to 100 ° C

VC(n) – VC(n+1) = 4.5V; TA= – 40 ° C to 100 ° C

Translation output 0.965 0.975 0.985 V

internal AFE reference voltage ; TA= – 40 ° C to 100 ° C

Voltage at PACK pin; TA= – 40 ° C to 0.98*V 100 ° C

Voltage at BAT pin; TA= – 40 ° C to 0.98*V 100 ° C 18

K= {VCELL+ output (VC5=0V; VC4=4.5V) – VCELL+ output 0.147 0.150 0.153 (VC5=0V; VC4=0V)}/4.5

K= {VCELL+ output (VC2=13.5V; VC1=18V) – VCELL+ output 0.147 0.150 0.153 (VC5=13.5V; VC1=13.5V)}/4.5

= 2.41 V to 2.59 V, V

REG25

50 150 250 mV

± 0.2 %

REG25

0.950 0.975 1

0.275 0.3 0.375

PAC

/18

BAT

PACK

/ 1.02*V

BAT

1.02*V

/18

BAT

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted), TA= – 40 ° C to 85 ° C, V 14V, C

VCELL+OU

VCELL+O

VCnL

CELL BALANCING

BAL

HARDWARE SHORT CIRCUIT AND OVERLOAD PROTECTION; TA= 25 ° C (unless otherwise noted)

(OL)

(SCC)

(SCD)

FET DRIVE CIRCUIT; TA= 25 ° C (unless otherwise noted)

DSGON

CHGON

DSGOFF

CHGOFF

ZVCHG

LOGIC; TA= – 40 ° C to 100 ° C (unless otherwise noted)

PULLUP

LOGIC SMBC, SMBD, PFIN, PRES, SAFE, ALERT

= 1µF, C

REG25

= 2.2µF; typical values at TA= 25 ° C (unless otherwise noted)

REG33

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Drive Current to VCELL+ capacitor 12 18 µ A

CELL offset error – 18 – 1 18 mV

VC(n) – VC(n+1) = 0V; VCELL+ = 0V; TA= – 40 ° C to 100 ° C

CELL ouput (VC2 = VC1 = 18V) – CELL output (VC2 = VC1 = 0V)

VC(n) pin leakage current VC1, VC2, VC3, VC4, VC5 = 3V – 1 0.01 1 µ A

for internal FET switch at V

internal cell balancing FET resistance 200 400 600 Ω

OL detection threshold voltage accuracy V

SCC detection threshold voltage accuracy

SCD detection threshold voltage accuracy

DS(on)

= 2V; TA= 25 ° C

= 25mV (min) 15 25 35

= 100mV; RSNS = 0, 1 90 100 110 mV

= 205mV (max) 185 205 225

= 50mV (min) 30 50 70

SCC

= 200mV; RSNS = 0, 1 180 200 220 mV

SCC

= 475mV (max) 428 475 523

SCC

= – 50mV (min) – 30 – 50 – 70

SCD

= – 200mV; RSNS = 0, 1 – 180 – 200 – 220 mV

SCD

= – 475mV (max) – 428 – 475 – 523

SCD

Delay time accuracy ± 15.25 µ s Protection circuit propagation delay 50 µ s

= V

– V

; V

DSG pin output on voltage 10M Ω ;DSG and CHG on; TA= 8 12 16 V

DSGON

DSG

PACK

– 40 ° C to 100 ° C V

= V

– V

; V

CHG pin output on voltage 10M Ω ;DSG and CHG on; TA= 8 12 16 V

CHGON

CHG

BAT

– 40 ° C to 100 ° C DSG pin output off voltage V CHG pin output off voltage V

CL=4700pF; V Rise time µ s

CL=4700pF; V

CL=4700pF; V Fall time µ s

≤ V

CL=4700pF; V

≤ V

= V

DSGOFF CHGOFF

+ 1V

PACK

+ 1V

BAT

– V

DSG

PACK

= V

– V

CHG

BAT

PACK

BAT PACK

BAT

≤ DSG ≤ V

≤ CHG ≤ V

+ V

DSGON

+ V

CHGON

PACK

+ 4V 400 1000

BAT

≤ DSG

≤ CHG

ZVCHG clamp voltage BAT = 4.5V 3.3 3.5 3.7 V

Internal pullup resistance k Ω

ALERT 60 100 200

RESET 1 3 6

ALERT 0.2 Logic low output voltage level 0.4 V

RESET; V

RESET

GPOD; I

= 7V; V

BAT

= 200 µ A

= 50 µ A 0.6

GPOD

= 1.5V;

REG25

High-level input voltage 2.0 V Low-level input voltage 0.8 V

= 2.41 V to 2.59 V, V

REG25

400 1000

40 200

bq20z75

SLUS723 – JULY 2007

0.2 V

BAT

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bq20z75

SLUS723 – JULY 2007

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted), TA= – 40 ° C to 85 ° C, V 14V, C

(SAFE)

lkg(SAFE)

lkg

ADC

COULOMB COUNTER

INTERNAL TEMPERATURE SENSOR

(TEMP)

VOLTAGE REFERENCE

HIGH FREQUENCY OSCILLATOR

(OSC)

= 1µF, C

REG25

= 2.2µF; typical values at TA= 25 ° C (unless otherwise noted)

REG33

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Output voltage high

(1)

SAFE, IL= – 0.5 mA V

Low-level output voltage PRES, PFIN, ALERT, IL= 7 mA; 0.4 V Input capacitance 5 pF SAFE source currents SAFE active, SAFE = V

– 0.6 V – 3 mA

REG25

SAFE leakage current SAFE inactive – 0.2 0.2 µA Input leakage current 1 µA

(2)

Input voltage range TS1,TS2, using external V

ref

Conversion time 31.5 ms Resolution (no missing codes) 16 bits Effective resolution 14 15 bits Integral nonlinearity ± 0.03 %FSR Offset error Offset error drift Full-scale error

(4)

(5)

TA= 25 ° C to 85 ° C 2.5 18 µ V/ ° C

Full-scale error drift 50 PPM/ ° C Effective input resistance

(6)

Input voltage range – 0.20 0.20 V Conversion time Single conversion 250 ms Effective resolution Single conversion 15 bits

Integral nonlinearity %FSR

Offset error

(7)

– 0.1 V to 0.20 V ± 0.007 ± 0.034

– 0.20 V to – 0.1 V ± 0.007

TA= 25 ° C to 85 ° C 10 µV Offset error drift 0.4 0.7 µV/ ° C Full-scale error

(8) (9)

Full-scale error drift 150 PPM/ ° C Effective input resistance

Temperature sensor voltage

(10)

(11)

TA= 25 ° C to 85 ° C 2.5 M Ω

Output voltage 1.215 1.225 1.230 V Output voltage drift 65 PPM/ ° C

Operating frequency 4.194 MHz

= 2.41 V to 2.59 V, V

REG25

– 0.

REG25

– 0.2 V

REG25

140 250 µV

± 0.1% ± 0.7%

8 M Ω

± 0.35%

– 2.0 mV/ ° C

BAT

0.2

(3)

(1) RC[0:7] bus (2) Unless otherwise specifified, the specification limits are valid at all measurement speed modes (3) Full-scale reference (4) Post-calibration performance and no I/O changes during conversion with SRN as the ground reference (5) Uncalibrated performance. This gain error can be eliminated with external calibration. (6) The A/D input is a switched-capacitor input. Since the input is switched, the effective input resistance is a measure of the average

resistance. (7) Post-calibration performance (8) Reference voltage for the coulomb counter is typically V (9) Uncalibrated performance. This gain error can be eliminated with external calibration.

/3.969 at V

ref

= 2.5 V, TA= 25 ° C.

REG25

(10) The CC input is a switched capacitor input. Since the input is switched, the effective input resistance is a measure of the average

resistance. (11) – 53.7 LSB/ ° C

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted), TA= – 40 ° C to 85 ° C, V 14V, C

(EIO)

(SXO)

LOW FREQUENCY OSCILLATOR

(LOSC)

(LEIO)

(LSXO)

(12) The frequency error is measured from 4.194 MHz. (13) The frequency drift is included and measured from the trimmed frequency at V (14) The startup time is defined as the time it takes for the oscillator output frequency to be ± 3% (15) The frequency error is measured from 32.768 kHz.

= 1µF, C

REG25

= 2.2µF; typical values at TA= 25 ° C (unless otherwise noted)

REG33

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Frequency error

Start-up time

(12) (13)

TA= 20 ° C to 70 ° C – 2% 0.25% 2%

(14)

Operating frequency 32.768 kHz

Frequency error

Start-up time

(13) (15)

TA= 20 ° C to 70 ° C – 1.5% 0.25% 1.5%

(14)

= 2.5V, TA= 25 ° C

REG25

– 2.5% 0.25% 2.5%

= 2.41 V to 2.59 V, V

REG25

– 3% 0.25% 3%

Data Flash Characteristics Over Recommended Operating Temperature and Supply Voltage

Typical Values at TA= 25 ° C and V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Data retention 10 Years Flash programming write-cycles 20k Cycles

(ROWPROG)

(MASSERASE)

(PAGEERASE)

(DDPROG)

(DDERASE)

RAM BACKUP

(RB)

(1) Assured by design. Not production tested.

Row programming time See Mass-erase time 200 ms Page-erase time 20 ms Flash-write supply current 5 10 mA Flash-erase supply current 5 10 mA

RB data-retention input current nA

RB data-retention input voltage

= 2.5 V (unless otherwise noted)

REG25

(1)

(RBI)

TA= 85 ° C V

(RBI)

TA= 25 ° C

(1)

> V

, V

(RBI)MIN

, V

(RBI)MIN

< V

REG25

, 1000 2500

IT –

< V

, 90 220

IT –

1.7 V

bq20z75

SLUS723 – JULY 2007

2.5 5 ms

500 µs

2 ms

BAT

SMBus Timing Characteristics

TA= – 40 ° C to 85 ° C Typical Values at TA= 25 ° C and V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SMB

MAS

(BUF)

(HD:STA)

(SU:STA)

(SU:STO)

(HD:DAT)

(SU:DAT)

SMBus operating frequency Slave mode, SMBC 50% duty cycle 10 100 kHz SMBus master clock frequency Master mode, No clock low slave 51.2 kHz

Bus free time between start and stop 4.7 µs (see Figure 1 )

Hold time after (repeated) start (see Figure 1 ) 4.0 µs Repeated start setup time (see Figure 1 ) 4.7 µs Stop setup time (see Figure 1 ) 4.0 µs

Data hold time (see Figure 1 )

Data setup time (see Figure 1 ) 250 ns

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= 2.5 V (Unless Otherwise Noted)

(REG25)

extend

Receive mode 0 ns Transmit mode 300

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(LOW)

(HD:STA)

(SU:DAT)

(HIGH)

(HD:DAT)

(HD:STA)

(BUF)

SCLK

SDATA

(SU:STO)

SCLK

SDATA

Start Stop

(LOW:SEXT)

(LOW:MEXT)

SCLK

ACK

(1)

SCLK

ACK

(1)

(SU:STA)

bq20z75

SLUS723 – JULY 2007

SMBus Timing Characteristics (continued)

TA= – 40 ° C to 85 ° C Typical Values at TA= 25 ° C and V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(TIMEOUT)

(LOW)

(HIGH)

(LOW:SEXT)

(LOW:MEXT)

(1) The bq20z75 times out when any clock low exceeds t (2) t

progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0). (3) t (4) t (5) Rise time tr= VILMAX – 0.15) to (VIHMIN + 0.15) (6) Fall time tf= 0.9V

Error signal/detect (see Figure 1 ) See Clock low period (see Figure 1 ) 4.7 µs Clock high period (see Figure 1 ) See Cumulative clock low slave extend time See Cumulative clock low master extend time (see See

Figure 1 )

Clock/data fall time See Clock/data rise time See

, Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving bq20z75 that is in

(HIGH)

(LOW:SEXT) (LOW:MEXT)

is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.

is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.

to (VILMAX – 0.15)

(TIMEOUT)

= 2.5 V (Unless Otherwise Noted)

(REG25)

(1)

(2) (3) (4)

(5) (6)

25 35 µs

4.0 50 µs 25 µs 10 µs

300 ns

1000 ns

A. SCLKACK is the acknowledge-related clock pulse generated by the master.

Figure 1. SMBus Timing Diagram

Product Folder Link(s): bq20z75

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bq20z75

SLUS723 – JULY 2007

FEATURE SET

Primary (1st Level) Safety Features

The bq20z75 supports a wide range of battery and system protection features that can easily be configured. The primary safety features include:

• Cell over/under voltage protection

• Charge and Discharge over current

• Short Circut

• Charge and Discharge Over temperature

• AFE Watchdog

Secondary (2nd Level) Safety Features

The secondary safety features of the bq20z75 can be used to indicate more serious faults via the SAFE (pin 7). This pin can be used to blow an in-line fuse to permanently disable the battery pack from charging or discharging. The secondary safety protection features include:

• Safety overvoltage

• Safety overcurrent in Charge and Discharge

• Safety overtemperature in Charge and Discharge

• Charge FET and 0 Volt Charge FET fault

• Discharge FET fault

• AFE communication fault

Charge Control Features

The bq20z75 charge control features include:

• Reports the appropriate charging current needed for constant current charging and the appropriate charging voltage needed for constant voltage charging to a smart charger using SMBus broadcasts.

• Determines the chemical state of charge of each battery cell using Impedance Track™ and can reduce the charge difference of the battery cells in fully charged state of the battery pack gradually using cell balancing algorithm during charging. This prevents fully charged cells from overcharging and causing excessive degradation and also increases the usable pack energy by preventing premature charge termination

• Supports pre-charging/zero-volt charging

• Support fast charging

• Supports charge inhibit and charge suspend if battery pack temperature is out of temperature range

• Reports charging fault and also indicate charge status via charge and discharge alarms.

Gas Gauging

The bq20z75 uses the Impedance Track™ Technology to measure and calculate the available charge in battery cells. The achievable accuracy is better than 1% error over the lifetime of the battery and there is no full charge discharge learning cycle required.

See Theory and Implementation of Impedance Track Battery Fuel-Gauging Algorithm application note (SLUA364) for further details.

Authentication

The bq20z75 supports authentication by the host using SHA-1.

Power Modes

The bq20z75 supports 3 different power modes to reduce power consumption:

• In Normal Mode, the bq20z75 performs measurements, calculations, protection decisions and data updates in 1 second intervals. Between these intervals, the bq20z75 is in a reduced power stage.

Product Folder Link(s): bq20z75

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bq20z75

SLUS723 – JULY 2007

• In Sleep Mode, the bq20z75 performs measurements, calculations, protection decisions and data update in adjustable time intervals. Between these intervals, the bq20z75 is in a reduced power stage. The bq20z75 has a wake function that enables exit from Sleep mode, when current flow or failure is detected.

• In Shutdown Mode the bq20z75 is completely disabled.

CONFIGURATION

Oscillator Function

The bq20z75 fully integrates the system oscillators. Therefore the bq20z75 requires no external components for this feature.

System Present Operation

The bq20z75 checks the PRES pin periodically (1 s). Connect the PRES pin to TOUT with a 100k Ω resistor. If PRES input is pulled to ground by external system host, the bq20z75 detects this as system present.

BATTERY PARAMETER MEASUREMENTS

The bq20z75 uses an integrating delta-sigma analog-to-digital converter (ADC) for current measurement, and a second delta-sigma ADC for individual cell and battery voltage, and temperature measurement.

Charge and Discharge Counting

The integrating delta-sigma ADC measures the charge/discharge flow of the battery by measuring the voltage drop across a small-value sense resistor between the SRP and SRN pins. The integrating ADC measures bipolar signals from – 0.25 V to 0.25 V. The bq20z75 detects charge activity when V discharge activity when V

= V

– V

(SRP)

is negative. The bq20z75 continuously integrates the signal over

(SRN)

time, using an internal counter. The fundamental rate of the counter is 0.65 nVh.

= V

– V

(SRP)

(SRN)

is positive and

Voltage

The bq20z75 updates the individual series cell voltages at one second intervals.The internal ADC of the bq20z75 measures the voltage, scales and calibrates it appropriately. This data is also used to calculate the impedance of the cell for the Impedance Track™ gas-gauging.

Current

The bq20z75 uses the GSRP and GSRN inputs to measure and calculate the battery charge and discharge current using a 5 m Ω to 20 m Ω typ. sense resistor.

Auto Calibration

The bq20z75 provides an auto-calibration feature to cancel the voltage offset error across GSRN and GSRP for maximum charge measurement accuracy. The bq20z75 performs auto-calibration when the SMBus lines stay low continuously for a minimum of 5 s.

Temperature

The bq20z75 has an internal temperature sensor and 2 external temperature sensor inputs TS1 and TS2 used in conjunction with two identical NTC thermistors (default are Semitec 103AT) to sense the battery enviromental temperature. The bq20z75 can be configured to use internal or external temperature sensors.

COMMUNICATIONS

The bq20z75 uses SMBus v1.1 with Master Mode and package error checking (PEC) options per the SBS specification.

SMBus On and Off State

The bq20z75 detects an SMBus off state when SMBC and SMBD are logic-low for ≥ 2 seconds. Clearing this state requires either SMBC or SMBD to transition high. Within 1 ms, the communication bus is available.

Product Folder Link(s): bq20z75

www.ti.com

SLUS723 – JULY 2007

SBS and Dataflash Values

Table 1. SBS COMMANDS

SBS Mode Name Format Size in Min Max Default Unit Cmd Bytes Value Value Value

0x00 R/W ManufacturerAccess hex 2 0x0000 0xffff — 0x01 R/W RemainingCapacityAlarm unsigned int 2 0 65535 — mAh or

0x02 R/W RemainingTimeAlarm unsigned int 2 0 65535 — min 0x03 R/W BatteryMode hex 2 0x0000 0xffff — 0x04 R/W AtRate signed int 2 – 32768 32767 — mA or 10mW 0x05 R AtRateTimeToFull unsigned int 2 0 65535 — min 0x06 R AtRateTimeToEmpty unsigned int 2 0 65535 — min 0x07 R AtRateOK unsigned int 2 0 65535 — 0x08 R Temperature unsigned int 2 0 65535 — 0.1 ° K 0x09 R Voltage unsigned int 2 0 20000 — mV 0x0a R Current signed int 2 – 32768 32767 — mA 0x0b R AverageCurrent signed int 2 – 32768 32767 — mA 0x0c R MaxError unsigned int 1 0 100 — % 0x0d R RelativeStateOfCharge unsigned int 1 0 100 — % 0x0e R AbsoluteStateOfCharge unsigned int 1 0 100 — % 0x0f R/W RemainingCapacity unsigned int 2 0 65535 — mAh or

0x10 R FullChargeCapacity unsigned int 2 0 65535 — mAh or

0x11 R RunTimeToEmpty unsigned int 2 0 65535 — min 0x12 R AverageTimeToEmpty unsigned int 2 0 65535 — min 0x13 R AverageTimeToFull unsigned int 2 0 65535 — min 0x14 R ChargingCurrent unsigned int 2 0 65535 — mA 0x15 R ChargingVoltage unsigned int 2 0 65535 — mV 0x16 R BatteryStatus unsigned int 2 0x0000 0xffff — 0x17 R/W CycleCount unsigned int 2 0 65535 — 0x18 R/W DesignCapacity unsigned int 2 0 65535 — mAh or

0x19 R/W DesignVoltage unsigned int 2 7000 16000 14400 mV 0x1a R/W SpecificationInfo unsigned int 2 0x0000 0xffff 0x0031 0x1b R/W ManufactureDate unsigned int 2 0 65535 0 0x1c R/W SerialNumber hex 2 0x0000 0xffff 0x20 R/W ManufacturerName String 11+1 — — Texas ASCII

Instruments 0x21 R/W DeviceName String 7+1 — — bq20z75 ASCII 0x22 R/W DeviceChemistry String 4+1 — — LION ASCII 0x23 R ManufacturerData String 14+1 — — — ASCII 0x2f R/W Authenticate String 20+1 — — — ASCII 0x3c R CellVoltage4 unsigned int 2 0 65535 — mV 0x3d R CellVoltage3 unsigned int 2 0 65535 — mV 0x3e R CellVoltage2 unsigned int 2 0 65535 — mV 0x3f R CellVoltage1 unsigned int 2 0 65535 — mV

bq20z75

10mWh

Product Folder Link(s): bq20z75

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bq20z75

SLUS723 – JULY 2007

Table 2. EXTENDED SBS COMMANDS

SBS Mode Name Format Size in Min Value Max Value Default Unit Cmd Bytes Value

0x45 R AFEData String 11+1 — — — ASCII 0x46 R/W FETControl hex 1 0x00 0xff — 0x4f R StateOfHealth unsigned int 1 0 100 — % 0x51 R SafetyStatus hex 2 0x0000 0xffff — 0x53 R PFStatus hex 2 0x0000 0xffff — 0x54 R OperationStatus hex 2 0x0000 0xffff — 0x55 R ChargingStatus hex 2 0x0000 0xffff — 0x57 R ResetData hex 2 0x0000 0xffff — 0x5a R PackVoltage unsigned int 2 0 65535 — mV 0x5d R AverageVoltage unsigned int 2 0 65535 — mV 0x60 R/W UnSealKey hex 4 0x00000000 0xffffffff — 0x61 R/W FullAccessKey hex 4 0x00000000 0xffffffff — 0x62 R/W PFKey hex 4 0x00000000 0xffffffff — 0x63 R/W AuthenKey3 hex 4 0x00000000 0xffffffff — 0x64 R/W AuthenKey2 hex 4 0x00000000 0xffffffff — 0x65 R/W AuthenKey1 hex 4 0x00000000 0xffffffff — 0x66 R/W AuthenKey0 hex 4 0x00000000 0xffffffff — 0x70 R/W ManufacturerInfo String 8+1 — — — 0x71 R/W SenseResistor unsigned int 2 0 65535 — µ Ω 0x77 R/W DataFlashSubClassID hex 2 0x0000 0xffff — 0x78 R/W DataFlashSubClassPage1 hex 32 — — — 0x79 R/W DataFlashSubClassPage2 hex 32 — — — 0x7a R/W DataFlashSubClassPage3 hex 32 — — — 0x7b R/W DataFlashSubClassPage4 hex 32 — — — 0x7c R/W DataFlashSubClassPage5 hex 32 — — — 0x7d R/W DataFlashSubClassPage6 hex 32 — — — 0x7e R/W DataFlashSubClassPage7 hex 32 — — — 0x7f R/W DataFlashSubClassPage8 hex 32 — — —

Product Folder Link(s): bq20z75

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bq20z75

SLUS723 – JULY 2007

Application Schematics

Product Folder Link(s): bq20z75

www.ti.com

TPC8017-H

321

bq20z75

SLUS723 – JULY 2007

Product Folder Link(s): bq20z75

PACKAGE OPTION ADDENDUM

www.ti.com

28-Sep-2007

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

BQ20Z75DBT ACTIVE SM8 DBT 38 50 Green (RoHS &

no Sb/Br)

BQ20Z75DBTR ACTIVE SM8 DBT 38 2000 Green (RoHS &

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-2-260C-1 YEAR

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

TAPE AND REEL BOX INFORMATION

5-Oct-2007

Device Package Pins Site Reel

Diameter

(mm)

BQ20Z75DBTR DBT 38 SITE 60 330 16 6.9 10.2 1.8 12 16 Q1

Reel

Width

(mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Oct-2007

Device Package Pins Site Length (mm) Width (mm) Height (mm)

BQ20Z75DBTR DBT 38 SITE 60 346.0 346.0 33.0

Pack Materials-Page 2

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TEXAS INSTRUMENTS bq20z75 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual