Texas Instruments BQ20Z45DBT Schematics

bq20z45

www.ti.com

.................................................................................................................................................................................................. SLUS800 – MARCH 2009

SBS 1.1-Compliant Gas Gauge and Protection Enabled With Impedance Track™

1

FEATURES

2

• Next Generation Patented Impedance Track™

Technology Accurately Measures Available Charge in Li-Ion and Li-Polymer Batteries

– Better Than 1% Error Over the Lifetime of

the Battery

• Supports the Smart Battery Specification

SBS V1.1

• Flexible Configuration for 2 to 4 Series Li-Ion

and Li-Polymer Cells

• Powerful 8-Bit RISC CPU With Ultralow Power

Modes

• Full Array of Programmable Protection

Features – Voltage, Current, and Temperature

• Satisfies JEITA Guidelines

• Added Flexibility to Handle More Complex

Charging Profiles

• Lifetime Data Logging

• Supports SHA-1 Authentication

• Complete Battery Protection and Gas Gauge

Solution in One Package

• Available in a 38-Pin TSSOP (DBT) package

DESCRIPTION

The bq20z45 SBS-compliant gas gauge and protection IC is a single IC solution designed for battery-pack or in-system installation. The bq20z45 measures and maintains an accurate record of available charge in Li-ion or Li-polymer batteries using its integrated high-performance analog peripherals, monitors capacity change, battery impedance, open-circuit voltage, and other critical parameters of the battery pack as well and reports the information to the system host controller over a serial-communication bus. Together with the integrated analog front-end (AFE) short-circuit and overload protection, the bq20z45 maximizes functionality and safety while minimizing external component count, cost, and size in smart battery circuits.

The implemented Impedance Track™ gas gauging technology continuously analyzes the battery impedance, resulting in superior gas-gauging accuracy. This enables remaining capacity to be calculated with discharge rate, temperature, and cell aging all accounted for during each stage of every cycle with high accuracy.

APPLICATIONS

• Notebook PCs

• Medical and Test Equipment

• Portable Instrumentation

AVAILABLE OPTIONS

T

A

– 40 ° C to 85 ° C bq20z45DBT

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com . (2) A single tube quantity is 50 units. (3) A single reel quantity is 2000 units

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 Impedance Track is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

38-PIN TSSOP (DBT) Tube 38-PIN TSSOP (DBT) Tape and Reel

(2)

PACKAGE

(1)

bq20z45DBTR

(3)

Coloumb

Counter

HWOver

Current&

ShortCircuit

Protection

CellVoltage

Multiplexer

N-ChannelFET

Drive

PreChargeFET

& GPODDrive

PowerMode

Control

SMBD

GSRN

GSRP

ASRN

ASRP

GPOD

ZVCHG

CHG

DSG

VC5

VC4

VC3

VC2

VC1

SMBC

CellBalancing

Temperature Measurement

DataFlash

Memory

SMB1.1

Impedance

Track™

GasGauging

SHA-1

Authentication

Over &Under

Voltage

Protection

Voltage

Measurement

OverCurrent

Protection

Oscillator

Charging Algorithm

FuseBlow

Detectionand

Logic

Over

Temperature

Protection

SAFE

PFIN

TS2

TS1

TOUT

PMS

Watchdog

Regulators

RESET

ALERT

REG33

REG25

VCELL+

BA

T

P

ACK

VCC

VSS

MSRT

RBI

SystemControl AFEHWControl

Pack-

RSNS 5m -20m typ.W W

Pack+

SMBC

SMBD

bq20z45

GND

VC4

VC3

VC2

VC1

VDD

OUT

CD

bq294xx

1

DSG

2

PACK

3

11

VCC

ALERT

4

12

ZVCHG

PRES

5

13

6

14

PMS

TS2

7

15

VSS

PFIN

8

16

REG33

SAFE

9

17

TOUT

SMBD

10

18 19

VCELL+

SMBC

NC

CHG

38

BAT

37

VC1

VSS

36

28

VC2

RBI

35

27

VC3

REG25

34

26

VC4

VSS

33

25

VC5

MRST

32

24

ASRP

GSRN

31

23

ASRN

GSRP

30

22

RESET

VSS VSS

29

21

20

GPOD

TS1

bq20z45

SLUS800 – MARCH 2009 ..................................................................................................................................................................................................

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

SYSTEM PARTITIONING DIAGRAM

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bq20z45

DBT PACKAGE

(TOP VIEW)

Product Folder Link(s): bq20z45

bq20z45

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.................................................................................................................................................................................................. SLUS800 – MARCH 2009

PIN FUNCTIONS

NO. NAME

1 DSG O High side N-chan discharge FET gate drive 2 PACK IA, P

3 VCC P 4 ZVCHG O P-chan pre-charge FET gate drive 5 GPOD OD

6 PMS I connected at CHG pin. Connect to VSS to disable 0V pre-charge using charge FET connected at

7 VSS P Negative device power supply input. Connect all VSS pins together for operation of device 8 REG33 P 3.3V regulator output. Connect at least a 2.2 µ F capacitor to REG33 and VSS 9 TOUT P Thermistor bias supply output

10 VCELL+ - Internal cell voltage multiplexer and amplifier output. Connect a 0.1 µ F capacitor to VCELL+ and VSS

11 ALERT I/OD

12 PRES I/OD System / Host present input. Pull up to TOUT

13 TS1 IA Temperature sensor 1 input

14 TS2 IA Temperature sensor 2 input

15 PFIN I/OD Fuse blow detection input

16 SAFE I/OD blow fuse signal output

17 SMBD I/OD SMBus data line

18 SMBC I/OD SMBus clock line

19 NC - Not connected

20, 21, 25,

28

22 GSRP IA Coulomb counter differential input. Connect to one side of the sense resistor

23 GSRN IA Coulomb counter differential input. Connect to one side of the sense resistor

24 MRST I Reset input for internal CPU core. connect to RESET for correct operation of device

26 REG25 P 2.5V regulator output. Connect at least a 1 µ F capacitor to REG25 and VSS

27 RBI P

29 RESET O Reset output. Connect to MSRT.

30 ASRN IA Short circuit and overload detection differential input. Connect to sense resistor

31 ASRP IA Short circuit and overload detection differential input. Connect to sense resistor

32 VC5 IA, P

33 VC4 IA, P

34 VC3 IA, P

35 VC2 IA, P and the negative voltage of the highest cell in 4 cell applications. Connect to VC3 in 2 cell stack

36 VC1 IA, P

37 BAT I, P Battery stack voltage sense input

38 CHG O High side N-chan charge FET gate drive (1) I = Input, IA = Analog input, I/O = Input/output, I/OD = Input/Open-drain output, O = Output, OA = Analog output, P = Power

VSS P Negative device power supply input. Connect all VSS pins together for operation of device

(1)

I/O

Battery pack input voltage sense input. It also serves as device wake up when device is in shutdown mode.

Positive device supply input. Connect to the center connection of the CHG FET and DSG FET to ensure device supply either from battery stack or battery pack input

High voltage general purpose open drain output. Can be configured to be used in pre-charge condition

Pre-charge mode setting input. Connect to PACK to enable 0v pre-charge using charge FET CHG pin.

Alert output. In case of short circuit condition, overload condition and watchdog time out this pin will be triggered.

RAM backup input. Connect a capacitor to this pin and VSS to protect loss of RAM data in case of short circuit condition

Cell voltage sense input and cell balancing input for the negative voltage of the bottom cell in cell stack.

Cell voltage sense input and cell balancing input for the positive voltage of the bottom cell and the negative voltage of the second lowest cell in cell stack.

Cell voltage sense input and cell balancing input for the positive voltage of the second lowest cell in cell stack and the negative voltage of the second highest cell in 4 cell applications.

Cell voltage sense input and cell balancing input for the positive voltage of the second highest cell applications

Cell voltage sense input and cell balancing input for the positive voltage of the highest cell in cell stack in 4 cell applications. Connect to VC2 in 3 or 2 cell stack applications

DESCRIPTION

Product Folder Link(s): bq20z45

bq20z45

SLUS800 – MARCH 2009 ..................................................................................................................................................................................................

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature (unless otherwise noted)

PIN UNIT

BAT, VCC – 0.3 V to 34 V PACK, PMS – 0.3 V to 34 V

V

Supply voltage range VC(n)-VC(n+1); n = 1, 2, 3, 4 – 0.3 V to 8.5 V

SS

VC1, VC2, VC3, VC4 – 0.3 V to 34 V VC5 – 0.3 V to 1 V PFIN, SMBD, SMBC – 0.3 V to 6 V

V

Input voltage range

IN

V

Output voltage range TOUT, ALERT, REG33 – 0.3 V to 6 V

OUT

I

Maximum combined sink current for input pins PRES, PFIN, SMBD, SMBC 50 mA

SS

T

Operating free-air temperature range – 40 ° C to 85 ° C

A

T

Functional temperature – 40 ° C to 100 ° C

F

T

Storage temperature range – 65 ° C to 150 ° C

stg

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

TS1, TS2, SAFE, VCELL+, PRES; ALERT – 0.3 V to V MRST, GSRN, GSRP, RBI – 0.3 V to V ASRN, ASRP – 1 V to 1 V DSG, CHG, GPOD – 0.3 V to 34 V ZVCHG – 0.3 V to V

RESET – 0.3 V to 7 V REG25 – 0.3 V to 2.75 V

(1)

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+ 0.3 V

(REG25)

+ 0.3 V

(REG25)

(BAT)

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

PIN MIN NOM MAX UNIT

V

SS

V

(STARTUP)

V

IN

V

(GPOD)

A

(GPOD)

C

(REG25)

C

(REG33)

C

(VCELL+)

C

(PACK)

(1) Use an external resistor to limit the current to GPOD to 1mA in high voltage application. (2) Use an external resistor to limit the inrush current PACK pin required.

Supply voltage VCC, BAT 4.5 25 V Minimum startup voltage VCC, BAT, PACK 5.5 V

VC(n)-VC(n+1); n = 1,2,3,4 0 5 V VC1, VC2, VC3, VC4 0 V

Input Voltage Range VC5 0 0.5 V

ASRN, ASRP – 0.5 0.5 V

PACK, PMS 0 25 V Output Voltage Range GPOD 0 25 V Drain Current

(1)

GPOD 1 mA

2.5V LDO Capacitor REG25 1 µ F

3.3V LDO Capacitor REG33 2.2 µ F Cell Voltage Output Capacitor VCELL+ 0.1 µ F PACK input block resistor

(2)

PACK 1 k Ω

SUP

V

Product Folder Link(s): bq20z45

bq20z45

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.................................................................................................................................................................................................. SLUS800 – MARCH 2009

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted), TA= – 40 ° C to 85 ° C, V V

= 14 V, C

(BAT)

SUPPLY CURRENT

I

(NORMAL)

I

(SLEEP)

I

(SHUTDOWN)

Firmware running 550 µ A Sleep Mode CHG FET on; DSG FET on 124 µ A

Shutdown Mode 0.1 1 µ A

SHUTDOWN WAKE; TA= 25 ° C (unless otherwise noted)

I

(PACK)

Shutdown exit at V

SRx WAKE FROM SLEEP; TA= 25 ° C (unless otherwise noted)

Positive or negative wake threshold

V

(WAKE)

V

(WAKE_ACR)

V

(WAKE_TCO)

t

(WAKE)

with 1.00 mV, 2.25 mV, 4.5 mV and 9 1.25 10 mV mV programmable options

Accuracy of V

Temperature drift of V Time from application of current and

wake of bq8040

POWER-ON RESET

V

IT –

V

hys

t

RST

Negative-going voltage input Voltage at REG25 pin 1.70 1.80 1.90 V Hysteresis V

RESET active low time 100 250 560 µ s

WATCHDOG TIMER

t

WDTINT

t

WDWT

2.5V LDO; I

V

(REG25)

Δ V

(REG25TEMP)

Δ V

(REG25LINE)

Δ V

(REG25LOAD)

I

(REG25MAX)

3.3V LDO; I

V

(REG33)

Δ V

(REG33TEMP)

Δ V

(REG33LINE)

Δ V

(REG33LOAD)

Watchdog start up detect time 250 500 1000 ms Watchdog detect time 50 100 150 µ s

(REG33OUT)

Regulator output voltage I

Regulator output change with I temperature TA= – 40 ° C to 100 ° C

Line regulation 3 10 mV

Load Regulation mV

Current Limit 5 40 75 mA

(REG25OUT)

Regulator output voltage I

Regulator output change with I temperature TA= – 40 ° C to 100 ° C

Line regulation 3 10 mV

Load Regulation mV

= 1 µ F, C

(REG25)

= 2.2 µ F; typical values at TA= 25 ° C (unless otherwise noted)

(REG33)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CHG FET off; DSG FET on 90 µ A CHG FET off; DSG FET off 52 µ A

threshold 1 µ A

STARTUP

V

= 1 mV;

(WAKE)

I

= 0, RSNS1 = 0, RSNS0 = 1;

(WAKE)

V

= 2.25 mV;

(WAKE)

I

) = 1, RSNS1 = 0, RSNS0 = 1; -0.8 0.8

(WAKE

I

= 0, RSNS1 = 1, RSNS0 = 0;

(WAKE)

accuracy 0.5 %/ ° C

(WAKE)

V

= 4.5 mV;

(WAKE)

I

= 1, RSNS1 = 1, RSNS0 = 1; -1.0 1.0

(WAKE)

I

= 0, RSNS1 = 1, RSNS0 = 0;

(WAKE)

V

= 9 mV;

(WAKE)

I

= 1, RSNS1 = 1, RSNS0 = 1;

(WAKE)

– V

IT+

IT-

active low time after power up or watchdog reset

= 0 mA; TA= 25 ° C (unless otherwise noted)

4.5 < VCC or BAT < 25 V; ) ≤ 16 mA; 2.41 2.5 2.59 V

(REG25OUT

TA= – 40 ° C to 100 ° C

(REG25OUT)

= 2 mA;

5.4 < VCC or BAT < 25 V;

I

(REG25OUT)

0.2 mA ≤ I

= 2 mA

(REG25OUT) (REG25OUT)

≤ 2 mA 7 25 ≤ 16 mA 25 50

drawing current until REG25 = 2 V to 0 V

= 0 mA; TA= 25 ° C (unless otherwise noted)

4.5 < VCC or BAT < 25 V;

(REG33OUT)

TA= – 40 ° C to 100 ° C

(REG33OUT)

≤ 25 mA; 3 3.3 3.6 V

= 2 mA;

5.4 < VCC or BAT < 25 V;

I

(REG33OUT)

0.2 mA ≤ I

0.2mA ≤ I

= 2 mA

(REG33OUT)

≤ 2 mA 7 17

≤ 25 mA 40 100

= 2.41 V to 2.59 V,

(REG25)

-0.7 0.7

-1.4 1.4

1 10 ms

50 150 250 mV

± 0.2 %

mV

Product Folder Link(s): bq20z45

bq20z45

SLUS800 – MARCH 2009 ..................................................................................................................................................................................................

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ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range (unless otherwise noted), TA= – 40 ° C to 85 ° C, V V

= 14 V, C

(BAT)

I

(REG33MAX)

Current Limit mA

THERMISTOR DRIVE

V

(TOUT)

R

DS(on)

Output voltage I TOUT pass element resistance 50 100 Ω

VCELL+ HIGH VOLTAGE TRANSLATION

V

(VCELL+OUT)

V

(VCELL+REF)

V

(VCELL+PACK)

V

(VCELL+BAT)

Translation output 0.965 0.975 0.985 V

CMMR Common mode rejection ratio VCELL+ 40 dB

K Cell scale factor

I

(VCELL+OUT)

V

(VCELL+O)

I

VCnL

Drive Current to VCELL+ capacitor 12 18 µ A

CELL offset error -18 -1 18 mV VC(n) pin leakage current VC1, VC2, VC3, VC4, VC5 = 3 V -1 0.01 1 µ A

CELL BALANCING

R

(BAL)

internal cell balancing FET resistance 200 400 600 Ω

HARDWARE SHORT CIRCUIT AND OVERLOAD PROTECTION; TA= 25 ° C (unless otherwise noted)

V

(OL)

V

(SCC)

V

(SCD)

t

da

t

pd

OL detection threshold voltage accuracy

SCC detection threshold voltage accuracy

SCD detection threshold voltage accuracy

Delay time accuracy ± 15.25 µ s Protection circuit propagation delay 50 µ s

FET DRIVE CIRCUIT; TA= 25 ° C (unless otherwise noted)

V

(DSGON)

V

(CHGON)

V

(DSGOFF)

V

(CHGOFF)

DSG pin output on voltage V

CHG pin output on voltage V

DSG pin output off voltage V CHG pin output off voltage V

= 1 µ F, C

(REG25)

= 2.2 µ F; typical values at TA= 25 ° C (unless otherwise noted)

(REG33)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

drawing current until REG33 = 3 V 25 100 145 short REG33 to VSS, REG33 = 0 V 12 65

= 0 mA; TA= 25 ° C V

(TOUT)

I

= 1 mA; R

(TOUT)

V

)/ 1 mA; TA= – 40 ° C to 100 ° C

(TOUT)

VC(n) - VC(n+1) = 0 V; TA= – 40 ° C to 100 ° C

VC(n) - VC(n+1) = 4.5 V; TA= – 40 ° C to 100 ° C

= (V

DS(on)

-

(REG25)

0.950 0.975 1

0.275 0.3 0.375

internal AFE reference voltage ; TA= – 40 ° C to 100 ° C

Voltage at PACK pin; 0.98 × 1.02 × TA= – 40 ° C to 100 ° C V

/18 V

(PACK)

Voltage at BAT pin; 0.98 × TA= – 40 ° C to 100 ° C V

/18

(BAT)

K= {VCELL+ output (VC5=0V; VC4=4.5V) - VCELL+ output (VC5=0V; 0.147 0.150 0.153 VC4=0V)}/4.5

K= {VCELL+ output (VC2=13.5V; VC1=18V) - VCELL+ output 0.147 0.150 0.153 (VC5=13.5V; VC1=13.5V)}/4.5

VC(n) - VC(n+1) = 0V; VCELL+ = 0 V; TA= – 40 ° C to 100 ° C

CELL output (VC2 = VC1 = 18 V) CELL output (VC2 = VC1 = 0 V)

R

for internal FET switch at

DS(on)

VDS= 2 V; TA= 25 ° C

VOL= 25 mV (min) 15 25 35 VOL= 100 mV; RSNS = 0, 1 90 100 110 mV VOL= 205 mV (max) 185 205 225 V

= 50 mV (min) 30 50 70

(SCC)

V

= 200 mV; RSNS = 0, 1 180 200 220 mV

(SCC)

V

= 475 mV (max) 428 475 523

(SCC)

V

= – 50 mV (min) – 30 – 50 – 70

(SCD)

V

= – 200 mV; RSNS = 0, 1 – 180 – 200 – 220 mV

(SCD)

V

= – 475 mV (max) – 428 – 475 – 523

(SCD)

V

= V

- V

(DSGON) (GS)

TA= – 40 ° C to 100 ° C V

(CHGON) (GS)

TA= – 40 ° C to 100 ° C

(DSGOFF) (CHGOFF)

(DSG)

= 10 M Ω ; DSG and CHG on; 8 12 16 V

= V

(CHG)

= 10 M Ω ; DSG and CHG on; 8 12 16 V

= V

(DSG)

= V

(CHG)

;

(PACK)

- V

;

(BAT)

- V

(PACK)

- V

(BAT)

(REG25)

V

= 2.41 V to 2.59 V,

(REG25)

/18

(PACK)

V

/18 1.02 × V

(BAT)

/18

(PACK)

/18

(BAT)

0.2 V

V

Product Folder Link(s): bq20z45

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.................................................................................................................................................................................................. SLUS800 – MARCH 2009

ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range (unless otherwise noted), TA= – 40 ° C to 85 ° C, V V

= 14 V, C

(BAT)

t

r

t

f

V

(ZVCHG)

Rise time µ s

Fall time µ s

ZVCHG clamp voltage BAT = 4.5 V 3.3 3.5 3.7 V

LOGIC; TA= – 40 ° C to 100 ° C (unless otherwise noted)

R

(PULLUP)

V

OL

Internal pullup resistance k Ω

Logic low output voltage level 0.4 V

LOGIC SMBC, SMBD, PFIN, PRES, SAFE, ALERT

V

IH

V

IL

V

OH

V

OL

C

I

(SAFE)

I

lkg

(2)

ADC

High-level input voltage 2.0 V Low-level input voltage 0.8 V Output voltage high Low-level output voltage PRES, PFIN, ALERT, IL= 7 mA; 0.4 V Input capacitance 5 pF SAFE source currents SAFE active, SAFE = V SAFE leakage current SAFE inactive – 0.2 0.2 µ A Input leakage current 1 µ A

Input voltage range TS1, TS2, using Internal V Conversion time 31.5 ms Resolution (no missing codes) 16 bits Effective resolution 14 15 bits

Integral nonlinearity ± 0.03 Offset error

Offset error drift Full-scale error

Full-scale error drift 50 Effective input resistance

COULOMB COUNTER

Input voltage range – 0.20 0.20 V Conversion time Single conversion 250 ms Effective resolution Single conversion 15 bits

Integral nonlinearity %FSR

= 1 µ F, C

(REG25)

= 2.2 µ F; typical values at TA= 25 ° C (unless otherwise noted)

(REG33)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CL= 4700 pF; V

≤ DSG ≤ V

(PACK)

+ 4V

(PACK)

CL= 4700 pF; V

(BAT)

≤ CHG ≤ V

+ 4V

(BAT)

CL= 4700pF; V

+ V

(PACK)

1V

≤ DSG ≤ V

(DSGON)

+ 40 200

(PACK)

CL= 4700 pF; V

+ V

(BAT)

≤ CHG ≤ V

(CHGON)

+ 1V

(BAT)

ALERT 60 100 200 RESET 1 3 6 ALERT 0.2 RESET; V

I

(RESET)

GPOD; I

(1)

(4)

(5)

(6)

IL= – 0.5 mA V

TA= 25 ° C to 85 ° C 2.5 18 µ V/ ° C

= 7V; V

(BAT)

= 200 µ A

= 50 µ A 0.6

(GPOD)

= 1.5 V;

(REG25)

REG25

– 0.6 V – 3 mA

(REG25)

ref

– 0.1 V to 0.20 V ± 0.007 ± 0.034 – 0.20 V to – 0.1 V ± 0.007

= 2.41 V to 2.59 V,

(REG25)

400 1000

40 200

– 0.5 V

– 0.2 1 V

140 250 µ V

± 0.1% ± 0.7%

8 M Ω

(

%FSR

3)

PPM/

° C

(1) RC[0:7] bus (2) Unless otherwise specified, the specification limits are valid at all measurement speed modes (3) Full-scale reference (4) Post-calibration performance and no I/O changes during conversion with SRN as the ground reference (5) Uncalibrated performance. This gain error can be eliminated with external calibration. (6) The A/D input is a switched-capacitor input. Since the input is switched, the effective input resistance is a measure of the average

resistance.

Product Folder Link(s): bq20z45

bq20z45

SLUS800 – MARCH 2009 ..................................................................................................................................................................................................

ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range (unless otherwise noted), TA= – 40 ° C to 85 ° C, V V

= 14 V, C

(BAT)

Offset error Offset error drift 0.4 0.7 µ V/ ° C Full-scale error

Full-scale error drift 150 Effective input resistance

INTERNAL TEMPERATURE SENSOR

V

(TEMP)

VOLTAGE REFERENCE

HIGH FREQUENCY OSCILLATOR

f

(OSC)

f

(EIO)

t

(SXO)

LOW FREQUENCY OSCILLATOR

f

(LOSC)

f

(LEIO)

t

(LSXO)

Temperature sensor voltage

Output voltage 1.215 1.225 1.230 V Output voltage drift 65

Operating frequency 4.194 MHz

Frequency error

Start-up time

Operating frequency 32.768 kHz

Frequency error

Start-up time

(7) Post-calibration performance (8) Reference voltage for the coulomb counter is typically V (9) Uncalibrated performance. This gain error can be eliminated with external calibration. (10) The CC input is a switched capacitor input. Since the input is switched, the effective input resistance is a measure of the average

resistance. (11) – 53.7 LSB/ ° C (12) The frequency error is measured from 4.194 MHz. (13) The frequency drift is included and measured from the trimmed frequency at V (14) The startup time is defined as the time it takes for the oscillator output frequency to be ± 3% (15) The frequency error is measured from 32.768 kHz.

= 1 µ F, C

(REG25)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(7)

(8) (9)

(12) (13)

(14)

(13) (15)

(14)

= 2.2 µ F; typical values at TA= 25 ° C (unless otherwise noted)

(REG33)

TA= 25 ° C to 85 ° C 10 µ V

(10)

(11)

TA= 25 ° C to 85 ° C 2.5 M Ω

TA= 20 ° C to 70 ° C – 2% 0.25% 2%

TA= 20 ° C to 70 ° C – 1.5% 0.25% 1.5%

/3.969 at V

ref

(REG25)

= 2.5 V, TA= 25 ° C.

= 2.5V, TA= 25 ° C

(REG25)

– 3% 0.25% 3%

– 2.5% 0.25% 2.5%

(REG25)

= 2.41 V to 2.59 V,

± 0.35%

-2.0 mV/ ° C

2.5 5 ms

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PPM/

° C

PPM/

° C

500 µ s

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.................................................................................................................................................................................................. SLUS800 – MARCH 2009

DATA FLASH CHARACTERISTICS OVER RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE

Typical Values at TA= 25 ° C and V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Data retention 10 Years Flash programming write-cycles 20k Cycles

t

(ROWPROG)

t

(MASSERASE)

t

(PAGEERASE)

I

(DDPROG)

I

(DDERASE)

RAM BACKUP

I

(RB)

V

(RB)

(1) Specified by design. Not production tested.

Row programming time See Mass-erase time 200 ms Page-erase time 20 ms Flash-write supply current 5 10 mA Flash-erase supply current 5 10 mA

RB data-retention input current nA

RB data-retention input voltage

= 2.5 V (unless otherwise noted)

(REG25)

(1)

V

> V

(RBI)

V

> V

(RBI)

, V

(RBI)MIN

, V

(RBI)MIN

< V

REG25 REG25

, TA= 85 ° C 1000 2500

IT –

< V

, TA= 25 ° C 90 220

IT –

1.7 V

SMBus TIMING CHARACTERISTICS

TA= – 40 ° C to 85 ° C Typical Values at TA= 25 ° C and V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f

(SMB)

f

(MAS)

t

(BUF)

t

(HD:STA)

t

(SU:STA)

t

(SU:STO)

t

(HD:DAT)

t

(SU:DAT)

t

(TIMEOUT)

t

(LOW)

t

(HIGH)

t

(LOW:SEXT)

t

(LOW:MEXT)

t

f

t

r

(1) The bq8040 times out when any clock low exceeds t (2) t

progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0). (3) t (4) t (5) Rise time tr= VILMAX – 0.15) to (V (6) Fall time tf= 0.9V

SMBus operating frequency Slave mode, SMBC 50% duty cycle 10 100 kHz SMBus master clock frequency 51.2 kHz Bus free time between start and stop

(see Figure 1 ) Hold time after (repeated) start (see Figure 1 ) 4 µ s Repeated start setup time (see Figure 1 ) 4.7 µ s Stop setup time (see Figure 1 ) 4 µ s

Data hold time (see Figure 1 )

Data setup time (see Figure 1 ) 250 ns Error signal/detect (see Figure 1 ) See Clock low period (see Figure 1 ) 4.7 µ s Clock high period (see Figure 1 ) See Cumulative clock low slave extend time See Cumulative clock low master extend time

(see Figure 1 ) Clock/data fall time See Clock/data rise time See

, Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving bq8040 that is in

(HIGH)

(LOW:SEXT) (LOW:MEXT)

is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.

is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.

MIN + 0.15)

MAX – 0.15)

IH

to (V

DD

IL

(TIMEOUT)

= 2.5 V (Unless Otherwise Noted)

REG25

Master mode, No clock low slave extend

4.7 µ s

Receive mode 0 ns Transmit mode 300

(1)

(2) (3)

(4)

See

(5) (6)

25 35 µ s

4 50 µ s

.

2 ms

25 ms 10 ms

300 ns

1000 ns

Product Folder Link(s): bq20z45

T

LOW

T

R

T

F

T

HD:STA

T

SU:DAT

T

HD:DAT

T

HD:STA

T

BUF

SCLK

SDATA

T

SU:STO

PSSP

SCLK

SDATA

Start Stop

T

LOW:SEXT

T

LOW:MEXT

T

LOW:MEXT

T

LOW:MEXT

SCLK

ACK

†

SCLK

ACK

†

T

SU:STA

T

HIGH

bq20z45

SLUS800 – MARCH 2009 ..................................................................................................................................................................................................

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A. SCLKACK is the acknowledge-related clock pulse generated by the master.

Figure 1. SMBus Timing Diagram

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FEATURE SET

Primary (1st Level) Safety Features

The bq20z45 supports a wide range of battery and system protection features that can easily be configured. The primary safety features include:

• Cell over/undervoltage protection

• Charge and discharge overcurrent

• Short Circuit

• Charge and discharge overtemperature with independent alarms and thresholds for each thermistor

• AFE Watchdog

Secondary (2nd Level) Safety Features

The secondary safety features of the bq20z45 can be used to indicate more serious faults via the SAFE (pin 7). This pin can be used to blow an in-line fuse to permanently disable the battery pack from charging or discharging. The secondary safety protection features include:

• Safety overvoltage

• Safety undervoltage

• Safety overcurrent in charge and discharge

• Safety overtemperature in charge and discharge with independent alarms and thresholds for each thermistor

• Charge FET and 0 Volt Charge FET fault

• Discharge FET fault

• Cell imbalance detection (active and at rest)

• Open thermistor detection

• AFE communication fault

Charge Control Features

The bq20z45 charge control features include:

• Supports JEITA temperature ranges. Reports charging voltage and charging current according to the active

temperature range.

• Handles more complex charging profiles. Allows for splitting the standard temperature range into 2

sub-ranges and allows for varying the charging current according to the cell voltage.

• Reports the appropriate charging current needed for constant current charging and the appropriate charging

voltage needed for constant voltage charging to a smart charger using SMBus broadcasts.

• Determines the chemical state of charge of each battery cell using Impedance Track™ and can reduce the

charge difference of the battery cells in fully charged state of the battery pack gradually using cell balancing algorithm during charging. This prevents fully charged cells from overcharging and causing excessive degradation and also increases the usable pack energy by preventing premature charge termination

• Supports pre-charging/zero-volt charging

• Supports charge inhibit and charge suspend if battery pack temperature is out of temperature range

• Reports charging fault and also indicate charge status via charge and discharge alarms.

Gas Gauging

The bq20z45 uses the Impedance Track™ Technology to measure and calculate the available charge in battery cells. The achievable accuracy is better than 1% error over the lifetime of the battery and there is no full charge discharge learning cycle required.

See Theory and Implementation of Impedance Track Battery Fuel-Gauging Algorithm application note (SLUA364 ) for further details.

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Lifetime Data Logging Features

The bq20z45 offers lifetime data logging, where important measurements are stored for warranty and analysis purposes. The data monitored include:

• Lifetime maximum temperature

• Lifetime minimum temperature

• Lifetime maximum battery cell voltage

• Lifetime minimum battery cell voltage

• Lifetime maximum battery pack voltage

• Lifetime minimum battery pack voltage

• Lifetime maximum charge current

• Lifetime maximum discharge current

• Lifetime maximum charge power

• Lifetime maximum discharge power

• Lifetime maximum average discharge current

• Lifetime maximum average discharge power

• Lifetime average temperature

Authentication

The bq20z45 supports authentication by the host using SHA-1.

Power Modes

The bq20z45 supports 3 different power modes to reduce power consumption:

• In Normal Mode, the bq20z45 performs measurements, calculations, protection decisions and data updates in

1 second intervals. Between these intervals, the bq20z45 is in a reduced power stage.

• In Sleep Mode, the bq20z45 performs measurements, calculations, protection decisions and data update in

adjustable time intervals. Between these intervals, the bq20z45 is in a reduced power stage. The bq20z45 has a wake function that enables exit from Sleep mode, when current flow or failure is detected.

• In Shutdown Mode the bq20z45 is completely disabled.

CONFIGURATION

Oscillator Function

The bq20z45 fully integrates the system oscillators. Therefore the bq20z45 requires no external components for this feature.

System Present Operation

The bq20z45 checks the PRES pin periodically (1s). If PRES input is pulled to ground by external system, the bq20z45 detects this as system present.

BATTERY PARAMETER MEASUREMENTS

The bq20z45 uses an integrating delta-sigma analog-to-digital converter (ADC) for current measurement, and a second delta-sigma ADC for individual cell and battery voltage, and temperature measurement.

Charge and Discharge Counting

The integrating delta-sigma ADC measures the charge/discharge flow of the battery by measuring the voltage drop across a small-value sense resistor between the SR1 and SR2 pins. The integrating ADC measures bipolar signals from -0.25 V to 0.25 V. The bq20z45 detects charge activity when V discharge activity when V

= V

SR

- V

(SRP)

is negative. The bq20z45 continuously integrates the signal over

(SRN)

time, using an internal counter. The fundamental rate of the counter is 0.65 nVh.

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= V

SR

- V

(SRP)

(SRN)

is positive and

bq20z45

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.................................................................................................................................................................................................. SLUS800 – MARCH 2009

Voltage

The bq20z45 updates the individual series cell voltages at one second intervals. The internal ADC of the bq20z45 measures the voltage, scales and calibrates it appropriately. This data is also used to calculate the impedance of the cell for the Impedance Track™ gas-gauging.

Current

The bq20z45 uses the SRP and SRN inputs to measure and calculate the battery charge and discharge current using a 5 m Ω to 20 m Ω typ. sense resistor.

Auto Calibration

The bq20z45 provides an auto-calibration feature to cancel the voltage offset error across SRN and SRP for maximum charge measurement accuracy. The bq20z45 performs auto-calibration when the SMBus lines stay low continuously for a minimum of 5 s.

Temperature

The bq20z45 has an internal temperature sensor and inputs for 2 external temperature sensor inputs TS1 and TS2 used in conjunction with two identical NTC thermistors (default are Semitec 103AT) to sense the battery environmental temperature. The bq20z45 can be configured to use internal or up to 2 external temperature sensors.

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COMMUNICATIONS

The bq20z45 uses SMBus v1.1 with Master Mode and package error checking (PEC) options per the SBS specification.

SMBus On and Off State

The bq20z45 detects an SMBus off state when SMBC and SMBD are logic-low for ≥ 2 seconds. Clearing this state requires either SMBC or SMBD to transition high. Within 1 ms, the communication bus is available.

SBS Commands

Table 1. SBS COMMANDS

SBS Size in Min Max

Mode Name Default Value Unit

Cmd Format Bytes Value Value

0x00 R/W ManufacturerAccess hex 2 0x0000 0xffff — — 0x01 R/W RemainingCapacityAlarm unsigned int 2 0 65535 300 mAh or 10mWh 0x02 R/W RemainingTimeAlarm unsigned int 2 0 65535 10 min 0x03 R/W BatteryMode hex 2 0x0000 0xe383 — — 0x04 R/W AtRate signed int 2 – 32768 32767 — mA or 10mW 0x05 R AtRateTimeToFull unsigned int 2 0 65534 — min 0x06 R AtRateTimeToEmpty unsigned int 2 0 65534 — min 0x07 R AtRateOK unsigned int 2 0 65535 — — 0x08 R Temperature unsigned int 2 0 65535 — 0.1 ° K 0x09 R Voltage unsigned int 2 0 65535 — mV 0x0a R Current signed int 2 – 32768 32767 — mA 0x0b R AverageCurrent signed int 2 – 32768 32767 — mA 0x0c R MaxError unsigned int 1 0 100 — % 0x0d R RelativeStateOfCharge unsigned int 1 0 100 — % 0x0e R AbsoluteStateOfCharge unsigned int 1 0 100+ — % 0x0f R/W RemainingCapacity unsigned int 2 0 65535 — mAh or 10mWh 0x10 R FullChargeCapacity unsigned int 2 0 65535 — mAh or 10mWh 0x11 R RunTimeToEmpty unsigned int 2 0 65534 — min 0x12 R AverageTimeToEmpty unsigned int 2 0 65534 — min 0x13 R AverageTimeToFull unsigned int 2 0 65534 — min 0x14 R ChargingCurrent unsigned int 2 0 65534 — mA 0x15 R ChargingVoltage unsigned int 2 0 65534 — mV 0x16 R BatteryStatus unsigned int 2 0x0000 0xffff — — 0x17 R/W CycleCount unsigned int 2 0 65535 — — 0x18 R/W DesignCapacity unsigned int 2 0 65535 4400 mAh or 10mWh 0x19 R/W DesignVoltage unsigned int 2 7000 16000 14400 mV 0x1a R/W SpecificationInfo unsigned int 2 0x0000 0xffff 0x0031 — 0x1b R/W ManufactureDate unsigned int 2 0 65535 01-Jan-1980 — 0x1c R/W SerialNumber hex 2 0x0000 0xffff 0x0001 — 0x20 R/W ManufacturerName String 20+1 — — Texas Inst. — 0x21 R/W DeviceName String 20+1 — — bq20z45 — 0x22 R/W DeviceChemistry String 4+1 — — LION — 0x23 R ManufacturerData String 14+1 — — — — 0x2f R/W Authenticate String 20+1 — — — — 0x3c R CellVoltage4 unsigned int 2 0 65535 — mV 0x3d R CellVoltage3 unsigned int 2 0 65535 — mV 0x3e R CellVoltage2 unsigned int 2 0 65535 — mV 0x3f R CellVoltage1 unsigned int 2 0 65535 — mV

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.................................................................................................................................................................................................. SLUS800 – MARCH 2009

Table 2. EXTENDED SBS COMMANDS

SBS Cmd Size in Default

0x45 R AFEData String 11+1 — — — — 0x46 R/W FETControl hex 2 0x00 0xff — — 0x4f R StateOfHealth hex 2 0x0000 0xffff — % 0x51 R SafetyStatus hex 2 0x0000 0xffff — — 0x53 R PFStatus hex 2 0x0000 0xffff — — 0x54 R OperationStatus hex 2 0x0000 0xffff — — 0x55 R ChargingStatus hex 2 0x0000 0xffff — — 0x57 R ResetData hex 2 0x0000 0xffff — — 0x58 R WDResetData unsigned int 2 0 65535 — — 0x5a R PackVoltage unsigned int 2 0 65535 — mV 0x5d R AverageVoltage unsigned int 2 0 65535 — mV 0x5e R TS1Temperature integer 2 – 400 1200 — 0.1 ° C 0x5f R TS2Temperature integer 2 – 400 1200 — 0.1 ° C 0x60 R/W UnSealKey hex 4 0x00000000 0xffffffff — — 0x61 R/W FullAccessKey hex 4 0x00000000 0xffffffff — — 0x62 R/W PFKey hex 4 0x00000000 0xffffffff — — 0x63 R/W AuthenKey3 hex 4 0x00000000 0xffffffff — — 0x64 R/W AuthenKey2 hex 4 0x00000000 0xffffffff — — 0x65 R/W AuthenKey1 hex 4 0x00000000 0xffffffff — — 0x66 R/W AuthenKey0 hex 4 0x00000000 0xffffffff — — 0x69 R SafetyStatus2 hex 2 0x0000 0x000f — — 0x6b R PFStatus2 hex 2 0x0000 0x000f — — 0x6c R/W ManufBlock1 String 20 — — — — 0x6d R/W ManufBlock2 String 20 — — — — 0x6e R/W ManufBlock3 String 20 — — — — 0x6f R/W ManufBlock4 String 20 — — — — 0x70 R/W ManufacturerInfo String 31+1 — — — — 0x71 R/W SenseResistor unsigned int 2 0 65535 — µ Ω 0x72 R TempRange hex 2 0x0000 0xffff — — 0x73 R LifetimeData String 32+1 — — — — 0x77 R/W DataFlashSubClassID hex 2 0x0000 0xffff — — 0x78 R/W DataFlashSubClassPage1 hex 32 — — — — 0x79 R/W DataFlashSubClassPage2 hex 32 — — — — 0x7a R/W DataFlashSubClassPage3 hex 32 — — — — 0x7b R/W DataFlashSubClassPage4 hex 32 — — — — 0x7c R/W DataFlashSubClassPage5 hex 32 — — — — 0x7d R/W DataFlashSubClassPage6 hex 32 — — — — 0x7e R/W DataFlashSubClassPage7 hex 32 — — — — 0x7f R/W DataFlashSubClassPage8 hex 32 — — — —

Mode Name Format Min Value Max Value Unit

Bytes Value

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APPLICATION SCHEMATIC

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Texas Instruments BQ20Z45DBT Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

DESCRIPTION

APPLICATIONS

SYSTEM PARTITIONING DIAGRAM

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

DATA FLASH CHARACTERISTICS OVER RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE

SMBus TIMING CHARACTERISTICS

FEATURE SET

Primary (1st Level) Safety Features

Secondary (2nd Level) Safety Features

Charge Control Features

Gas Gauging

Lifetime Data Logging Features

Authentication

Power Modes

CONFIGURATION

Oscillator Function

System Present Operation

BATTERY PARAMETER MEASUREMENTS

Charge and Discharge Counting

Voltage

Current

Auto Calibration

Temperature

COMMUNICATIONS

SMBus On and Off State

SBS Commands

APPLICATION SCHEMATIC