Texas Instruments BQ20Z45DBT Schematics

bq20z45

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.................................................................................................................................................................................................. SLUS800 – MARCH 2009

SBS 1.1-Compliant Gas Gauge and Protection Enabled With Impedance Track™

FEATURES

• Next Generation Patented Impedance Track™

Technology Accurately Measures Available Charge in Li-Ion and Li-Polymer Batteries

– Better Than 1% Error Over the Lifetime of

the Battery

• Supports the Smart Battery Specification

SBS V1.1

• Flexible Configuration for 2 to 4 Series Li-Ion

and Li-Polymer Cells

• Powerful 8-Bit RISC CPU With Ultralow Power

Modes

• Full Array of Programmable Protection

Features – Voltage, Current, and Temperature

• Satisfies JEITA Guidelines

• Added Flexibility to Handle More Complex

Charging Profiles

• Lifetime Data Logging

• Supports SHA-1 Authentication

• Complete Battery Protection and Gas Gauge

Solution in One Package

• Available in a 38-Pin TSSOP (DBT) package

DESCRIPTION

The bq20z45 SBS-compliant gas gauge and protection IC is a single IC solution designed for battery-pack or in-system installation. The bq20z45 measures and maintains an accurate record of available charge in Li-ion or Li-polymer batteries using its integrated high-performance analog peripherals, monitors capacity change, battery impedance, open-circuit voltage, and other critical parameters of the battery pack as well and reports the information to the system host controller over a serial-communication bus. Together with the integrated analog front-end (AFE) short-circuit and overload protection, the bq20z45 maximizes functionality and safety while minimizing external component count, cost, and size in smart battery circuits.

The implemented Impedance Track™ gas gauging technology continuously analyzes the battery impedance, resulting in superior gas-gauging accuracy. This enables remaining capacity to be calculated with discharge rate, temperature, and cell aging all accounted for during each stage of every cycle with high accuracy.

APPLICATIONS

• Notebook PCs

• Medical and Test Equipment

• Portable Instrumentation

AVAILABLE OPTIONS

– 40 ° C to 85 ° C bq20z45DBT

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com . (2) A single tube quantity is 50 units. (3) A single reel quantity is 2000 units

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 Impedance Track is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

38-PIN TSSOP (DBT) Tube 38-PIN TSSOP (DBT) Tape and Reel

(2)

PACKAGE

(1)

bq20z45DBTR

(3)

Coloumb

Counter

HWOver

Current&

ShortCircuit

Protection

CellVoltage

Multiplexer

N-ChannelFET

Drive

PreChargeFET

& GPODDrive

PowerMode

Control

SMBD

GSRN

GSRP

ASRN

ASRP

GPOD

ZVCHG

CHG

DSG

VC5

VC4

VC3

VC2

VC1

SMBC

CellBalancing

Temperature Measurement

DataFlash

Memory

SMB1.1

Impedance

Track™

GasGauging

SHA-1

Authentication

Over &Under

Voltage

Protection

Voltage

Measurement

OverCurrent

Protection

Oscillator

Charging Algorithm

FuseBlow

Detectionand

Logic

Over

Temperature

Protection

SAFE

PFIN

TS2

TS1

TOUT

PMS

Watchdog

Regulators

RESET

ALERT

REG33

REG25

VCELL+

ACK

VCC

VSS

MSRT

RBI

SystemControl AFEHWControl

Pack-

RSNS 5m -20m typ.W W

Pack+

SMBC

SMBD

bq20z45

GND

VC4

VC3

VC2

VC1

VDD

OUT

bq294xx

DSG

PACK

VCC

ALERT

ZVCHG

PRES

PMS

TS2

VSS

PFIN

REG33

SAFE

TOUT

SMBD

18 19

VCELL+

SMBC

CHG

BAT

VC1

VSS

VC2

RBI

VC3

REG25

VC4

VSS

VC5

MRST

ASRP

GSRN

ASRN

GSRP

RESET

VSS VSS

GPOD

TS1

bq20z45

SLUS800 – MARCH 2009 ..................................................................................................................................................................................................

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

SYSTEM PARTITIONING DIAGRAM

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bq20z45

DBT PACKAGE

(TOP VIEW)

Product Folder Link(s): bq20z45

bq20z45

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PIN FUNCTIONS

NO. NAME

1 DSG O High side N-chan discharge FET gate drive 2 PACK IA, P

3 VCC P 4 ZVCHG O P-chan pre-charge FET gate drive 5 GPOD OD

6 PMS I connected at CHG pin. Connect to VSS to disable 0V pre-charge using charge FET connected at

7 VSS P Negative device power supply input. Connect all VSS pins together for operation of device 8 REG33 P 3.3V regulator output. Connect at least a 2.2 µ F capacitor to REG33 and VSS 9 TOUT P Thermistor bias supply output

10 VCELL+ - Internal cell voltage multiplexer and amplifier output. Connect a 0.1 µ F capacitor to VCELL+ and VSS

11 ALERT I/OD

12 PRES I/OD System / Host present input. Pull up to TOUT

13 TS1 IA Temperature sensor 1 input

14 TS2 IA Temperature sensor 2 input

15 PFIN I/OD Fuse blow detection input

16 SAFE I/OD blow fuse signal output

17 SMBD I/OD SMBus data line

18 SMBC I/OD SMBus clock line

19 NC - Not connected

20, 21, 25,

22 GSRP IA Coulomb counter differential input. Connect to one side of the sense resistor

23 GSRN IA Coulomb counter differential input. Connect to one side of the sense resistor

24 MRST I Reset input for internal CPU core. connect to RESET for correct operation of device

26 REG25 P 2.5V regulator output. Connect at least a 1 µ F capacitor to REG25 and VSS

27 RBI P

29 RESET O Reset output. Connect to MSRT.

30 ASRN IA Short circuit and overload detection differential input. Connect to sense resistor

31 ASRP IA Short circuit and overload detection differential input. Connect to sense resistor

32 VC5 IA, P

33 VC4 IA, P

34 VC3 IA, P

35 VC2 IA, P and the negative voltage of the highest cell in 4 cell applications. Connect to VC3 in 2 cell stack

36 VC1 IA, P

37 BAT I, P Battery stack voltage sense input

38 CHG O High side N-chan charge FET gate drive (1) I = Input, IA = Analog input, I/O = Input/output, I/OD = Input/Open-drain output, O = Output, OA = Analog output, P = Power

VSS P Negative device power supply input. Connect all VSS pins together for operation of device

(1)

I/O

Battery pack input voltage sense input. It also serves as device wake up when device is in shutdown mode.

Positive device supply input. Connect to the center connection of the CHG FET and DSG FET to ensure device supply either from battery stack or battery pack input

High voltage general purpose open drain output. Can be configured to be used in pre-charge condition

Pre-charge mode setting input. Connect to PACK to enable 0v pre-charge using charge FET CHG pin.

Alert output. In case of short circuit condition, overload condition and watchdog time out this pin will be triggered.

RAM backup input. Connect a capacitor to this pin and VSS to protect loss of RAM data in case of short circuit condition

Cell voltage sense input and cell balancing input for the negative voltage of the bottom cell in cell stack.

Cell voltage sense input and cell balancing input for the positive voltage of the bottom cell and the negative voltage of the second lowest cell in cell stack.

Cell voltage sense input and cell balancing input for the positive voltage of the second lowest cell in cell stack and the negative voltage of the second highest cell in 4 cell applications.

Cell voltage sense input and cell balancing input for the positive voltage of the second highest cell applications

Cell voltage sense input and cell balancing input for the positive voltage of the highest cell in cell stack in 4 cell applications. Connect to VC2 in 3 or 2 cell stack applications

DESCRIPTION

Product Folder Link(s): bq20z45

bq20z45

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature (unless otherwise noted)

PIN UNIT

BAT, VCC – 0.3 V to 34 V PACK, PMS – 0.3 V to 34 V

Supply voltage range VC(n)-VC(n+1); n = 1, 2, 3, 4 – 0.3 V to 8.5 V

VC1, VC2, VC3, VC4 – 0.3 V to 34 V VC5 – 0.3 V to 1 V PFIN, SMBD, SMBC – 0.3 V to 6 V

Input voltage range

Output voltage range TOUT, ALERT, REG33 – 0.3 V to 6 V

OUT

Maximum combined sink current for input pins PRES, PFIN, SMBD, SMBC 50 mA

Operating free-air temperature range – 40 ° C to 85 ° C

Functional temperature – 40 ° C to 100 ° C

Storage temperature range – 65 ° C to 150 ° C

stg

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

TS1, TS2, SAFE, VCELL+, PRES; ALERT – 0.3 V to V MRST, GSRN, GSRP, RBI – 0.3 V to V ASRN, ASRP – 1 V to 1 V DSG, CHG, GPOD – 0.3 V to 34 V ZVCHG – 0.3 V to V

RESET – 0.3 V to 7 V REG25 – 0.3 V to 2.75 V

(1)

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+ 0.3 V

(REG25)

+ 0.3 V

(REG25)

(BAT)

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

PIN MIN NOM MAX UNIT

(STARTUP)

(GPOD)

(REG25)

(REG33)

(VCELL+)

(PACK)

(1) Use an external resistor to limit the current to GPOD to 1mA in high voltage application. (2) Use an external resistor to limit the inrush current PACK pin required.

Supply voltage VCC, BAT 4.5 25 V Minimum startup voltage VCC, BAT, PACK 5.5 V

VC(n)-VC(n+1); n = 1,2,3,4 0 5 V VC1, VC2, VC3, VC4 0 V

Input Voltage Range VC5 0 0.5 V

ASRN, ASRP – 0.5 0.5 V

PACK, PMS 0 25 V Output Voltage Range GPOD 0 25 V Drain Current

(1)

GPOD 1 mA

2.5V LDO Capacitor REG25 1 µ F

3.3V LDO Capacitor REG33 2.2 µ F Cell Voltage Output Capacitor VCELL+ 0.1 µ F PACK input block resistor

(2)

PACK 1 k Ω

SUP

Product Folder Link(s): bq20z45

bq20z45

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ELECTRICAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted), TA= – 40 ° C to 85 ° C, V V

= 14 V, C

(BAT)

SUPPLY CURRENT

(NORMAL)

(SLEEP)

(SHUTDOWN)

Firmware running 550 µ A Sleep Mode CHG FET on; DSG FET on 124 µ A

Shutdown Mode 0.1 1 µ A

SHUTDOWN WAKE; TA= 25 ° C (unless otherwise noted)

(PACK)

Shutdown exit at V

SRx WAKE FROM SLEEP; TA= 25 ° C (unless otherwise noted)

Positive or negative wake threshold

(WAKE)

(WAKE_ACR)

(WAKE_TCO)

(WAKE)

with 1.00 mV, 2.25 mV, 4.5 mV and 9 1.25 10 mV mV programmable options

Accuracy of V

Temperature drift of V Time from application of current and

wake of bq8040

POWER-ON RESET

IT –

hys

RST

Negative-going voltage input Voltage at REG25 pin 1.70 1.80 1.90 V Hysteresis V

RESET active low time 100 250 560 µ s

WATCHDOG TIMER

WDTINT

WDWT

2.5V LDO; I

(REG25)

Δ V

(REG25TEMP)

Δ V

(REG25LINE)

Δ V

(REG25LOAD)

(REG25MAX)

3.3V LDO; I

(REG33)

Δ V

(REG33TEMP)

Δ V

(REG33LINE)

Δ V

(REG33LOAD)

Watchdog start up detect time 250 500 1000 ms Watchdog detect time 50 100 150 µ s

(REG33OUT)

Regulator output voltage I

Regulator output change with I temperature TA= – 40 ° C to 100 ° C

Line regulation 3 10 mV

Load Regulation mV

Current Limit 5 40 75 mA

(REG25OUT)

Regulator output voltage I

Regulator output change with I temperature TA= – 40 ° C to 100 ° C

Line regulation 3 10 mV

Load Regulation mV

= 1 µ F, C

(REG25)

= 2.2 µ F; typical values at TA= 25 ° C (unless otherwise noted)

(REG33)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CHG FET off; DSG FET on 90 µ A CHG FET off; DSG FET off 52 µ A

threshold 1 µ A

STARTUP

= 1 mV;

(WAKE)

= 0, RSNS1 = 0, RSNS0 = 1;

(WAKE)

= 2.25 mV;

(WAKE)

) = 1, RSNS1 = 0, RSNS0 = 1; -0.8 0.8

(WAKE

= 0, RSNS1 = 1, RSNS0 = 0;

(WAKE)

accuracy 0.5 %/ ° C

(WAKE)

= 4.5 mV;

(WAKE)

= 1, RSNS1 = 1, RSNS0 = 1; -1.0 1.0

(WAKE)

= 0, RSNS1 = 1, RSNS0 = 0;

(WAKE)

= 9 mV;

(WAKE)

= 1, RSNS1 = 1, RSNS0 = 1;

(WAKE)

– V

IT+

IT-

active low time after power up or watchdog reset

= 0 mA; TA= 25 ° C (unless otherwise noted)

4.5 < VCC or BAT < 25 V; ) ≤ 16 mA; 2.41 2.5 2.59 V

(REG25OUT

TA= – 40 ° C to 100 ° C

(REG25OUT)

= 2 mA;

5.4 < VCC or BAT < 25 V;

(REG25OUT)

0.2 mA ≤ I

= 2 mA

(REG25OUT) (REG25OUT)

≤ 2 mA 7 25 ≤ 16 mA 25 50

drawing current until REG25 = 2 V to 0 V

= 0 mA; TA= 25 ° C (unless otherwise noted)

4.5 < VCC or BAT < 25 V;

(REG33OUT)

TA= – 40 ° C to 100 ° C

(REG33OUT)

≤ 25 mA; 3 3.3 3.6 V

= 2 mA;

5.4 < VCC or BAT < 25 V;

(REG33OUT)

0.2 mA ≤ I

0.2mA ≤ I

= 2 mA

(REG33OUT)

≤ 2 mA 7 17

≤ 25 mA 40 100

= 2.41 V to 2.59 V,

(REG25)

-0.7 0.7

-1.4 1.4

1 10 ms

50 150 250 mV

± 0.2 %

Product Folder Link(s): bq20z45

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ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range (unless otherwise noted), TA= – 40 ° C to 85 ° C, V V

= 14 V, C

(BAT)

(REG33MAX)

Current Limit mA

THERMISTOR DRIVE

(TOUT)

DS(on)

Output voltage I TOUT pass element resistance 50 100 Ω

VCELL+ HIGH VOLTAGE TRANSLATION

(VCELL+OUT)

(VCELL+REF)

(VCELL+PACK)

(VCELL+BAT)

Translation output 0.965 0.975 0.985 V

CMMR Common mode rejection ratio VCELL+ 40 dB

K Cell scale factor

(VCELL+OUT)

(VCELL+O)

VCnL

Drive Current to VCELL+ capacitor 12 18 µ A

CELL offset error -18 -1 18 mV VC(n) pin leakage current VC1, VC2, VC3, VC4, VC5 = 3 V -1 0.01 1 µ A

CELL BALANCING

(BAL)

internal cell balancing FET resistance 200 400 600 Ω

HARDWARE SHORT CIRCUIT AND OVERLOAD PROTECTION; TA= 25 ° C (unless otherwise noted)

(OL)

(SCC)

(SCD)

OL detection threshold voltage accuracy

SCC detection threshold voltage accuracy

SCD detection threshold voltage accuracy

Delay time accuracy ± 15.25 µ s Protection circuit propagation delay 50 µ s

FET DRIVE CIRCUIT; TA= 25 ° C (unless otherwise noted)

(DSGON)

(CHGON)

(DSGOFF)

(CHGOFF)

DSG pin output on voltage V

CHG pin output on voltage V

DSG pin output off voltage V CHG pin output off voltage V

= 1 µ F, C

(REG25)

= 2.2 µ F; typical values at TA= 25 ° C (unless otherwise noted)

(REG33)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

drawing current until REG33 = 3 V 25 100 145 short REG33 to VSS, REG33 = 0 V 12 65

= 0 mA; TA= 25 ° C V

(TOUT)

= 1 mA; R

(TOUT)

)/ 1 mA; TA= – 40 ° C to 100 ° C

(TOUT)

VC(n) - VC(n+1) = 0 V; TA= – 40 ° C to 100 ° C

VC(n) - VC(n+1) = 4.5 V; TA= – 40 ° C to 100 ° C

= (V

DS(on)

(REG25)

0.950 0.975 1

0.275 0.3 0.375

internal AFE reference voltage ; TA= – 40 ° C to 100 ° C

Voltage at PACK pin; 0.98 × 1.02 × TA= – 40 ° C to 100 ° C V

/18 V

(PACK)

Voltage at BAT pin; 0.98 × TA= – 40 ° C to 100 ° C V

/18

(BAT)

K= {VCELL+ output (VC5=0V; VC4=4.5V) - VCELL+ output (VC5=0V; 0.147 0.150 0.153 VC4=0V)}/4.5

K= {VCELL+ output (VC2=13.5V; VC1=18V) - VCELL+ output 0.147 0.150 0.153 (VC5=13.5V; VC1=13.5V)}/4.5

VC(n) - VC(n+1) = 0V; VCELL+ = 0 V; TA= – 40 ° C to 100 ° C

CELL output (VC2 = VC1 = 18 V) CELL output (VC2 = VC1 = 0 V)

for internal FET switch at

DS(on)

VDS= 2 V; TA= 25 ° C

VOL= 25 mV (min) 15 25 35 VOL= 100 mV; RSNS = 0, 1 90 100 110 mV VOL= 205 mV (max) 185 205 225 V

= 50 mV (min) 30 50 70

(SCC)

= 200 mV; RSNS = 0, 1 180 200 220 mV

(SCC)

= 475 mV (max) 428 475 523

(SCC)

= – 50 mV (min) – 30 – 50 – 70

(SCD)

= – 200 mV; RSNS = 0, 1 – 180 – 200 – 220 mV

(SCD)

= – 475 mV (max) – 428 – 475 – 523

(SCD)

= V

- V

(DSGON) (GS)

TA= – 40 ° C to 100 ° C V

(CHGON) (GS)

TA= – 40 ° C to 100 ° C

(DSGOFF) (CHGOFF)

(DSG)

= 10 M Ω ; DSG and CHG on; 8 12 16 V

= V

(CHG)

= 10 M Ω ; DSG and CHG on; 8 12 16 V

= V

(DSG)

= V

(CHG)

;

(PACK)

- V

;

(BAT)

- V

(PACK)

- V

(BAT)

(REG25)

= 2.41 V to 2.59 V,

(REG25)

/18

(PACK)

/18 1.02 × V

(BAT)

/18

(PACK)

/18

(BAT)

0.2 V

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