TEXAS INSTRUMENTS bq2058T Technical data

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bq2058T

Lithium Ion PackSupervisor

For 2-Cell Packs

Features

➤ Protects and individually moni-

tors two Li-Ion series cells for overvoltage,undervoltage

➤ Monitors pack for overcurrent ➤ Designed for battery pack inte-

gration

➤ Minimal external components ➤ Drives external FET switches ➤ Selectable overvoltage (V

thresholds

Mask programmable by

Benchmarq

- Standard version–4.25V

➤ Supply current: 12µA typical ➤ Sleep current: 0.7µA typical ➤ 16-pin 150-mil narrow SOIC

General Description

The bq2058T Lithium Ion Pack Supervisor is designed to control the charge and discharge cell voltage limits for two lithium-ion (Li-Ion) series cells, accommodating battery packs containing series/parallel configurations. The low operating current does not overdischarge the cells during periods of storage and does not significantly increase the system discharge load. The bq2058T can be part of a low-cost Li-Ion charge control system

)

within the battery pack. The bq2058T controls two external

FETs to limit the charge and discharge potentials. The bq2058T allows charging when each individual cell voltage is below V voltage on any cell exceeds VOVfor a user-configurable delay period (t the open-drain CHG pin goes to the high-impedance state, shutting off

(overvoltage limit). If the

charge to the battery pack. This safety feature prevents overcharge of any cell within the battery pack. After an overvoltage condition occurs, each cell must fall below V for the bq2058T to re-enable charging.

(charge enable voltage)

The bq2058T protects batteries from overdischarge. If the voltage on any cell falls below V limit) for a user-configurable delay period (t low, shutting off the battery discharge.

), the DSG output is driven

UVD

This safety feature prevents overdischarge of any cell within the battery pack.

The bq2058T also stops discharge on detection of an overcurrent condition, such as a short circuit. If an overcurrent condition occurs for a userconfigurable delay period (t DSG output is driven low, disconnect-

ing the load from the pack. DSG re-

OVD

mains low until removal of the short circuit or overcurrent condition.

(undervoltage

), the

OCD

Pin Connections

July 1997

BAT

BAT BAT

CHG

CTL

CSL

2N 1N

16-Pin Narrow SOIC

DSG

UVD

OVD

OCD

CC CSH BAT

PN2058T1.eps

Pin Names

CHG Charge control output CTL Pack disable input V

Low potential input

CSL Overcurrent sense low-side

input

BAT

Battery 2 negative input

Battery 1 negative input

DSG Discharge control output UVD Undervoltagedelay input OVD Overvoltage delay input OCD Overcurrent delay input V

High potential input

CSH Overcurrent sense high-side

input

BAT

Battery 1 positive input

bq2058T

Pin Descriptions

CHG Charge control output

This open-drain output controls the charge path to the battery pack. Charging is allowed when high.

CTL Packdisable input

When high, this input allows an external source to disable the pack by making both DSG and CHG inactive. For normal operation,the CTL pin is low.

CSL Overcurrent sense low-side input

BAT

DSG Discharge control output

Low potential input

This input is connected between the low-side discharge FET (or sense resistor) and BAT2Nto enable overcurrent sensing in the battery pack’sground path.

Battery 2 negative inputs (3 pins)

These pins are connected to the negative terminal of the cell designated BAT2 in Figure 2.

Battery 1 negative input

This input is connected to the negative terminal of the cell designated BAT1 in Figure 2.

This push-pull output controls the discharge path to the battery pack. Discharge is allowed when high.

UVD Undervoltage delay input

This input uses an external capacitor to V to set the undervoltage delay timing.

OVD Overvoltage delay input

This input uses an external capacitor to V to set the overvoltage delay timing.

OCD Overcurrent delay input

This input uses an external capacitor to V to set the overcurrent delay timing.

High potential inputs (2 pins)

CSH Overcurrent sense high-side input

This input is connected between the high-side discharge FET (or sense resistor) and BAT1Pto enable overcurrent sense in the battery pack’spositive supply path.

BAT

Battery 1 positive input

This input is connected to the positive terminal of the cell designated BAT1in Figure2.

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Cell Inputs

Pin 9 Pin 8

Pin 7

Pin 3

Chip Negative

Supply

B1P B1N

B2N

Sel2 Sel1

bq2058T

Sel2

Sel1

D CK

Any_Above_V

Edge

Non-Retrigger

Reset Capacitor

OVD

Pin 13 Discharge Off Delay Capacitor Input

Out

Oneshot

All_Below_V

D CK

Reset

Over_charge

Pin 1

CHG

Charge Control Output (open drain)

July 1997

Any_Below_V

Sel2

Sel1

D CK

UVD Pin 14 Charge Off Delay Capacitor Input

Pin 10 Pin 9

Pin 4 Pin 7

Sel2

Sel1

D CK

Pin 10

Pin 9

Pin 4 Pin 7

CSH B1P

B2N

160mV

CSL

Overcurrent Delay Capacitor Input

Pin 12

160mV

OCD

CSH B1P

CSL

B2N

Edge

Non-Retrigger

Reset Capacitor

70mV

Edge

Reset Capacitor

Pin 2

Out

Oneshot

Out

Non-Retrigger

Oneshot

CTL

External Output Control

D CK

Reset

Sleep

D CK

Reset

Pin 16

DSG

Discharge Control Output (totem pole)

Over_current

BD2058T1.eps

Figure 1. Block Diagram

bq2058T

Functional Description

Figure 1 is a block diagram outlining the major components of the bq2058T. Figure 2 shows a low-side control connection diagram. The following sections detail the various functional aspects of the bq2058T.

Thresholds

The bq2058T monitors the lithium ion pack for the conditions listed below. Shown with these conditions are the respective thresholds used to determine if that condition exists:

Overvoltage (VOV)

■

Undervoltage (VUV)

■

Overcurrent (V

■

Charge Enable (VCE)

■

Charge Detect (VCD)

■

POS

OCH,VOCL

)

2N 2N 2N

DSG V UVD OVD OCD V CSH

BAT

CHG CTL V

CSL BAT BAT BAT

BAT

bq2058T

The bq2058T samples a cell every 60ms (typical). Every sample is a fully differential measurement of each cell. During this sample period, the bq2058T compares the measurements with these thresholds to determine if any of the these conditions exist:V

OV,VUV

,and VCE.

Overcurrent and charge detect are conditions that are not sampled, but are continuously monitored.

Initialization

On initial power-up, such as connecting the battery pack for the first time to the bq2058T,the bq2058T enters the low-power sleep mode, disabling the DSG output. It is

recommended that a top to bottom cell connection be made at pack assembly for proper initialization. A charging supplymust be applied to the bq2058T

circuit to enable the pack. See Low-Power Sleep Mode and Charge Detect sections.

BAT1

NEG

Figure 2. 2-Cell Connection Diagram, Low-Side Control

FG2058T1.eps

BAT2

July 1997

bq2058T

Low-Power Sleep Mode

The bq2058T enters the low-power sleep mode in two different ways:

1. On initial power-up.

2. After the detection of an undervoltage condi-

tion–V

When the bq2058T enters the low-power sleep mode, DSG is driven low and the device consumes 0.7µA (typical). The bq2058T only comes out of low-power sleep mode when a valid charge detect condition exists.

Charge Detect

The bq2058T continuously monitors for a charge detect condition. A valid charge detect condition exists when either of the conditions is true:

CSL < BAT

CSH > BAT

- 70mV (VCD)

+ 70mV (VCD)

A valid charge detect enables the DSG output, allowing charging of the lithium ion cells. This is accomplished by applying the charging supply to the pack.

Undervoltage

Undervoltage (or overdischarge) protection is asserted when any cell voltage drops below the VUVthreshold and remains below the VUVthreshold for a time exceeding a user-configurable delay (t

). The DSG

UVD

output is driven low, disabling the discharge of the pack. The bq2058T then enters the low-power sleep mode. VUVis defined as follows:

= 2.25V

Overvoltage

Overvoltage (or overcharge) protection is asserted when any cell voltage exceeds the VOVthreshold and remains above the VOVthreshold for a time exceeding a userconfigurable delay (t high impedance state, disabling charge into the battery pack. Since the charge control output is an open drain output, a pull-down resistor is needed from the CHG pin to the negative side of the pack. This pulls the gate of the charge FET low when the CHG pin goes to high impedance. Charging is disabled until a valid charge enable exists. See Charge Enable section.

Important note: If any battery pin floats (BAT BAT1N,BAT2N), the bq2058T assumes an overvoltage has occurred.

Because of different manufacturers’ specifications for overvoltage thresholds, the bq2058T can be available with different V different voltage thresholds.

July 1997

). The CHG pin goes to the

OVD

options. Table 1 summarizes these

Table 1. Overvoltage Threshold Options

Part # VOVLimit

bq2058T 4.25V bq2058TR 4.35V

The overvoltage threshold limits are programmed at Benchmarq. The bq2058T is the standard option that is more readily available for sampling and prototyping purposes. Please contact Benchmarq for other voltage threshold and tolerance options.

Charge Enable

A valid charge enable indicates that an overvoltage (overcharge) condition no longer exists and that the pack is ready to accept further charge. Once overvoltage protection is asserted, charging will not be enabled until all cell voltages fall below VCE. The VCEthreshold is a function of V

and changes with different VOVlim-

OV,

its.

CE=VOV

- 150mV

Overcurrent

The bq2058T detects an overcurrent (or short circuit) condition only in the discharge direction. Overcurrent protection is asserted when either of the conditions occurs and remain for a time exceeding a userconfigurable delay (t

where:

OCL

OCH

When either of these conditions occurs, DSG is driven low, disconnecting the load from the pack. DSG remains low until both of the voltage conditions are false, indicating removal of the short-circuit condition. The user can facilitate clearing these conditions by inserting the battery pack into a charger.

The high-side overcurrent sense can be disabled by con-

necting CSH to BAT greater than BAT1P. If high-side detection is disabled, low-side detection must be used with CSL.

The FETs in the charge/discharge path controlled by the CHG and DSG pins affect the overcurrent level. The on-resistance of these FETs need to be taken into account when determining overcurrent levels.

OCD

CSL > BAT CSH < BAT1P-V

2N+VOCL

OCH

= 160mV (low-side detect)

= 160mV (high-side detect)

. This ensures that CSH is never

bq2058T

CHG and DSG States

The CHG and DSG output truth table is shown below:

Condition CHG pin DSG pin

Normal operation High High Overvoltage Z High Undervoltage High Low Overcurrent High Low Floating battery input Z Indeterminate CTL = high Z Low

The polarities of CHG and DSGare mask programmable at Benchmarq. Push-pull vs. open-drain configuration is also mask-configurable at Benchmarq. Please contact Benchmarq for availability of these variations.

PackDisable Input–CTL

The CTL pin is used to electrically disconnect the battery from the pack terminals through an externally supplied signal. When CTL is taken high, CHG goes to the high impedance state and DSG is driven low. Any load on the pack terminals will be interpreted as an overcurrent condition by the bq2058T with the overcurrent delay timer held in reset. When the CTL pin is driven low, the overcurrent delay timer is allowed to start. If the programmed delay (t recovery circuit, if implemented, will be unable to correct the overcurrent situation prior to the delay timeout. It is recommended that a delay time of greater than 10ms (C

≥ 0.01µF) be used if the CTL pin function

OCD

is to be utilized.

) is too short, the overcurrent

OCD

Important note: If CTL floats, it is internally pulled high making both DSG and CHG inactive, thus disabling the pack. If CTL is not used, it should be tied to V

The polarity of CTL is mask-programmable at Benchmarq. Please contact Benchmarq for other polarity options.

Protection DelayTimers

The delay time between the detection of an overcurrent, overvoltage, or undervoltage condition and the deactivation of the CHG and/or DSG outputs is user-configurable by the selection of capacitorvalues between VCCand OCD, OVD,and UVD pins (respectively. SeeTable2 below.

The fault condition must persist through the entire delay period, or the bq2058T may not deactivate either FET control output.

Figure 3 shows a step-by-step event cycle for the bq2058T.

Table 2.Protection Delay Timers

Protection

Feature

Overcurrent t Overvoltage t Undervoltage t

Delay

Period

OCD OVD UVD

Capacitor from

VCCto:

OCD OVD UVD

Capacitor Time

0.010µF

0.100µF

Notes: 1. The delay time versus capacitance can be approximated bythe following equations:.

For t For t

OCD OVD,tUVD

(s)

≈ 1.2 ∗ C ≈ 9.5 ∗ C

, where 0.001µF ≤ C≤ 0.1µF

(µf)

, where 0.01µF ≤ C≤ 1µF

(µf)

2. Overvoltage andundervoltage conditions are sampled by thebq2058T. The delay in Table 2 is in addition to the time required for the bq2058T todetect the violation, which may vary from 0 to 120 ms depending on where in the sampling periodthe violation occurs. Overcurrent is continuously monitored and is subject to a delay of approximately 1.5ms.

Typical

12ms 950ms ±40% 950ms ±40%

Tolerance

±40%

July 1997

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