TEXAS INSTRUMENTS bq2012 Technical data

bq2012

Gas Gauge IC With

Slow-Charge Control

Features

Conservative and repeatable

➤

measurement of available charge
in rechargeable batteries

Charge control output

➤

Designed for battery pack inte

➤

gration

120µA typical standby current

-

(self-discharge estimation mode)

Small size enables imple-

-

mentations in as little as
square inch of PCB

➤ Integrate within a system or as a

stand-alone device

Display capacity via single-

-

wire serial communication
port or direct drive of LEDs

➤ Measurements compensated for

current and temperature

➤ Self-discharge compensation us-

ing internal temperature sensor

➤

16-pin narrow SOIC

1

2

General Description

The bq2012 Gas Gauge IC is in
tended for battery-pack or in-system
installation to maintain an accurate
record of available battery charge.
The IC monitors a voltage drop
across a sense resistor connected in

­series between the negative battery

terminal and ground to determine
charge and discharge activity of the
battery.

Self-discharge of NiMH and NiCd
batteries is estimated based on an
internal timer and temperature sen
sor. Compensations for battery tem
perature and rate of charge or dis­charge are applied to the charge,
discharge, and self-discharge calcu­lations to provide available charge
information across a wide range of
operating conditions. Battery capac­ity is automatically recalibrated, or
“learned,” in the course of a dis­charge cycle from full to empty.

The bq2012 includes a charge con­trol output that, when used with
other full-charge safety termination
methods, can provide a cost-effective

means of controlling charge based
on the battery's charge state.

-

Nominal available charge may be di
rectly indicated using a five- or six­segment LED display. These seg
ments are used to graphically indi
cate nominal available charge.

The bq2012 supports a simple
single-line bidirectional serial link to
an external processor (common
ground). The bq2012 outputs battery
information in response to external
commands over the serial link.

Internal registers include available

­charge, temperature, capacity, battery

­ID, battery status, and programming

pin settings. To support subassembly
testing, the outputs may also be con­trolled. The external processor may
also overwrite some of the bq2012 gas
gauge data registers.

The bq2012 may operate directly
from three or four cells. With the
REF output and an external transis­tor, a simple, inexpensive regulator
can be built to provide V

CC

greater number of cells.

-

-

-

across a

Pin Connections Pin Names

LCOM LED common output

SEG

/PROG1LED segment 1/

SEG

SEG

SEG

SEG

SEG

1

2

3

4

5

6

program 1 input

/PROG2LED segment 2/

program 2 input

/PROG3LED segment 3/

program 3 input

/PROG4LED segment 4/

program 4 input

/PROG5LED segment 5/

program 5 input

/PROG6LED segment 6/

program 6 input

9/96 B

LCOM

SEG1/PROG

SEG2/PROG

SEG3/PROG

SEG4/PROG

SEG5/PROG

SEG6/PROG

1

2

3

4

5

6

V

SS

16-Pin Narrow SOIC

16

15

14

13

12

11

10

9

PN201201.eps

V

CC

REF

CHG

DQ

EMPTY

SB

DISP

SR

1

2

3

4

5

6

7

8

REF Voltage reference output

CHG

Charge control output

DQ Serial communications

input/output

EMPTY Empty battery indicator

output

SB Battery sense input

DISP

Display control input

SR Sense resistor input

V

CC

V

SS

3.0–6.5V

System ground

1

bq2012

Pin Descriptions

LCOM

SEG
SEG

PROG
PROG

PROG
PROG

PROG

PROG

CHG

LED common output

Open-drain output switches V
current for the LEDs. The switch is off dur
ing initialization to allow reading of the soft
pull-up or pull-down program resistors.
LCOM is also high impedance when the dis
play is off.

LED display segment outputs (dual func

–

1

tion with PROG

6

Each output may activate an LED to sink
the current sourced from LCOM.

Programmed full count selection inputs

–

1

(dual function with SEG

2

These three-level input pins define the pro
grammed full count (PFC) thresholds de
scribed in Table 2.

Gas gauge rate selection inputs (dual

–

3

function with SEG

4

These three-level input pins define the scale
factor described in Table 2.

Self-discharge rate selection (dual func-

5

tion with SEG

This three-level input pin defines the selfdis­charge compensation rate shown in Table 1.

Display mode selection (dual function

6

with SEG

)

6

This three-level pin defines the display op
eration shown in Table 1.

Charge control output

This open-drain output becomes active low
when charging is allowed. Valid charging
conditions are described in the Charge Con
trol section.

–PROG6)

1

)

5

–SEG4)

3

–SEG2)

1

to source

CC

-

-

-

-

-

-

-

SR

DISP

SB

EMPTY

DQ

REF

V

CC

V

SS

Sense resistor input

The voltage drop (V
sistor R

is monitored and integrated over

S

) across the sense re

SR

time to interpret charge and discharge activ
ity. The SR input is tied to the high side of
the sense resistor. V
charge, and V

SR>VSS

SR<VSS

indicates charge. The
effective voltage drop (V
bq2012 is V

SR+VOS

(see Table 5).

indicates dis

) as seen by the

SRO

Display control input

high disables the LED display. DISP

DISP
tied to VCCallows PROGXto connect directly
to V

or VSSinstead of through a pull-up or

CC

pull-down resistor. DISP

floating allows the
LED display to be active during a valid
charge or during discharge if the NAC regis
ter is updated at a rate equivalent to V

-4mV. DISP

low activates the display. See

SRO

Table 1.

Secondary battery input

This input monitors the single-cell voltage
potential through a high-impedance resis­tive divider network for end-of-discharge
voltage (EDV) thresholds, maximum charge
voltage (MCV), and battery removed.

Battery empty output

This open-drain output becomes high­impedance on detection of a valid end-of­discharge voltage (V

) and is low following

EDVF

the next application of a valid charge.

Serial I/O pin

This is an open-drain bidirectional pin.

Voltage reference output for regulator

REF provides a voltage reference output for
an optional micro-regulator.

Supply voltage input

Ground

-

-

-

-

≤

2

bq2012

Functional Description

General Operation

The bq2012 determines battery capacity by monitoring
the amount of charge input to or removed from a re
chargeable battery. The bq2012 measures discharge and
charge currents, estimates self-discharge, monitors the
battery for low-battery voltage thresholds, and compen
sates for temperature and charge/discharge rates. The
charge measurement is made by monitoring the voltage
across a small-value series sense resistor between the
negative battery terminal and ground. The available
battery charge is determined by monitoring this voltage
over time and correcting the measurement for the envi
ronmental and operating conditions.

bq2012

Gas Gauge IC

LCOM

SEG1/PROG

SEG2/PROG

SEG3/PROG

SEG4/PROG

SEG5/PROG

SEG6/PROG

CHG

REF

V

CC

SB

1

2

DISP

3

4

SR

5

V

SS

6

EMPTY

DQ

Figure 1 shows a typical battery pack application of the
bq2012 using the LED display capability as a charge­state indicator. The bq2012 can be configured to display
capacity in either a relative or an absolute display mode.
The relative display mode uses the last measured dis
charge capacity of the battery as the battery “full” refer
ence. The absolute display mode uses the programmed

­full count (PFC) as the full reference, forcing each seg

ment of the display to represent a fixed amount of
charge. A push-button display feature is available for

­momentarily enabling the LED display.

The bq2012 monitors the charge and discharge currents
as a voltage across a sense resistor (see R

in Figure 1).

S

A filter between the negative battery terminal and the
SR pin may be required if the rate of change of the bat

-

tery current is too great.

R

1

1M

Q1
ZVNL110A

C1

0.1 F
V

V

CC

CC

RB

RB

1

2

R

S

-

-

-

-

Indicates optional.

Directly connect to VCC across 3 or 4 cells (3 to 4.8V nominal,should not
exceed 6.5V) with a resistor and a Zener diode to limit voltage during charge.
Otherwise, R1, C1, and Q1 are needed for regulation of >4 cells.
The value of R1 depends on the number of cells.

Programming resistors (6 max.) and ESD-protection diodes are not shown.

R-C on SR may be required (application-specific), where the R
should not exceed 100k.

Figure 1. Battery Pack Application Diagram—LED Display

3

Charger

Load

FG201201.eps

bq2012

Voltage Thresholds

In conjunction with monitoring VSRfor charge/discharge
currents, the bq2012 monitors the single-cell battery po
tential through the SB pin. The single-cell voltage po
tential is determined through a resistor/divider network
per the following equation:

RB

1

N

RB

2

where N is the number of cells, RB
positive battery terminal, and RB

1=−

is connected to the

1

is connected to the

2

negative battery terminal. The single-cell battery volt
age is monitored for the end-of-discharge voltage (EDV)
and for maximum cell voltage (MCV). EDV threshold
levels are used to determine when the battery has
reached an “empty” state, and the MCV threshold is used
for fault detection during charging.

Two EDV thresholds for the bq2012 are fixed at:

EDV1 (early warning) = 1.05V

EDVF (empty) = 0.95V

If V

is below either of the two EDV thresholds, the as-

SB

sociated flag is latched and remains latched, independ­ent of V

During discharge and charge, the bq2012 monitors V

, until the next valid charge.

SB

SR

for various thresholds. These thresholds are used to
compensate the charge and discharge rates. Refer to the
count compensation section for details. EDV monitoring
is disabled if V
ond after V

SR

-250mV typical and resumes

≤

SR

> -250mV.

1

sec-

2

EMPTY Output

The EMPTY output switches to high impedance when
V

SB<VEDF

curs. The bq2012 also monitors V

2.25V. V

and remains latched until a valid charge oc

relative to V

falling from above V

SB

SB

resets the device.

MCV

MCV

Reset

The bq2012 recognizes a valid battery whenever VSBis
greater than 0.1V typical. V

rising from below 0.25V

SB

or falling from above 2.25V resets the device. Reset can
also be accomplished with a command over the serial
port as described in the Register Reset section.

Temperature

The bq2012 internally determines the temperature in
10°C steps centered from -35°C to +85°C. The tempera
ture steps are used to adapt charge and discharge rate
compensations, self-discharge counting, and available
charge display translation. The temperature range is

available over the serial port in 10°C increments as
shown below:

-

TMPGG (hex) Temperature Range

-

0x < -30°C

1x -30°C to -20°C

2x -20°C to -10°C

-

3x -10°C to 0°C

4x 0°C to 10°C

5x 10°C to 20°C

6x 20°C to 30°C

7x 30°C to 40°C

8x 40°C to 50°C

9x 50°C to 60°C

Ax 60°C to 70°C

Bx 70°C to 80°C

Cx > 80°C

Layout Considerations

The bq2012 measures the voltage differential between
the SR and V

­pin) is greatly affected by PC board layout. For optimal

,

results, the PC board layout should follow the strict rule
of a single-point ground return. Sharing high-current
ground with small signal ground causes undesirable
noise on the small signal nodes. Additionally:

■

The capacitors (SB and VCC) should be placed as
close as possible to the SB and V
and their paths to V
A high-quality ceramic capacitor of 0.1µf is
recommended for V

■

The sense resistor (RS) should be as close as possible
to the bq2012.

-

■

The R-C on the SR pin should be located as close as
possible to the SR pin. The maximum R should not
exceed 100K.

pins. VOS(the offset voltage at the SR

SS

pins, respectively,

should be as short as possible.

SS

.

CC

CC

4

bq2012

Gas Gauge Operation

The operational overview diagram in Figure 2 illustrates
the operation of the bq2012. The bq2012 accumulates a
measure of charge and discharge currents, as well as an
estimation of self-discharge. Charge and discharge cur
rents are temperature and rate compensated, whereas
self-discharge is only temperature compensated.

The main counter, Nominal Available Charge (NAC),
represents the available battery capacity at any given
time. Battery charging increments the NAC register,
while battery discharging and self-discharge decrement
the NAC register and increment the DCR (Discharge
Count Register).

The Discharge Count Register (DCR) is used to update
the Last Measured Discharge (LMD) register only if a
complete battery discharge from full to empty occurs
without any partial battery charges. Therefore, the
bq2012 adapts its capacity determination based on the
actual conditions of discharge.

The battery’s initial capacity is equal to the programmed
full count (PFC) shown in Table 2. Until LMD is up­dated, NAC counts up to but not beyond this threshold
during subsequent charges. This approach allows the
gas gauge to be charger-independent and compatible
with any type of charge regime.

1. Last Measured Discharge (LMD) or learned

battery capacity:

LMD is the last measured discharge capacity of the
battery. On initialization (application of V

-

tery replacement), LMD = PFC. During subsequent
discharges, the LMD is updated with the latest
measured capacity in the Discharge Count Register
(DCR) representing a discharge from full to below
EDV1. A qualified discharge is necessary for a ca
pacity transfer from the DCR to the LMD register.
The LMD also serves as the 100% reference thresh
old used by the relative display mode.

2. Programmed Full Count (PFC) or initial bat

tery capacity:

The initial LMD and gas gauge rate values are pro
grammed by using PROG
provides the 100% reference for the absolute dis

–PROG4. The PFC also

1

play mode. The bq2012 is configured for a given ap
plication by selecting a PFC value from Table 2.
The correct PFC may be determined by multiplying
the rated battery capacity in mAh by the sense re
sistor value:

Battery capacity (mAh)*sense resistor (Ω) =

PFC (mVh)

Selecting a PFC slightly less than the rated capac­ity for absolute mode provides capacity above the
full reference for much of the battery’s life.

CC

or bat

-

-

-

-

-

-

-

-

Inputs

Main Counters

and Capacity

Reference (LMD)

Outputs

Charge
Current

Rate and

Rate and

Temperature

Temperature

Compensation

Compensation

+

Available Charge

Nominal

Available

Charge

(NAC)

Temperature

Translation

Chip-Controlled

LED Display

Discharge

Current

Rate and

Temperature

Compensation

--

<

Discharged

Last

Measured

(LMD)

Serial

Port

Qualified
Transfer

Temperature Step,
Other Data

Figure 2. Operational Overview

5

Self-Discharge

Timer

Temperature

Compensation

+

+

Discharge

Count

Register

(DCR)

FG201002.eps

bq2012

Example: Selecting a PFC Value

Given:

Sense resistor = 0.1

Ω

Number of cells = 6
Capacity = 2200mAh, NiCd battery
Current range = 50mA to 2A
Absolute display mode
Serial port only
Self-discharge =
Voltage drop over sense resistor = 5mV to 200mV

C

64

Therefore:

Select:

PFC = 33792 counts or 211mVh
PROG

= float

1

PROG

= float

2

PROG

= float

3

PROG

= low

4

PROG

= float

5

PROG

= float

6

The initial full battery capacity is 211mVh
(2110mAh) until the bq2012 “learns” a new capac
ity with a qualified discharge from full to EDV1.

2200mAh*0.1Ω= 220mVh

Table 1. bq2012 Programming

Pin

Connection

H Self-discharge disabled NAC = PFC on reset LED disabled

Z

L

Note: PROG5and PROG6states are independent.

PROG

5

Self-Discharge Rate

NAC

64

NAC

47

PROG

6

Display Mode

Absolute

LED enabled on discharge when

V

< -4mV or during a valid charge

SRO

Relative LED on

Table 2. bq2012 Programmed Full Count mVh Selections

-

DISP

Display State

Programmed

PROG

1 2 PROG

-- -

Full

x

Count

(PFC)

Scale =

1/80

PROG

= L PROG4= Z

4

= H PROG3= Z PROG3= L PROG3= H PROG3= Z PROG3= L

3

Scale =

1/160

Scale =

1/320

Scale =

1/640

Scale =

1/1280

Scale =

1/2560

Units

mVh/
count

H H 49152 614 307 154 76.8 38.4 19.2 mVh

H Z 45056 563 282 141 70.4 35.2 17.6 mVh

H L 40960 512 256 128 64.0 32.0 16.0 mVh

Z H 36864 461 230 115 57.6 28.8 14.4 mVh

Z Z 33792 422 211 106 53.0 26.4 13.2 mVh

Z L 30720 384 192 96.0 48.0 24.0 12.0 mVh

L H 27648 346 173 86.4 43.2 21.6 10.8 mVh

L Z 25600 320 160 80.0 40.0 20.0 10.0 mVh

L L 22528 282 141 70.4 35.2 17.6 8.8 mVh

V

is equivalent to 2

SR

counts/sec. (nom.)

90 45 22.5 11.25 5.56 2.8 mV

6

bq2012

3. Nominal Available Charge (NAC):

NAC counts up during charge to a maximum
value of LMD and down during discharge and
self-discharge to 0. NAC is reset to 0 on initializa
tion (PROG
is set to PFC on initialization if PROG
prevent overstatement of charge during periods of

= Z or low) and on reaching EDV1. NAC

6

= high. To

6

overcharge, NAC stops incrementing when NAC =
LMD.

4. Discharge Count Register (DCR):

The DCR counts up during discharge independent
of NAC and could continue increasing after NAC
has decremented to 0. DCR stops counting when
EDV1 is reached. Prior to NAC = 0 (empty battery),
both discharge and self-discharge increment the
DCR. After NAC = 0, only discharge increments the
DCR. The DCR resets to 0 when NAC = LMD. The
DCR does not roll over but stops counting when it
reaches FFFFh.

The DCR value becomes the new LMD value on the
first charge after a valid discharge to V

EDV1

if:

No valid charge initiations (charges greater than
256 NAC counts; where V

SRO>VSRQ

) occurred dur­ing the period between NAC = LMD and EDV1 de­tected.

The self-discharge count is not more than 4096
counts (8% to 18% of PFC, specific percentage
threshold determined by PFC).

The temperature is ≥ 0°C when the EDV1 level is
reached during discharge.

The valid discharge flag (VDQ) indicates whether
the present discharge is valid for LMD update.

Charge Counting

Charge activity is detected based on a positive voltage
on the V
bq2012 increments NAC at a rate proportional to V
(VSR+VOS) and, if enabled, activates the LED display if
the rate is equivalent to V
crement the NAC after compensation for charge rate
and temperature.

The bq2012 determines charge activity sustained at a
continuous rate equivalent to V
charge equates to sustained charge activity greater than
256 NAC counts. Once a valid charge is detected, charge
counting continues until V
a programmable threshold as described in the Digital
Magnitude Filter section. The default value for V
375µV.

input. If charge activity is detected, the

SR

> 4mV. Charge actions in

SRO

. A valid

SRQ.VSRQ

falls below V

SRO

SRO>VSRQ

SRO

SRQ

Charge Control

Charge control is provided by the CHG output. This
output is asserted continuously when:

-

NAC < 0.94*LMD and

0.95V < V
0°C < Temp < 50°C and
BRM=0

This output is asserted at a
and high for 7.5 sec) when the above conditions are not
met and:

NAC < LMD and

0.95V < V
Temp < 50°C and
BRM=0

This output is also asserted at a
and high for 7.5 sec) for a 2-hour top-off period after:

NAC = LMD and
Temp < 50°C and

0.95V < V
BRM=0

This output is inactive when:

NAC = LMD (after a 2-hour top-off period) or
Temp > 50°C or
V

SB

V

SB

BRM=1

The top-off timer (2 hours) is reset to allow another top­off after the battery is discharged to 0.8*LMD (PROG
=L)or0.8*PFC (PROG6=ZorH).

Caution: The charge control output (CHG
be used with other forms of charge termination
such as∆T/∆t and -∆V.

If charge terminates due to maximum temperature, the
battery temperature must fall typically 10°C below 50°C
before the charge output becomes active again.

-

Discharge Counting

All discharge counts where V
register to decrement and the DCR to increment. Ex
ceeding the fast discharge threshold (FDQ) if the rate is
equivalent to V
abled. The display becomes inactive after V
above -4mV. V

is

described in the Digital Magnitude Filter section. The
default value for V

is

SB

SB

SB

< 0.95V or
> 2.25V or

SRO

SRD

< 2.25V and

1

duty cycle (low for 0.5 sec

16

< 2.25V and

1

duty cycle (low for 0.5 sec

16

< 2.25V and

SRO<VSRD

cause the NAC

< -4mV activates the display, if en

is a programmable threshold as

is -300µV.

SRD

) should

rises

SRO

6

-

-

7

bq2012

Self-Discharge Estimation

The bq2012 continuously decrements NAC and increments
DCR for self-discharge based on time and temperature.
The self-discharge count rate is programmed to be a nomi

1

nal

64

*

by PROG

NAC or

1

NAC per day or disabled as selected

47

. This is the rate for a battery whose tempera

5

*

ture is between 20°–30°C. The NAC register cannot be
decremented below 0.

Count Compensations

The bq2012 determines fast charge when the NAC up
dates at a rate of≥2 counts/sec. Charge and discharge are
compensated for temperature and charge/discharge
rate before updating the NAC and/or DCR. Self-dis
charge estimation is compensated for temperature be
fore updating the NAC or DCR.

Charge Compensation

Two charge efficiency compensation factors are used for
trickle charge and fast charge. Fast charge is defined as
a rate of charge resulting in≥2 NAC counts/sec (≥0.15C
to 0.32C depending on PFC selections; see Table 2). The
compensation defaults to the fast charge factor until the
actual charge rate is determined.

Temperature adapts the charge rate compensation factors
over three ranges between nominal, warm, and hot tem­peratures. The compensation factors are shown below.

Charge

Temperature

<30°C 0.80 0.95

30– 40°C 0.75 0.90

> 40°C 0.65 0.80

Discharge Compensation

Corrections for the rate of discharge are made by adjusting
an internal discharge compensation factor. The discharge
factor is based on the dynamically measured V
compensation factors during discharge are:

Approximate

V

Threshold

SR

V

> -150 mV 1.00 100%

SR

V

< -150 mV 1.05 95%

SR

Temperature compensation during discharge also takes place.
At lower temperatures, the compensation factor increases by

0.05 for each 10°C temperature range below 10°C.

Compensation factor = 1.0 + (0.05*N)

Trickle Charge
Compensation

Discharge

Compensation

Factor Efficiency

Fast Charge

Compensation

. The

SR

Where N = Number of 10°C steps below 10°C and

-150mV < V

SR

<0.

For example:

­T > 10°C : Nominal compensation,N = 0

-

0°C<T<10°C: N = 1 (i.e., 1.0 becomes 1.05)

-10°C<T<0°C:N=2(i.e., 1.0 becomes 1.10)

-20°C<T<-10°C: N = 3 (i.e., 1.0 becomes 1.15)

-20°C<T<-30°C: N = 4 (i.e., 1.0 becomes 1.20)

-

Self-Discharge Compensation

The self-discharge compensation is programmed for a

-

nominal rate of

-

the rate for a battery within the 20–30°C temperature

1

64

NAC or

*

1

NAC per day. This is

47

*

range (TMPGG = 6x). This rate varies across 8 ranges
from <10°C to >70°C, doubling with each higher tem
perature step (10°C). See Table 3.

Table 3. Self-Discharge Compensation

Temperature

Step

< 10°C

10–20°C

20–30°C

30–40°C

40–50°C

50–60°C

PROG

Typical Rate

= Z PROG5= L

5

NAC

256

NAC

128

NAC

64

NAC

32

NAC

16

NAC

8

NAC

NAC

NAC

NAC

NAC

NAC

Digital Magnitude Filter

The bq2012 has a programmable digital filter to eliminate
charge and discharge counting below a set threshold. The de
fault setting is -0.30mV for V

and +0.38mV for V

SRD

proper digital filter setting can be calculated using the following
equation. Table 4 shows typical digital filter settings.

V

(mV) = -45 / DMF

SRD

V

(mV) = -1.25*V

SRQ

SRD

Table 4. Typical Digital Filter Settings

DMF

Hex.

75 4B -0.60 0.75

100 64 -0.45 0.56

150 (default) 96 -0.30 0.38

175 AF -0.26 0.32
200 C8 -0.23 0.28

DMF

V

SRD

(mV)

V
(mV)

188

23 5.

11 8.

588.

94

47

SRQ

SRQ

-

-

. The

8

bq2012

Error Summary

Capacity Inaccurate

The LMD is susceptible to error on initialization or if no
updates occur. On initialization, the LMD value in
cludes the error between the programmed full capacity
and the actual capacity. This error is present until a
valid discharge occurs and LMD is updated (see DCR de
scription). The other cause of LMD error is battery
wear-out. As the battery ages, the measured capacity
must be adjusted to account for changes in actual battery
capacity.

A Capacity Inaccurate counter (CPI) is maintained and
incremented each time a valid charge occurs (qualified
by NAC; see the CPI register description) and is reset
whenever LMD is updated from the DCR. The counter
does not wrap around but stops counting at 255. The ca
pacity inaccurate flag (CI) is set if LMD has not been up
dated following 64 valid charges.

Current-Sensing Error

Table 5 illustrates the current-sensing error as a func­tion of V
charge counts to the NAC register when V
V

OS

. A digital filter eliminates charge and dis-

SR

) is between V

SRQ

and V

SRD

.

SRO(VSR

Communicating With the bq2012

The bq2012 includes a simple single-pin (DQ plus re­turn) serial data interface. A host processor uses the in­terface to access various bq2012 registers. Battery char
acteristics may be easily monitored by adding a single
contact to the battery pack. The open-drain DQ pin on
the bq2012 should be pulled up by the host system, or may
be left floating if the serial interface is not used.

The interface uses a command-based protocol, where the
host processor sends a command byte to the bq2012.
The command directs the bq2012 to either store the next
eight bits of data received to a register specified by the
command byte or output the eight bits of data specified
by the command byte.

The communication protocol is asynchronous return-to­one. Command and data bytes consist of a stream of eight
bits that have a maximum transmission rate of 333
bits/sec. The least-significant bit of a command or data
byte is transmitted first. The protocol is simple enough
that it can be implemented by most host processors using

­either polled or interrupt processing. Data input from the

bq2012 may be sampled using the pulse-width capture
timers available on some microcontrollers.

­Communication is normally initiated by the host proces

sor sending a BREAK command to the bq2012. A
BREAK is detected when the DQ pin is driven to a
logic-low state for a time, t
should then be returned to its normal ready-high logic
state for a time, t
a command from the host processor.

The return-to-one data bit frame consists of three dis

-

tinct sections. The first section is used to start the

-

transmission by either the host or the bq2012 taking the
DQ pin to a logic-low state for a period, t
next section is the actual data transmission, where the
data should be valid by a period, t
edge used to start communication. The data should be
held for a period, t
sample the data bit.

+

The final section is used to stop the transmission by return­ing the DQ pin to a logic-high state by at least a period,
t

, after the negative edge used to start communication.

SSU

The final logic-high state should be held until a period, t
allow time to ensure that the bit transmission was stopped
properly. The timings for data and break communication are
given in the serial communication timing specification and

­illustration sections.

Communication with the bq2012 is always performed
with the least-significant bit being transmitted first.
Figure 3 shows an example of a communication se
quence to read the bq2012 NAC register.

. The bq2012 is now ready to receive

BR

, to allow the host or bq2012 to

DV

or greater. The DQ pin

B

STRH,B

, after the negative

DSU

bq2012 Registers

The bq2012 command and status registers are listed in
Table 6 and described in the following sections.

. The

,to

SV

-

-

-

Table 5. Current-Sensing Error as a Function of V

Symbol Parameter Typical Maximum Units Notes

INL

INR

Integrated non-linearity
error

Integrated non­repeatability error

2

±

1

±

4

±

2

±

Add 0.1% per °C above or below 25°C

%

and 1% per volt above or below 4.25V.

Measurement repeatability given

%

similar operating conditions.

SR

9

bq2012

Table 6. bq2012 Command and Status Registers

Symbol

CMDR

FLGS1

TMPGG

NACH

NACL

BATID

LMD

FLGS2

PPD

PPU

CPI

DMF

RST Reset register 39h Write RST 0000000

Register

Name

Command
register

Primary
status flags
register

Temperature
and gas gauge
register

Nominal
available
charge high
byte register

Nominal
available
charge low
byte register

Battery
identification
register

Last meas­ured dis­charge regis­ter

Secondary
status flags
register

Program pin
pull-down
register

Program pin
pull-up regis
ter

Capacity
inaccurate
count register

Digital mag
nitude filter
register

Loc.

(hex)

-

-

Read/

Write

00h Write W/R

01h Read CHGS BRP BRM CI VDQ CHG

02h Read TMP3 TMP2 TMP1 TMP0 GG3 GG2 GG1 GG0

03h R/W NACH7 NACH6 NACH5 NACH4 NACH3 NACH2 NACH1 NACH0

17h Read NACL7 NACL6 NACL5 NACL4 NACL3 NACL2 NACL1 NACL0

04h R/W BATID7 BATID6 BATID5 BATID4 BATID3 BATID2 BATID1 BATID0

05h R/W LMD7 LMD6 LMD5 LMD4 LMD3 LMD2 LMD1 LMD0

06h Read CR DR2 DR1 DR0 n/u n/u n/u OVLD

07h Read n/u n/u PPD6 PPD5 PPD4 PPD3 PPD2 PPD1

08h Read n/u n/u PPU6 PPU5 PPU4 PPU3 PPU2 PPU1

09h Read CPI7 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 CPI0

0ah R/W DMF7 DMF6 DMF5 DMF4 DMF3 DMF2 DMF1 DMF0

7(MSB) 6543210(LSB)

AD6 AD5 AD4 AD3 AD2 AD1 AD0

Control Field

EDV1 EDVF

Note: n/u = not used

10

bq2012

Written by Host to bq2012

CMDR = 03h

LSB MSB LSB MSB

1110

Break 0 0 0 0 0 0 1 0 1 0 0 1

DQ

Figure 3. Typical Communication With the bq2012

Command Register (CMDR)

The write-only CMDR register is accessed when eight
valid command bits have been received by the bq2012.
The CMDR register contains two fields:

W/R bit

■

Command address

■

The W/R

bit of the command register is used to select
whether the received command is for a read or a write
function.

The W/R

values are:

CMDR Bits

7654 3 2 1 0

W/R

Where W/R

- -- - - - -

is:

0 The bq2012 outputs the requested register

contents specified by the address portion of
CMDR.

1 The following eight bits should be written

to the register specified by the address por

-

tion of CMDR.

The lower seven-bit field of CMDR contains the address
portion of the register to be accessed. Attempts to write
to invalid addresses are ignored.

CMDR Bits

765 4 3 2 1 0

- AD6 AD5 AD4 AD3 AD2 AD1

AD0

(LSB)

Primary Status Flags Register (FLGS1)

The read-only FLGS1 register (address=01h) contains
the primary bq2012 flags.

Received by Host to bq2012

NAC = 65h

TD201201.eps

The charge status flag (CHGS) is asserted when a
valid charge rate is detected. Charge rate is deemed
valid when V

SRO>VSRQ

.AV

of less than V

SRO

SRQ

or

discharge activity clears CHGS.

The CHGS values are:

FLGS1 Bits

7654 3 2 1 0

CHGS - -- - - - -

Where CHGS is:

0 Either discharge activity detected or V

V

SRQ

1V

SRO>VSRQ

SRO

<

The battery replaced flag (BRP) is asserted whenever
the potential on the SB pin (relative to V

), VSB, falls

SS

from above the maximum cell voltage, MCV (2.25V), or
rises above 0.1V. The BRP flag is also set when the
bq2012 is reset (see the RST register description). BRP
is reset when either a valid charge action increments
NAC to be equal to LMD, or a valid charge action is de
tected after the EDV1 flag is asserted. BRP = 1 signifies
that the device has been reset.

The BRP values are:

FLGS1 Bits

7654 3 2 1 0

- BRP - - - - - -

Where BRP is:

0 Battery is charged until NAC = LMD or dis

-

charged until the EDV1 flag is asserted

1V

dropping from above MCV, VSBrising

SB

from below 0.1V, or a serial port initiated
reset has occurred

-

11

bq2012

The battery removed flag (BRM) is asserted whenever
the potential on the SB pin (relative to V

) rises above

SS

MCV or falls below 0.1V. The BRM flag is asserted until
the condition causing BRM is removed.

The BRM values are:

FLGS1 Bits

76543 2 1 0

- - BRM - - - - -

Where BRM is:

0 0.1V < V

1 0.1 V > V

< 2.25V

SB

or VSB> 2.25V

SB

The capacity inaccurate flag (CI) is used to warn the
user that the battery has been charged a substantial
number of times since LMD has been updated. The CI
flag is asserted on the 64th charge after the last LMD
update or when the bq2012 is reset. The flag is cleared
after an LMD update.

The CI values are:

FLGS1 Bits

7654 3 2 1 0

---CI- - - -

Where CI is:

0 When LMD is updated with a valid full dis-

charge

1 After the 64th valid charge action with no

LMD updates

The valid discharge flag (VDQ) is asserted when the
bq2012 is discharged from NAC = LMD. The flag re
mains set until either LMD is updated or one of three
actions that can clear VDQ occurs:

■

The self-discharge count register (SDCR) has
exceeded the maximum acceptable value (4096
counts) for an LMD update.

■

A valid charge action sustained at V

SRO>VSRQ

for at

least 256 NAC counts.

■

The EDV1 flag was set at a temperature below 0°C

The VDQ values are:

FLGS1 Bits

7654 3 2 1 0

- - - - VDQ - - -

Where VDQ is:

0 SDCR≥4096, subsequent valid charge ac

tion detected, or EDV1 is asserted with the
temperature less than 0°C

1 On first discharge after NAC = LMD

The charge control flag, CHG
the CHG

pin is asserted (see the charge control section

on page 7 for a description of the CHG

The CHG

values are:

, is asserted whenever

pin function).

FLGS1 Bits

7654 3 2 1 0

- - - - - CHG

Where CHG

0 When the CHG

is:

pin is asserted active low,

--

signifying that the bq2012 is in a state to
allow charge activity.

1 When the CHG

pin is high-impedance, sig­nifying that no charge activity should take
place.

The first end-of-discharge warning flag (EDV1)
warns the user that the battery is almost empty. The
first segment pin, SEG

, is modulated at a 4Hz rate if

1

the display is enabled once EDV1 is asserted, which
should warn the user that loss of battery power is immi­nent. The EDV1 flag is latched until a valid charge has
been detected.

The EDV1 values are:

FLGS1 Bits

7654 3 2 1 0

- - - - - - EDV1 -

­Where EDV1 is:

0 Valid charge action detected, V

1V

< 1.05V providing that OVLD=0 (see

SB

SB

1.05V

≥

FLGS2 register description)

The final end-of-discharge warning flag (EDVF) flag
is used to warn that battery power is at a failure condi
tion. All segment drivers are turned off. The EDVF flag
is latched until a valid charge has been detected. The
EMPTY pin is also forced to a high-impedance state on
assertion of EDV1. The host system may pull EMPTY
high, which may be used to disable circuitry to prevent
deep-discharge of the battery.

-

-

12

bq2012

The EDVF values are:

FLGS1 Bits

7654 3 2 1 0

- - - - - - - EDVF

Where EDVF is:

0 Valid charge action detected, V

1V

< 0.95V providing that OVLD=0 (see

SB

SB

0.95V

≥

FLGS2 register description)

Temperature and Gas Gauge Register
(TMPGG)

The read-only TMPGG register (address=02h) contains
two data fields. The first field contains the battery tem
perature. The second field contains the available charge
from the battery.

TMPGG Temperature Bits

7 6 5 4 3210

TMP3 TMP2 TMP1 TMP0 - - -

The bq2012 contains an internal temperature sensor.
The temperature is used to set charge and discharge ef­ficiency factors as well as to adjust the self-discharge co­efficient.

The temperature register contents may be translated as
shown in Table 7.

The bq2012 calculates the available charge as a function
of NAC, temperature, and a full reference, either LMD
or PFC. The results of the calculation are available via
the display port or the gas gauge field of the TMPGG
register. The register is used to give available capacity

1

in

increments from 0 to

16

TMPGG Gas Gauge Bits

7654 3 2 1 0

- - - - GG3 GG2 GG1 GG0

15

.

16

Table 7. Temperature Register Translation

TMP3 TMP2 TMP1 TMP0 Temperature

0000 T < -30°C

0001-30°C < T < -20°C

0010-20°C < T < -10°C

0011-10°C < T < 0°C

01000°C < T < 10°C

010110°C < T < 20°C

011020°C < T < 30°C

011130°C < T < 40°C

100040°C < T < 50°C

100150°C < T < 60°C

-

101060°C < T < 70°C

101170°C < T < 80°C

1100 T > 80°C

The adjustment between > 0°C and -20°C<T<0°Chas
a 10°C hysteresis.

Nominal Available Charge Registers
(NACH/NACL)

The read/write NACH high-byte register (address=03h)
and the read-only NACL low-byte register (address=17h)
are the main gas gauging register for the bq2012. The
NAC registers are incremented during charge actions and
decremented during discharge and self-discharge actions.
The correction factors for charge/discharge efficiency are
applied automatically to NAC.

On reset, if PROG
cleared to 0; if PROG
= 0. When the bq2012 detects a valid EDV1, NACH and
NACL are reset to 0. Writing to the NAC registers affects

the available charge counts and, therefore, affects the
bq2012 gas gauge operation. Do not write the NAC regis
ters to a value greater than LMD.

= Z or low, NACH and NACL are

6

= high, NACH = PFC and NACL

6

-

The gas gauge display and the gas gauge portion of the
TMPGG register are adjusted for cold temperature de
pendencies. A piece-wise correction is performed as fol
lows:

Temperature Available Capacity Calculation

> 0°C NAC / “Full Reference”

-20°C < T < 0°C 0.75*NAC / “Full Reference”

< -20°C 0.5*NAC / “Full Reference”

Battery Identification Register (BATID)

­The read/write BATID register (address=04h) is avail

­able for use by the system to determine the type of bat

tery pack. The BATID contents are retained as long as
V

is greater than 2V. The contents of BATID have no

CC

effect on the operation of the bq2012. There is no de
fault setting for this register.

Last Measured Discharge Register (LMD)

LMD is a read/write register (address=05h) that the
bq2012 uses as a measured full reference. The bq2012
adjusts LMD based on the measured discharge capacity

13

-

-

-

bq2012

of the battery from full to empty. In this way the
bq2012 updates the capacity of the battery. LMD is set
to PFC during a bq2012 reset.

Secondary Status Flags Register (FLGS2)

The read-only FLGS2 register (address=06h) contains
the secondary bq2012 flags.

The charge rate flag (CR) is used to denote the fast
charge regime. Fast charge is assumed whenever a
charge action is initiated. The CR flag remains asserted
if the charge rate does not fall below 2 counts/sec.

The CR values are:

FLGS2 Bits

76543 2 1 0

CR - - - - - - -

Where CR is:

0 When charge rate falls below 2 counts/sec

1 When charge rate is above 2 counts/sec

The fast charge regime efficiency factors are used when
CR = 1. When CR = 0, the trickle charge efficiency fac­tors are used. The time to change CR varies due to the
user-selectable count rates.

The discharge rate flags, DR2–0, are bits 6–4.

FLGS2 Bits

7 6 5 4 3210

- DR2 DR1 DR0 - - -

They are used to determine the current discharge re
gime as follows:

DR2 DR1 DR0 VSR(V)

000 V

001 V

The overload flag (OVLD) is asserted when a discharge
overload is detected, V

< -250mV. OVLD remains as

SR

serted as long as the condition persists and is cleared
when V

> -250mV. The overload condition is used to

SR

stop sampling of the battery terminal characteristics for
end-of-discharge determination. Sampling is re-enabled

0.5 secs after the overload condition is removed.

FLGS2 Bits

76543 2 1 0

- - - - - - - OVLD

> -150mV

SR

< -150mV

SR

DR2–0 and OVLD are set based on the measurement of the
voltage at the SR pin relative to V

. The rate at which

SS

this measurement is made varies with device activity.

Program Pin Pull-Down Register (PPD)

The read-only PPD register (address=07h) contains some of
the programming pin information for the bq2012. The seg
ment drivers, SEG
location, PPD

, have a corresponding PPD register

1–6

. A given location is set if a pull-down re

1–6

sistor has been detected on its corresponding segment
driver. For example, if SEG

and SEG4have pull-down

1

resistors, the contents of PPD are xx001001.

Program Pin Pull-Up Register (PPU)

The read-only PPU register (address=08h) contains the
rest of the programming pin information for the
bq2012. The segment drivers, SEG
sponding PPU register location, PPU

, have a corre

1–6

. A given loca

1–6

tion is set if a pull-up resistor has been detected on its cor
responding segment driver. For example, if SEG
SEG

have pull-up resistors, the contents of PPU are

6

xx100100.

PPD/PPU Bits

87654321

- - PPU

PPU5PPU4PPU3PPU2PPU

6

- - PPD6PPD5PPD4PPD3PPD2PPD

Capacity Inaccurate Count Register (CPI)

The read-only CPI register (address=09h) is used to in
dicate the number of times a battery has been charged
without an LMD update. Because the capacity of a re
chargeable battery varies with age and operating condi

­tions, the bq2012 adapts to the changing capacity over

time. A complete discharge from full (NAC=LMD) to
empty (EDV1=1) is required to perform an LMD update
assuming there have been no intervening valid charges,
the temperature is greater than or equal to 0°C, and the
self-discharge counter is less than 4096 counts.

The CPI register is incremented every time a valid
charge is detected if NAC < 0.94*LMD. When NAC

-

0.94*LMD, the CPI register increments on the first
valid charge; CPI does not increment again for a valid
charge until NAC is discharged below 0.94*LMD. This
prevents continuous trickle charging from incrementing
CPI if self-discharge decrements NAC. The CPI register
increments to 255 without rolling over. When the con
tents of CPI are incremented to 64, the capacity inaccu
rate flag, CI, is asserted in the FLGS1 register. The CPI
register is reset whenever an update of the LMD regis
ter is performed, and the CI flag is also cleared.

-

-

-

-

-

and

3

1

1

-

-

-

≥

-

-

-

14

bq2012

Digital Magnitude Filter (DMF)

The read-write DMF register (address = 0ah) provides
the system with a means to change the default settings
of the digital magnitude filter. By writing different val
ues into this register, the limits of V

SRD

and V

SRQ

can be

adjusted.

Note: Care should be taken when writing to this regis
ter. A V

SRD

and V

below the specified VOSmay ad

SRQ

versely affect the accuracy of the bq2012. Refer to Table
4 for recommended settings for the DMF register.

Reset Register (RST)

The reset register (address=39h) provides the means to
perform a software-controlled reset of the device. By
writing the RST register contents from 00h to 80h, a
bq2012 reset is performed. Setting any bit other than the

most-significant bit of the RST register is not allowed,
and results in improper operation of the bq2012.

Resetting the bq2012 sets the following:

LMD = PFC

■

CPI, VDQ, NACH, and NACL = 0

■

CI and BRP = 1

■

Note: NACH = PFC when PROG

6

=H.

Display

The bq2012 can directly display capacity information us­ing low-power LEDs. If LEDs are used, the program
pins should be resistively tied to V
gram high or program low, respectively.

The bq2012 displays the battery charge state in either
absolute or relative mode. In relative mode, the battery
charge is represented as a percentage of the LMD. Each
LED segment represents 20% of the LMD. The sixth
segment is not used.

or VSSfor a pro

CC

In absolute mode, each segment represents a fixed
amount of charge, based on the initial PFC. In absolute
mode, each segment represents 20% of the PFC, with
the sixth segment representing “overfull” (charge above

-

the PFC). As the battery wears out over time, it is pos
sible for the LMD to be below the initial PFC. In this
case, all of the LEDs may not turn on, representing the
reduction in the actual battery capacity.

-

-

The capacity display is also adjusted for the present bat
tery temperature. The temperature adjustment reflects
the available capacity at a given temperature but does
not affect the NAC register. The temperature adjust
ments are detailed in the TMPGG register description.

When DISP
tive. When DISP

is tied to VCC, the SEG

outputs are inac

1–6

is left floating, the display becomes ac
tive whenever the NAC registers are counting at a rate
equivalent to V

< -4mV or V

SRO

SRO>VSRQ

pulled low, the segment outputs become active immedi
ately. A capacitor tied to DISP

allows the display to re
main active for a short period of time after activation by
a push-button switch.

The segment outputs are modulated as two banks of
three, with segments 1, 3, and 5 alternating with seg­ments 2, 4, and 6. The segment outputs are modulated
at approximately 100Hz with each segment bank active
for 30% of the period.

SEG

blinks at a 4Hz rate whenever VSBhas been de-

1

tected to be below V
battery condition. V

(EDV1 = 1), indicating a low-

EDV1

below V

SB

(EDVF = 1) disables

EDVF

the display output.

Microregulator

-

The bq2012 can operate directly from three or four cells.
To facilitate the power supply requirements of the
bq2012, an REF output is provided to regulate an exter
nal low-threshold n-FET. A micropower source for the
bq2012 can be inexpensively built using the FET and an
external resistor; see Figure 1.

-

-

-

-

-

. When

-

-

-

15

bq2012

Absolute Maximum Ratings

Symbol Parameter Minimum Maximum Unit Notes

V

CC

All other pins Relative to V

REF Relative to V

V

SR

T

OPR

Relative to V

Relative to V

SS

SS

SS

SS

Operating tempera
ture

-0.3 7.0 V

-0.3 7.0 V

-0.3 8.5 V Current limited by R1 (see Figure 1)

Minimum 100Ωseries resistor should

-0.3 7.0 V

be used to protect SR in case of a
shorted battery (see the bq2012 appli
cation note for details).

-

0 70 °C Commercial

-

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional opera

tion should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Expo
sure to conditions beyond the operational limits for extended periods of time may affect device reliability.

DC Voltage Thresholds (T

= T

A

; V = 3.0 to 6.5V)

OPR

Symbol Parameter Minimum Typical Maximum Unit Notes

V

V

V

V

V

V

V

V

V

EDVF

EDV1

SR1

ORD

SRO

SRQ

SRD

MCV

BR

Final empty warning 0.93 0.95 0.97 V SB

First empty warning 1.03 1.05 1.07 V SB

Discharge compensation threshold -120 -150 -180 mV

SR, V
note 2)

+ VOS(see

SR

Overload threshold -230 -250 -280 mV SR, VSR+ V

SR sense range -300 - +2000 mV SR, VSR+ V

Valid charge 375 - -

Valid discharge - - -300

VVSR+VOS(see note 1)

µ

VVSR+VOS(see note 1)

µ

Maximum single-cell voltage 2.20 2.25 2.30 V SB

Battery removed/replaced

- 0.1 0.25 V SB pulled low

2.20 2.25 2.30 V SB pulled high

OS

OS

Notes: 1. Default value; value set in DMF register. VOSis affected by PC board layout. Proper layout

guidelines should be followed for optimal performance. See “LayoutConsiderations.”

2. Proper threshold measurements require V

to be more than 1.5V greater than the desired signal

CC

value.

-

-

16

bq2012

DC Electrical Characteristics (T

=T

OPR

)

A

Symbol Parameter Minimum Typical Maximum Unit Notes

excursion from < 2.0V to

V

V

CC

V

OS

V

REF

R

REF

I

CC

V

SB

R

SBmax

I

DISP

I

LCOM

R

DQ

V

SR

R

SR

V

IH

V

IL

V

IZ

V

OLSL

V

OLSH

V

OHLCL

V

OHLCH

I

IH

I

IL

I

OHLCOM

I

OLS

I

OL

V

OL

V

IHDQ

V

ILDQ

R

PROG

R

FLOAT

Supply voltage 3.0 4.25 6.5 V

Offset referred to V

SR

-

±50

±150

Reference at 25°C 5.7 6.0 6.3 V I

Reference at -40°C to +85°C 4.5 - 7.5 V I

Reference input impedance 2.0 5.0 - MΩV

- 90 135

Normal operation

- 120 180

- 170 250

Battery input - - 2.4 V

SB input impedance 10 - - MΩ0 < VSB<V

DISP input leakage - - 5

LCOM input leakage -0.2 - 0.2

Internal pulldown 500 - - K

Sense resistor input -0.3 - 2.0 V

SR input impedance 10 - - MΩ-200mV < VSR<V

Logic input high VCC- 0.2 - - V PROG1–PROG

Logic input low - - VSS+ 0.2 V PROG1–PROG

Logic input Z float - float V PROG1–PROG

SEGXoutput low, low V

CC

SEGXoutput low, high V

LCOM output high, low V

LCOM output high, high V

PROG

PROG

input high current - 1.2 -

1-6

input low current - 1.2 -

1-6

CC

CC

CC

- 0.1 - V

- 0.4 - V

VCC- 0.3 - - V VCC= 3V, I

VCC- 0.6 - - V VCC= 6.5V, I

LCOM source current -33 - - mA At V

SEGXsink current - - 11.0 mA At V

Open-drain sink current - - 5.0 mA

Open-drain output low - - 0.5 V I

DQ input high 2.5 - - V DQ

DQ input low - - 0.8 V DQ

Soft pull-up or pull-down resis
tor value (for programming)

-

- - 200

Float state external impedance - 5 - MΩPROG1–PROG

CC

3.0V initializes the unit.

=V

DISP

µV

= 5µA

REF

= 5µA

REF

= 3V

REF

AV

µ

AV

µ

AV

µ

AV

µ

A DISP =V

µ

= 3.0V

CC

= 4.25V

CC

= 6.5V

CC

DISP=VSS

Ω

V

SR<VSS

V

SR>VSS

= 3V, I

V

CC

SEG

–SEG

1

= 6.5V, I

V

CC

SEG

–SEG

1

AV

µ

PROG=VCC

AV

µ

PROG=VCC

OHLCH=VCC

OLSH

At V

OL=VSS

DQ, EMPTY, CHG

5mA, DQ, EMPTY

≤

OL

PROG

K

Ω

–PROG

1

CC

CC

CC

= discharge;

= charge

OLS

6

OLS

6

OHLCOM

OHLCOM

/2

/2

= 0.4V

+ 0.3V

Note: All voltages relative to VSS.

CC

6

6

6

1.75mA

≤

11.0mA

≤

- 0.6V

6

6

≥

= -5.25mA

= -33.0mA

17

bq2012

Serial Communication Timing Specification

Symbol Parameter Minimum Typical Maximum Unit Notes

t

CYCH

t

CYCB

t

STRH

t

STRB

t

DSU

t

DH

t

DV

t

SSU

t

SH

t

SV

t

B

t

BR

Note: The open-drain DQ pin should be pulled to at least VCCby the host system for proper DQ operation.

Cycle time, host to bq2012 3 - - ms See note

Cycle time, bq2012 to host 3 - 6 ms

Start hold, host to bq2012 5 - - ns

Start hold, bq2012 to host 500 - -

Data setup - - 750

Data hold 750 - -

s

µ

s

µ

s

µ

Data valid 1.50 - - ms

Stop setup - - 2.25 ms

Stop hold 700 - -

s

µ

Stop valid 2.95 - - ms

Break 3 - - ms

Break recovery 1 - - ms

DQ may be left floating if the serial interface is not used.

Serial Communication Timing Illustration

DQ

(R/W "1")

t

DQ

(R/W "0")

DQ

(BREAK)

STRH

t

STRB

t

DSU

t

DV

t

t

DH

t

SSU

t

SV

CYCH, tCYCB, tB

18

t

SH

t

BR

TD201002.eps

16-Pin SOIC Narrow (SN)

bq2012

16-Pin SN(0.150" SOIC

Inches Millimeters

D

e

B

E

H

A

C

A1

Dimension

A 0.060 0.070 1.52 1.78

A1 0.004 0.010 0.10 0.25

B 0.013 0.020 0.33 0.51

C 0.007 0.010 0.18 0.25

D 0.385 0.400 9.78 10.16

E 0.150 0.160 3.81 4.06

e 0.045 0.055 1.14 1.40

H 0.225 0.245 5.72 6.22

L 0.015 0.035 0.38 0.89

Min. Max. Min. Max.

)

.004

L

Data Sheet Revision History

Change No. Page No. Description Nature of Change

1 7 Addition to Table 2 Added bottom row

Note: Change 1 = Sept. 1996 B changes from July 1994.

Ordering Information

bq2012

Temperature Range:

blank = Commercial (0 to +70°C)

Package Option:

SN = 16-pin narrow SOIC

Device:

bq2012 Gas Gauge IC

19

PACKAGE OPTION ADDENDUM

www.ti.com

6-Dec-2006

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

BQ2012SN-D107 ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br)

BQ2012SN-D107G4 ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br)

BQ2012SN-D107TR ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br)

BQ2012SND107TRG4 ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-2-260C-1 YEAR

CU NIPDAU Level-2-260C-1 YEAR

CU NIPDAU Level-2-260C-1 YEAR

CU NIPDAU Level-2-260C-1 YEAR

(3)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 1