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AM571x Sitara™ Processors

Silicon Revision 2.0 and 2.1

1 Device Overview

1.1 Features

• Arm®Cortex®-A15 microprocessor subsystem

• C66x floating-point VLIW DSP cores – Fully object-code compatible with C67x and

C64x+

– Up to thirty-two 16 × 16-bit fixed-point multiplies

per cycle

• Up to 512KB of on-chip L3 RAM

• Level 3 (L3) and level 4 (L4) interconnects

• DDR3/DDR3L External Memory Interface (EMIF) module

– Supports up to DDR3-1333 (667 MHz) – Up to 2GB across single chip select

• 2x Dual Arm®Cortex®-M4 coprocessors (IPU1 and IPU2)

• IVA-HD subsystem – 4K @ 15fps encode and decode support for

H.264 CODEC

– Other CODECs are up to 1080p60

• Display subsystem – Full-HD video (1920 × 1080p, 60 fps) – Multiple video inputs and video outputs – 2D and 3D graphics – Display controller with DMA engine and up to

three pipelines

– HDMI™ encoder: HDMI 1.4a and DVI 1.0

compliant

• 2x dual-core Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS)

• Accelerator (BB2D) subsystem – Vivante®GC320 core

• Video Processing Engine (VPE)

• Available single-core PowerVR®SGX544 3D GPU

• Secure boot support – Hardware-enforced root-of-trust – Customer programmable keys (SR 2.1) – Support for takeover protection, IP protection,

and anti-roll back protection

• Cryptographic acceleration support – Supports cryptographic cores

– AES – 128/192/256-bits key sizes – 3DES – 56/112/168-bits key sizes – MD5, SHA1 – SHA2 – 224/256/384/512 – True random number generator

AM5718, AM5716

SPRS957I –MARCH 2016–REVISED NOVEMBER 2019

– DMA support

• Debug security – Secure software controlled debug access – Security aware debugging

• Trusted Execution Environment (TEE) support – Arm®TrustZone®based TEE – Extensive firewall support for isolation – Secure DMA path and interconnect – Secure Watchdog/Timer/IPC

• One Video Input Port (VIP) module – Support for up to four multiplexed input ports

• General-Purpose Memory Controller (GPMC)

• Enhanced Direct Memory Access (EDMA) controller

• 2-Port Gigabit Ethernet switch

• Sixteen 32-bit general-purpose timers

• 32-bit MPU watchdog timer

• Five high speed Inter-Integrated Circuit ( I2C™) ports

• HDQ/ 1-Wire®interface

• Ten configurable UART/IrDA/CIR modules

• Four Multichannel Serial Peripheral Interfaces (McSPI)

• Quad Serial Peripheral Interface (QSPI)

• SATA Gen2 interface

• Eight Multichannel Audio Serial Port (McASP) modules

• SuperSpeed USB 3.0 dual-role device

• High Speed USB 2.0 dual-role device

• Four MultiMedia Card/ Secure Digital®/Secure Digital Input Output interfaces ( MMC™/ SD®/SDIO)

• PCI-Express®( PCIe®) revision 3.0 subsystems with two 5-Gbps lanes

– One 2-lane Gen2-compliant port – or Two 1-lane Gen2-compliant ports

• Dual Controller Area Network (DCAN) modules – CAN 2.0B protocol

• MIPI®Camera Serial Interface 2 (CSI-2)

• Up to 215 General-Purpose I/O (GPIO) pins

• Power, reset, and clock management

• On-chip debug with CTools technology

• 28-nm CMOS technology

• 23 mm × 23 mm, 0.8-mm pitch, 760-pin BGA

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

AM5718, AM5716

SPRS957I –MARCH 2016–REVISED NOVEMBER 2019

1.2 Applications

• Industrial communication

• Human Machine Interface (HMI)

• Automation and control

1.3 Description

AM571x Sitara™ processors are Arm®applications processors built to meet the intense processing needs of modern embedded products.

AM571x devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.

Programmability is provided by a single-core Arm®Cortex®-A15 RISC CPU with Arm®Neon™ extensions and a TI C66x VLIW floating-point DSP core. The Arm®processor lets developers keep control functions separate from vision algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm®and C66x DSP, including C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a debugging interface for visibility into source code execution.

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• High performance applications

• Other general use

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment is available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The AM571x Sitara Arm processor family is qualified according to the AEC-Q100 Standard.

Device Information

PART NUMBER PACKAGE BODY SIZE

AM5718ABC FCBGA (760) 23.0 mm × 23.0 mm AM5716ABC FCBGA (760) 23.0 mm × 23.0 mm

(1) For more information, see Section 10, Mechanical, Packaging, and Orderable Information.

(1)

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(1x C66x

Coprocessor)

Mailbox x13

EDMA

High Speed Interconnect

Program/Data Storage

Connectivity

Display Subsystem

System

(1x Arm

Cortex–A15)

IVA HD

1080p Video

Coprocessor

DSP

PCIe SS x2

(NAND/NOR/

Async)

(1x SGX544 3D)

VIP

(Dual Cortex–M4)

intro-001

GPMC / ELM

AM571x

GPU

MPU

IPU1

Serial Interfaces

I2C x5

UART x10

McSPI x4

DCAN x2

Spinlock

GPIO x8

Timers x16

WDT

QSPI

LCD1

EMIF 32-bit

DDR3(L)

SDMA

VPE

McASP x8

MMU x2

CAL

CSI2 x2

BB2D

(GC320 2D)

(Dual Cortex–M4)

IPU2

LCD2

LCD3

HDMI 1.4a

1x GFX Pipeline

3x Video Pipeline

Blend / Scale

PWM SS x3

RTC SS

HDQ

KBD

GMAC_SW

USB 3.0

Dual Role FS/HS/SS

w/ PHYs

USB 2.0

Dual Role FS/HS

w/ PHY

512-KB

OCMC_RAM

w/ ECC

SATA

DMM

MMC / SD x4

PRU-ICCS x2

Secure Boot Debug

SecurityTEE (HS devices)

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1.4 Functional Block Diagram

Figure 1-1 is functional block diagram for the device.

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SPRS957I –MARCH 2016–REVISED NOVEMBER 2019

Figure 1-1. AM571x Block Diagram

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1 Device Overview ......................................... 1

1.1 Features .............................................. 1

1.2 Applications........................................... 2

1.3 Description............................................ 2

1.4 Functional Block Diagram ........................... 3

2 Revision History ......................................... 5

3 Device Comparison ..................................... 6

3.1 Related Products ..................................... 8

4 Terminal Configuration and Functions.............. 9

4.1 Terminal Assignment ................................. 9

4.2 Ball Characteristics.................................. 10

4.3 Multiplexing Characteristics ......................... 81

4.4 Signal Descriptions.................................. 98

5 Specifications ......................................... 141

5.1 Absolute Maximum Ratings........................ 141

5.2 ESD Ratings ....................................... 142

5.3 Power-On-Hour (POH) Limits...................... 143

5.4 Recommended Operating Conditions ............. 143

5.5 Operating Performance Points..................... 147

5.6 Power Consumption Summary .................... 165

5.7 Electrical Characteristics........................... 165

5.8 VPP Specifications for One-Time Programmable

(OTP) eFuses...................................... 175

5.9 Thermal Characteristics............................ 177

5.10 Power Supply Sequences ......................... 178

6 Clock Specifications ................................. 183

6.1 Input Clock Specifications ......................... 184

6.2 DPLLs, DLLs Specifications ....................... 193

7 Timing Requirements and Switching

Characteristics ........................................ 197

7.1 Timing Test Conditions ............................ 197

7.2 Interface Clock Specifications ..................... 197

7.3 Timing Parameters and Information ............... 197

7.4 Recommended Clock and Control Signal Transition

Behavior............................................ 199

7.5 Virtual and Manual I/O Timing Modes ............. 199

7.6 Video Input Ports (VIP) ............................ 202

7.7 Display Subsystem - Video Output Ports.......... 220

7.8 Display Subsystem - High-Definition Multimedia

Interface (HDMI) ................................... 231

7.9 Camera Serial Interface 2 CAL bridge (CSI2) ..... 232

7.10 External Memory Interface (EMIF)................. 232

7.11 General-Purpose Memory Controller (GPMC)..... 232

7.12 Timers.............................................. 256

7.13 Inter-Integrated Circuit Interface (I2C)............. 256

7.14 HDQ / 1-Wire Interface (HDQ1W) ................. 259

7.15 Universal Asynchronous Receiver Transmitter

(UART)............................................. 261

7.16 Multichannel Serial Peripheral Interface (McSPI) . 263

7.17 Quad Serial Peripheral Interface (QSPI) .......... 269

7.18 Multichannel Audio Serial Port (McASP) .......... 273

7.19 Universal Serial Bus (USB) ........................ 293

7.20 Serial Advanced Technology Attachment (SATA). 293

7.21 Peripheral Component Interconnect Express

(PCIe) .............................................. 293

7.22 Controller Area Network Interface (DCAN) ........ 294

7.23 Ethernet Interface (GMAC_SW) ................... 295

7.24 eMMC/SD/SDIO ................................... 308

7.25 General-Purpose Interface (GPIO) ................ 331

7.26 PRU-ICSS Interfaces .............................. 332

7.27 System and Miscellaneous interfaces ............. 359

7.28 Test Interfaces ..................................... 359

8 Applications, Implementation, and Layout ...... 363

8.1 Power Supply Mapping ............................ 363

8.2 DDR3 Board Design and Layout Guidelines....... 364

8.3 High Speed Differential Signal Routing Guidance. 388

8.4 Power Distribution Network Implementation

Guidance........................................... 388

8.5 Thermal Solution Guidance........................ 388

8.6 Single-Ended Interfaces ........................... 388

8.7 LJCB_REFN/P Connections....................... 390

8.8 Clock Routing Guidelines .......................... 391

9 Device and Documentation Support.............. 393

9.1 Device Nomenclature .............................. 393

9.2 Tools and Software ................................ 395

9.3 Documentation Support............................ 396

9.4 Related Links ...................................... 396

9.5 Support Resources ................................ 396

9.6 Trademarks ........................................ 396

9.7 Electrostatic Discharge Caution ................... 397

9.8 Glossary............................................ 397

10 Mechanical, Packaging, and Orderable

Information ............................................ 398

10.1 Packaging Information ............................. 398

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2 Revision History

Changes from June 1, 2018 to April 5, 2019 (from G Revision (May 2018) to H Revision) Page

• Added Device Security Features for Silicon revision 2.1 in Section 1.1, Features........................................... 1

• Added vpp details for Silicon revision 2.1 in Table 4-1, Unused Balls Specific Connection Requirements,

Table 4-2, Ball Characteristics and Table 4-35, Power Supply Signal Descriptions ....................................... 10

• Updated OPP_HIGH power supply value in note (6) under Table 5-8, Voltage Domains Operating Performance

Points................................................................................................................................ 148

• Updated SYS_32K to FUNC_32K_CLK in Table 5-10, Maximum Supported Frequency and Section 5.10, Power

Supply Sequences ................................................................................................................ 149

• Added Section 5.8, VPP Specifications for One-Time Programmable (OTP) eFuses for Silicon revision 2.1 ........ 175

• Updated porz and rstoutn descriptions under Figure 5-2, Power-Up Sequencing........................................ 179

• Updated system clock names in Section 6, Clock Specifications ........................................................... 183

• Added PRU-ICSS sync and latch signals to IOSETs in Table 7-154, PRU-ICSS1 IOSETs and Table 7-155,

PRU-ICSS2 IOSETs............................................................................................................... 341

• Added Silicon revison 2.1 in support in Figure 9-1, Printed Device Reference and Table 9-1, Nomenclature

Description.......................................................................................................................... 393

• Updated note for cosmetic marks on package................................................................................. 393

Changes from April 6, 2019 to November 15, 2019 (from H Revision (April 2019) to I Revision) Page

• Added reminders to disable unused pulls and RX pads in Section 4.2, Ball Characteristics ............................. 11

• Removed uart2_rxd for Muxmode 0 .............................................................................................. 13

• Added clarification notes for EMU[1:0] connections in Table 4-24, GPIOs Signal Descriptions and Table 4-28,

Debug Signal Descriptions ....................................................................................................... 120

• Updated clock names in Table 5-10, Maximum Supported Frequency .................................................... 149

• Updated EMIF_DLL_FCLK max rate in Table 6-15, DLL Characteristics.................................................. 196

• Updated GPMC timing table footnotes.......................................................................................... 233

• Updated information about WD_TIMER1 in Section 7.12, Timers .......................................................... 256

• Updated parameter number in Table 7-46, Timing Requirements for QSPI............................................... 271

• Added MII_TXER timing to Section 7.23.1, GMAC MII Timings............................................................. 297

• Updated MDIO Timing Diagram and MDIO7 parameter values............................................................. 298

• Updated timing specification values for MMC.................................................................................. 312

• Updated Delay time for MMC2 in Table 7-110, Switching Characteristics for MMC2 - JC64 High Speed DDR

Mode................................................................................................................................. 320

• Added note regarding DDR ECC solutions to Table 8-4, Supported DDR3 Device Combinations..................... 365

• Added clarifications about validated DDR topology ........................................................................... 374

• Updated reference name to errata document in Section 9.3, Documentation Support .................................. 396

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3 Device Comparison

Table 3-1 shows a comparison between AM571x devices, highlighting the differences. For a comparison

of the full AM57xx family of devices, refer to Parametric Table.

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Table 3-1. Device Comparison

FEATURES

AM5718 AM5716

DEVICE

Features

CTRL_WKUP_STD_FUSE_DIE_ID_2[31:24] Base PN register bit field value

(3)

AM5718: 55 (0x37) AM5716: 53 (0x35)

AM5718-E: 56 (0x38) AM5716-E: 54 (0x36)

Processors/ Accelerators

Speed Grades X X, D Arm Single Cortex-A15 Microprocessor Subsystem

MPU core 0 Yes

(MPU) C66x VLIW DSP DSP1 Yes BitBLT 2D Hardware Acceleration Engine (BB2D) BB2D Yes Not Supported Display Subsystem VOUT1 Yes Not Supported

VOUT2 Yes Not Supported VOUT3 Yes Not Supported HDMI Yes Not Supported

Dual Arm Cortex-M4 Image Processing Unit (IPU) IPU1 Yes

IPU2 Yes Image Video Accelarator (IVA) IVA Yes Not Supported SGX544 Single-Core 3D Graphics Processing Unit

GPU Yes Not Supported (GPU)

Video Input Port 1 (VIP1) vin1a Yes

vin1b Yes

vin2a Yes

vin2b Yes Video Processing Engine (VPE) VPE Yes

Program/Data Storage

On-Chip Shared Memory (RAM) OCMC_RAM1 512KB General-Purpose Memory Controller (GPMC) GPMC Yes DDR3 Memory Controller EMIF1 up to 2GB across single chip select Dynamic Memory Manager (DMM) DMM Yes

Radio Support

Audio Tracking Logic (ATL) ATL Not Supported Viterbi Coprocessor (VCP) VCP1 Not Supported

VCP2 Not Supported

(1) (1) (1)

Peripherals

Dual Controller Area Network (DCAN) Interface DCAN1 Yes

DCAN2 Yes Enhanced DMA (EDMA) EDMA Yes System DMA (DMA_SYSTEM) DMA_SYSTEM Yes Ethernet Subsystem (Ethernet SS) GMAC_SW[0] MII, RMII, or RGMII

GMAC_SW[1] MII, RMII, or RGMII General Purpose I/O (GPIO) GPIO up to 215 Inter-Integrated Circuit (I2C) Interface I2C 5 System Mailbox Module MAILBOX 13 13

(1) (1) (1) (1) (1)

(1) (1)

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Table 3-1. Device Comparison (continued)

FEATURES

AM5718 AM5716

Media Local Bus Subsystem MLB Not Supported Camera Adaptation Layer (CAL) Camera Serial

Interface 2 (CSI2)

CSI2_0 Yes

CSI2_1 Yes Multichannel Audio Serial Port (McASP) McASP1 16 serializers

McASP2 16 serializers

McASP3 4 serializers

McASP4 4 serializers

McASP5 4 serializers

McASP6 4 serializers

McASP7 4 serializers

McASP8 4 serializers MultiMedia Card/Secure Digital/Secure Digital Input

Output Interface (MMC/SD/SDIO)

MMC1 1x UHSI 4b

MMC2 1x eMMC™ 8b

MMC3 1x SDIO 8b

MMC4 1x SDIO 4b PCI-Express 3.0 Port with Integrated PHY PCIe_SS1 up to two lanes (second lane shared with

PCIe_SS2 Single lane (shared with PCIe_SS1 and USB1) 2x Programmable Real-Time Unit Subsystem and

Industrial Communication Subsystem (PRU-ICSS)

PRU-ICSS1 Yes

PRU-ICSS2 Yes Serial Advanced Technology Attachment (SATA) SATA Yes Real-Time Clock Subsystem (RTCSS)

(2)

RTCSS Yes Multichannel Serial Peripheral Interface (McSPI) McSPI 4 HDQ1W HDQ1W Yes Quad SPI (QSPI) QSPI Yes Spinlock Module SPINLOCK Yes Keyboard Controller (KBD) KBD Yes Timers, General-Purpose TIMERS GP 16 Timer, Watchdog WD TIMER Yes Pulse-Width Modulation Subsystem (PWMSS) PWMSS1 Yes

PWMSS2 Yes

PWMSS3 Yes Universal Asynchronous Receiver/Transmitter

UART 10 (UART)

Universal Serial Bus (USB3.0) USB1 (SuperSpeed, Dual-Role-

Device [DRD] Universal Serial Bus (USB2.0) USB2 (High Speed, Dual-Role-

Device [DRD], with embedded HS

PHY)

USB3 (High Speed, OTG2.0, with

ULPI)

USB4 (High Speed, OTG2.0, with

ULPI) (1) Features noted as “not supported,” must not be used. Their functionality is not supported by TI for this family of devices. These features

are subject to removal without notice on future device revisions. Any information regarding the unsupported features has been retained

in the documentation solely for the purpose of clarifying signal names or for consistency with previous feature descriptions. (2) RTC-only mode is not a supported feature. (3) For more details about the CTRL_WKUP_STD_FUSE_DIE_ID_2 register and Base PN bit field, see the AM571x Technical Reference

Manual.

DEVICE

(1)

PCIe_SS2 and USB1)

Yes

Not Supported

(1)

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3.1 Related Products

Sitara™ processors Broad family of scalable processors based on Arm® Cortex®-A cores and TI C66x

DSP cores with flexible accelerators, peripherals, connectivity and unified software support – perfect for sensors to servers. Sitara processors have the reliability needed for use in industrial applications.

AM57x Sitara™ processors AM57x Sitara™ processors are highly integrated devices that enable high-

performance and multimedia applications. In addition to the Arm® Cortex®-A15 cores and TI C66x DSP cores, on-board accelerators provide enhanced vision and machine learning capabilities, support for multiple industrial Ethernet protocols, and video processing.

Sitara™ processors applications Sitara™ processors provide scalable solutions for a wide range of

applications from HMIs and gateways to more complex equipment such as drives and substation automation equipment. Sitara processors also offer multi-protocol support for industrial communication protocols such as EtherCAT®, Ethernet/IP, and Profinet.

Reference Designs and Evaluation Modules TI provides many reference designs containing ‘building

block’ solutions to enable customers to rapidly develop their own unique products and solutions. EVMs are also provided to help kick-start product development.

Companion Products for AM571x Review products that are frequently purchased or used in conjunction

with this product to complete your design.

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4 Terminal Configuration and Functions

4.1 Terminal Assignment

Figure 4-1 shows the ball locations for the 760 plastic ball grid array (PBGA) package and is used in

conjunction with Table 4-2 through Table 4-35 to locate signal names and ball grid numbers.

AM5718, AM5716

SPRS957I –MARCH 2016–REVISED NOVEMBER 2019

Figure 4-1. ABC S-PBGA-N760 Package (Bottom View)

The following bottom balls are not pinned out: AF7 / AF10 / AF13 / AF16 / AF19 / AE4 / AE25 / AB26 / W3 / W26 / T3 / T26 / N3 / N26 / K3 / K26 / G3 / D4 / D25 / C10 / C13 / C16 / C19 / C22.

These balls do not exist on the package.

The following bottom balls are not connected: AH11 / AH12 / AG2 / AG8 / AG11 / AG12 / AF4 / AF6 / AF8 / AF9 / AE3 / AE5 / AE6 / AE8 / AE9 / AD3 / AD8 / AD9 / Y15 / Y16 / V18 / V19 / U18 / U19 / U22 / U23 / U24 / U25 / U26 / U27 / U28 / T22 / T23 / T27 / T28 / R20 / R22 / R23 / R24 / R25 / R26 / R27 / R28 / P19 / P22 / P23 / P24 / P25 / P26 / P27 / N20 / N22 / N23 / N27 / N28 / M20 / M21 / M22 / M23 / M24 / M25 / M26 / M27 / M28 / L20 / L21 / L22 / L23 / L24 / L25 / L26 / L27 / L28 / K20 / K21 / K22 / K23 / K27 / K28 / J20 / J21 / J22 / J23 / J24 / J25 / J26 / J27 / H20 / H21 / H22 / H23 / H24 / H25 / H26 / H27 / H28 / G22 / G23 / G24 / G25 / G26 / G27 / G28 / F24 / F25 / F26 / F27 / F28 / E24 / E26 / E27 / E28.

These balls can be connected as desired, including to vss.

4.1.1 Unused Balls Connection Requirements

This section describes the Unused/Reserved balls connection requirements.

NOTE

The following balls are reserved: A27 / Y5 / Y10 / B28 These balls must be left unconnected.

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All unused power supply balls must be supplied with the voltages specified in the

Section 5.4, Recommended Operating Conditions, unless alternative tie-off options are

included in Section 4.4, Signal Descriptions.

Table 4-1. Unused Balls Specific Connection Requirements

BALLS CONNECTION REQUIREMENTS

AE15 / AC15 / AE14 / D20 / AD17 / AC16 / V27 / AH25 / AE27 /

AD27 / Y28

E20 / D21 / E23 / C20 / C21 / V28 / F18 / AG25 / AE28 / AD28 / Y27

/ F17 / C25

K14 (vpp) This ball must be left unconnected if unused

AF14 (rtc_iso)

AB17 (rtc_porz)

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NOTE

These balls must be connected to GND through an external pull

resistor if unused

These balls must be connected to the corresponding power supply

through an external pull resistor if unused

This ball should be connected to the corresponding power supply

through an external pull resistor if unused; or can be connected to

F22 (porz) when RTC unused (level translation may be needed)

This ball should be connected to VSS when RTC is unused; or can

be connected to F22 (porz) when RTC unused (level translation may

be needed)

All other unused signal balls with a Pad Configuration Register can be left unconnected with their internal pullup or pulldown resistor enabled.

All other unused signal balls without a Pad Configuration Register can be left unconnected.

4.2 Ball Characteristics

Table 4-2 describes the terminal characteristics and the signals multiplexed on each ball. The following list

describes the table column headers:

1. BALL NUMBER: Ball number(s) on the bottom side associated with each signal on the bottom.

2. BALL NAME: Mechanical name from package device (name is taken from muxmode 0).

3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 0).

Table 4-2 does not take into account the subsystem multiplexing signals. Subsystem

multiplexing signals are described in Section 4.4, Signal Descriptions.

In the Driver off mode, the buffer is configured in high-impedance.

NOTE

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4. PN: This column shows if the functionality is applicable for AM5716 device. Note that the Ball

5. MUXMODE: Multiplexing mode number:

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NOTE

In some cases Table 4-2 may present more than one signal name per muxmode for the same ball. First signal in the list is the dominant function as selected via CTRL_CORE_PAD_* register.

All other signals are virtual functions that present alternate multiplexing options. This virtual functions are controlled via CTRL_CORE_ALT_SELECT_MUX or CTRL_CORE_VIP_MUX_SELECT register. For more information on how to use these options, see Pad Configuration Registers section, Control Module chapter in the device TRM.

Characteristics table presents a functionality of AM5718. If the cell is empty it means that the signal is available in all devices.

- Yes - Functionality is presented in AM5716

- No - Functionality is not presented in AM5716 An empty box means Yes.

a. MUXMODE 0 is the primary mode; this means that when MUXMODE=0 is set, the function

mapped on the pin corresponds to the name of the pin. The primary muxmode is not necessarily the default muxmode.

NOTE

The default mode is the mode at the release of the reset; also see the RESET REL. MUXMODE column.

b. MUXMODE 1 through 15 are possible muxmodes for alternate functions. On each pin, some

muxmodes are effectively used for alternate functions, while some muxmodes are not used. Only MUXMODE values which correspond to defined functions should be used.

c. An empty box means Not Applicable.

6. TYPE: Signal type and direction: – I = Input

– O = Output – IO = Input or Output – D = Open drain – DS = Differential Signaling – A = Analog – PWR = Power – GND = Ground – CAP = LDO Capacitor

NOTE

The RX buffer within the pad logic should be disabled on all pins that are not being used as an input. For more information, see the Control Module / Control Module Functional Description / PAD Functional Multiplexing and Configuration section in the device TRM.

7. BALL RESET STATE: The state of the terminal at power-on reset: – drive 0 (OFF): The buffer drives VOL(pulldown or pullup resistor not activated).

– drive 1 (OFF): The buffer drives VOH(pulldown or pullup resistor not activated). – OFF: High-impedance – PD: High-impedance with an active pulldown resistor – PU: High-impedance with an active pullup resistor – An empty box means Not Applicable

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Designs that contain pullup or pulldown resistors, either on the board or in attached devices that oppose internal pullup or pulldown resistors, that are active while the device is held in reset, must not remain in reset for long periods of time.

8. BALL RESET REL. STATE: The state of the terminal at the deactivation of the rstoutn signal (also mapped to the PRCM SYS_WARM_OUT_RST signal).

– drive 0 (OFF): The buffer drives VOL(pulldown or pullup resistor not activated). – drive clk (OFF): The buffer drives a toggling clock (pulldown or pullup resistor not activated). – drive 1 (OFF): The buffer drives VOH(pulldown or pullup resistor not activated). – OFF: High-impedance – PD: High-impedance with an active pulldown resistor – PU: High-impedance with an active pullup resistor – An empty box means Not Applicable

For more information on the CORE_PWRON_RET_RST reset signal and its reset sources, see Power, Reset, and Clock Management chapter in the device TRM.

9. BALL RESET REL. MUXMODE: This muxmode is automatically configured at the release of the rstoutn signal (also mapped to the PRCM SYS_WARM_OUT_RST signal). An empty box means Not Applicable.

10. IO VOLTAGE VALUE: This column describes the IO voltage value (VDDS supply). An empty box means Not Applicable.

11. POWER: The voltage supply that powers the terminal IO buffers. An empty box means Not Applicable.

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NOTE

VOUT1, VOUT2 and VOUT3 are only supported at 1.8V and not at 3.3V. This must be considered in the pin mux programming and VDDSHVx supply connections.

12. HYS: Indicates if the input buffer is with hysteresis: – Yes: With hysteresis

– No: Without hysteresis – An empty box: Not Applicable

NOTE

For more information, see the hysteresis values in Section 5.7, Electrical Characteristics.

13. BUFFER TYPE: Drive strength of the associated output buffer. An empty box means Not Applicable.

NOTE

For programmable buffer strength: – The default value is given in Table 4-2. – A note describes all possible values according to the selected muxmode.

14. PULLUP / PULLDOWN TYPE: Denotes the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled via software.

– PU: Internal pullup – PD: Internal pulldown – PU/PD: Internal pullup and pulldown

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15. DSIS: The deselected input state (DSIS) indicates the state driven on the peripheral input (logic "0" or

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SPRS957I –MARCH 2016–REVISED NOVEMBER 2019

– PUx/PDy: Programmable internal pullup and pulldown – PDy: Programmable internal pulldown – An empty box means No pull

NOTE

Internal pullup or pulldown resistors must be disabled when opposed by an external pullup or pulldown resistor on the board or within an attached device.

logic "1") when the peripheral pin function is not selected by any of the PINCNTLx registers. – 0: Logic 0 driven on the peripheral's input signal port.

– 1: Logic 1 driven on the peripheral's input signal port. – blank: Pin state driven on the peripheral's input signal port.

NOTE

Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the proper software configuration (Hi-Z mode is not an input signal).

NOTE

When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that pad’s behavior is undefined. This should be avoided.

NOTE

Some of the EMIF1 signals have an additional state change at the release of porz. The state that the signals change to at the release of porz is as follows:

drive 0 (OFF) for: ddr1_csn0, ddr1_ck, ddr1_nck, ddr1_casn, ddr1_rasn, ddr1_wen, ddr1_ba[2:0], ddr1_a[15:0].

OFF for: ddr1_ecc_d[7:0], ddr1_dqm[3:0], ddr1_dqm_ecc, ddr1_dqs[3:0], ddr1_dqsn[3:0], ddr1_dqs_ecc, ddr1_dqsn_ecc, ddr1_d[31:0].

NOTE

Dual rank support is not available on this device, but signal names are retained for consistency with the AM57xx family of devices.

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BALL

RESET

(1)

BALL

RESET REL.

STATE [8]

BALL

RESET REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER [11] HYS [12]

BUFFER

TYPE [13]

CSI2

Table 4-2. Ball Characteristics

BALL NUMBER

[1]

K9 cap_vbbldo_dsp cap_vbbldo_dsp CAP Y14 cap_vbbldo_gpu cap_vbbldo_gpu CAP J10 cap_vbbldo_iva cap_vbbldo_iva CAP J16 cap_vbbldo_mpu cap_vbbldo_mpu CAP T20 cap_vddram_core1 cap_vddram_core1 CAP L9 cap_vddram_core3 cap_vddram_core3 CAP J19 cap_vddram_core4 cap_vddram_core4 CAP J9 cap_vddram_dsp cap_vddram_dsp CAP Y13 cap_vddram_gpu cap_vddram_gpu CAP K16 cap_vddram_iva cap_vddram_iva CAP K19 cap_vddram_mpu cap_vddram_mpu CAP AE1 csi2_0_dx0 csi2_0_dx0 0 I 1.8 vdda_csi Yes LVCMOS

AF1 csi2_0_dx1 csi2_0_dx1 0 I 1.8 vdda_csi Yes LVCMOS

AF2 csi2_0_dx2 csi2_0_dx2 0 I 1.8 vdda_csi Yes LVCMOS

AH4 csi2_0_dx3 csi2_0_dx3 0 I 1.8 vdda_csi Yes LVCMOS

AH3 csi2_0_dx4 csi2_0_dx4 0 I 1.8 vdda_csi Yes LVCMOS

AD2 csi2_0_dy0 csi2_0_dy0 0 I 1.8 vdda_csi Yes LVCMOS

AE2 csi2_0_dy1 csi2_0_dy1 0 I 1.8 vdda_csi Yes LVCMOS

AF3 csi2_0_dy2 csi2_0_dy2 0 I 1.8 vdda_csi Yes LVCMOS

AG4 csi2_0_dy3 csi2_0_dy3 0 I 1.8 vdda_csi Yes LVCMOS

AG3 csi2_0_dy4 csi2_0_dy4 0 I 1.8 vdda_csi Yes LVCMOS

AG5 csi2_1_dx0 csi2_1_dx0 0 I 1.8 vdda_csi Yes LVCMOS

AG6 csi2_1_dx1 csi2_1_dx1 0 I 1.8 vdda_csi Yes LVCMOS

AH7 csi2_1_dx2 csi2_1_dx2 0 I 1.8 vdda_csi Yes LVCMOS

AH5 csi2_1_dy0 csi2_1_dy0 0 I 1.8 vdda_csi Yes LVCMOS

AH6 csi2_1_dy1 csi2_1_dy1 0 I 1.8 vdda_csi Yes LVCMOS

AG7 csi2_1_dy2 csi2_1_dy2 0 I 1.8 vdda_csi Yes LVCMOS

BALL NAME [2] SIGNAL NAME [3] PN [4]

MUXMODE

[5]

TYPE [6]

STATE [7]

PULL UP/DOWN TYPE [14]

PU/PD

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Table 4-2. Ball Characteristics

BALL NUMBER

[1]

G19 dcan1_rx dcan1_rx 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage

G20 dcan1_tx dcan1_tx 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage

AD20 ddr1_a0 ddr1_a0 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

AC19 ddr1_a1 ddr1_a1 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

AC20 ddr1_a2 ddr1_a2 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

AB19 ddr1_a3 ddr1_a3 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

AF21 ddr1_a4 ddr1_a4 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

AH22 ddr1_a5 ddr1_a5 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

AG23 ddr1_a6 ddr1_a6 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

AE21 ddr1_a7 ddr1_a7 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

AF22 ddr1_a8 ddr1_a8 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

AE22 ddr1_a9 ddr1_a9 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

AD21 ddr1_a10 ddr1_a10 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

AD22 ddr1_a11 ddr1_a11 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

AC21 ddr1_a12 ddr1_a12 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

AF18 ddr1_a13 ddr1_a13 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

AE17 ddr1_a14 ddr1_a14 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

BALL NAME [2] SIGNAL NAME [3] PN [4]

uart8_txd 2 O mmc2_sdwp 3 I sata1_led 4 O hdmi1_cec No 6 IO gpio1_15 14 IO Driver off 15 I

uart8_rxd 2 I mmc2_sdcd 3 I hdmi1_hpd No 6 IO gpio1_14 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET REL.

STATE [8]

BALL

RESET REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER [11] HYS [12]

BUFFER

TYPE [13]

LVCMOS

DDR

PULL UP/DOWN TYPE [14]

PU/PD

PUx/PDy

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Table 4-2. Ball Characteristics

BALL NUMBER

[1]

AD18 ddr1_a15 ddr1_a15 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

AF17 ddr1_ba0 ddr1_ba0 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

AE18 ddr1_ba1 ddr1_ba1 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

AB18 ddr1_ba2 ddr1_ba2 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

AC18 ddr1_casn ddr1_casn 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

AG24 ddr1_ck ddr1_ck 0 O PD drive 0 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

AG22 ddr1_cke ddr1_cke 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

AH23 ddr1_csn0 ddr1_csn0 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

AB16 ddr1_csn1 ddr1_csn1 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

AF25 ddr1_d0 ddr1_d0 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

AF26 ddr1_d1 ddr1_d1 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

AG26 ddr1_d2 ddr1_d2 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

AH26 ddr1_d3 ddr1_d3 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

AF24 ddr1_d4 ddr1_d4 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

AE24 ddr1_d5 ddr1_d5 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

AF23 ddr1_d6 ddr1_d6 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

AE23 ddr1_d7 ddr1_d7 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

AC23 ddr1_d8 ddr1_d8 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

AF27 ddr1_d9 ddr1_d9 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

AG27 ddr1_d10 ddr1_d10 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

AF28 ddr1_d11 ddr1_d11 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

AE26 ddr1_d12 ddr1_d12 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

AC25 ddr1_d13 ddr1_d13 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

BALL NAME [2] SIGNAL NAME [3] PN [4]

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET REL.

STATE [8]

BALL

RESET REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER [11] HYS [12]

BUFFER

TYPE [13]

DDR

PULL UP/DOWN TYPE [14]

PUx/PDy

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Table 4-2. Ball Characteristics

BALL NUMBER

[1]

AC24 ddr1_d14 ddr1_d14 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

AD25 ddr1_d15 ddr1_d15 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

V20 ddr1_d16 ddr1_d16 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

W20 ddr1_d17 ddr1_d17 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

AB28 ddr1_d18 ddr1_d18 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

AC28 ddr1_d19 ddr1_d19 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

AC27 ddr1_d20 ddr1_d20 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

Y19 ddr1_d21 ddr1_d21 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

AB27 ddr1_d22 ddr1_d22 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

Y20 ddr1_d23 ddr1_d23 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

AA23 ddr1_d24 ddr1_d24 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

Y22 ddr1_d25 ddr1_d25 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

Y23 ddr1_d26 ddr1_d26 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

AA24 ddr1_d27 ddr1_d27 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

Y24 ddr1_d28 ddr1_d28 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

AA26 ddr1_d29 ddr1_d29 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

AA25 ddr1_d30 ddr1_d30 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

AA28 ddr1_d31 ddr1_d31 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

AD23 ddr1_dqm0 ddr1_dqm0 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

AB23 ddr1_dqm1 ddr1_dqm1 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

AC26 ddr1_dqm2 ddr1_dqm2 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

AA27 ddr1_dqm3 ddr1_dqm3 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

V26 ddr1_dqm_ecc ddr1_dqm_ecc 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

BALL NAME [2] SIGNAL NAME [3] PN [4]

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET REL.

STATE [8]

BALL

RESET REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER [11] HYS [12]

BUFFER

TYPE [13]

DDR

PULL UP/DOWN TYPE [14]

PUx/PDy

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Table 4-2. Ball Characteristics

BALL NUMBER

[1]

AH25 ddr1_dqs0 ddr1_dqs0 0 IO PD PD 1.35/1.5 vdds_ddr1 LVCMOS

AE27 ddr1_dqs1 ddr1_dqs1 0 IO PD PD 1.35/1.5 vdds_ddr1 LVCMOS

AD27 ddr1_dqs2 ddr1_dqs2 0 IO PD PD 1.35/1.5 vdds_ddr1 LVCMOS

Y28 ddr1_dqs3 ddr1_dqs3 0 IO PD PD 1.35/1.5 vdds_ddr1 LVCMOS

AG25 ddr1_dqsn0 ddr1_dqsn0 0 IO PU PU 1.35/1.5 vdds_ddr1 LVCMOS

AE28 ddr1_dqsn1 ddr1_dqsn1 0 IO PU PU 1.35/1.5 vdds_ddr1 LVCMOS

AD28 ddr1_dqsn2 ddr1_dqsn2 0 IO PU PU 1.35/1.5 vdds_ddr1 LVCMOS

Y27 ddr1_dqsn3 ddr1_dqsn3 0 IO PU PU 1.35/1.5 vdds_ddr1 LVCMOS

V28 ddr1_dqsn_ecc ddr1_dqsn_ecc 0 IO PU PU 1.35/1.5 vdds_ddr1 LVCMOS

V27 ddr1_dqs_ecc ddr1_dqs_ecc 0 IO PD PD 1.35/1.5 vdds_ddr1 LVCMOS

W22 ddr1_ecc_d0 ddr1_ecc_d0 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

V23 ddr1_ecc_d1 ddr1_ecc_d1 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

W19 ddr1_ecc_d2 ddr1_ecc_d2 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

W23 ddr1_ecc_d3 ddr1_ecc_d3 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

Y25 ddr1_ecc_d4 ddr1_ecc_d4 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

V24 ddr1_ecc_d5 ddr1_ecc_d5 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

V25 ddr1_ecc_d6 ddr1_ecc_d6 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

Y26 ddr1_ecc_d7 ddr1_ecc_d7 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS

AH24 ddr1_nck ddr1_nck 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

AE20 ddr1_odt0 ddr1_odt0 0 O PD drive 0 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

AC17 ddr1_odt1 ddr1_odt1 0 O PD drive 0 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

AF20 ddr1_rasn ddr1_rasn 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

AG21 ddr1_rst ddr1_rst 0 O PD drive 0 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

BALL NAME [2] SIGNAL NAME [3] PN [4]

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET REL.

STATE [8]

BALL

RESET REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER [11] HYS [12]

BUFFER

TYPE [13]

DDR

PULL UP/DOWN TYPE [14]

PUx/PDy

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Table 4-2. Ball Characteristics

BALL NUMBER

[1]

Y18 ddr1_vref0 ddr1_vref0 0 PWR OFF drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

AH21 ddr1_wen ddr1_wen 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS

G21 emu0 emu0 0 IO PU PU 0 1.8/3.3 vddshv3 Yes Dual Voltage

D24 emu1 emu1 0 IO PU PU 0 1.8/3.3 vddshv3 Yes Dual Voltage

AC5 gpio6_10 gpio6_10 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage

AB4 gpio6_11 gpio6_11 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage

BALL NAME [2] SIGNAL NAME [3] PN [4]

gpio8_30 14 IO

gpio8_31 14 IO

mdio_mclk 1 O i2c3_sda 2 IO vin2b_hsync1 4 I vin1a_clk0 9 I ehrpwm2A 10 O pr2_mii_mt1_clk 11 I pr2_pru0_gpi0 12 I pr2_pru0_gpo0 13 O gpio6_10 14 IO Driver off 15 I

mdio_d 1 IO i2c3_scl 2 IO vin2b_vsync1 4 I vin1a_de0 9 I ehrpwm2B 10 O pr2_mii1_txen 11 O pr2_pru0_gpi1 12 I pr2_pru0_gpo1 13 O gpio6_11 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET REL.

STATE [8]

BALL

RESET REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER [11] HYS [12]

BUFFER

TYPE [13]

DDR

LVCMOS

PULL UP/DOWN TYPE [14]

PUx/PDy

PU/PD

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Table 4-2. Ball Characteristics

BALL NUMBER

[1]

E21 gpio6_14 gpio6_14 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage

F20 gpio6_15 gpio6_15 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage

F21 gpio6_16 gpio6_16 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage

BALL NAME [2] SIGNAL NAME [3] PN [4]

mcasp1_axr8 1 IO dcan2_tx 2 IO uart10_rxd 3 I vout2_hsync No 6 O vin2a_hsync0

vin1a_hsync0 i2c3_sda 9 IO timer1 10 IO gpio6_14 14 IO Driver off 15 I

mcasp1_axr9 1 IO dcan2_rx 2 IO uart10_txd 3 O vout2_vsync No 6 O vin2a_vsync0

vin1a_vsync0 i2c3_scl 9 IO timer2 10 IO gpio6_15 14 IO Driver off 15 I

mcasp1_axr10 1 IO vout2_fld No 6 O vin2a_fld0

vin1a_fld0 clkout1 9 O timer3 10 IO gpio6_16 14 IO Driver off 15 I

MUXMODE

[5]

8 I

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET REL.

STATE [8]

BALL

RESET REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER [11] HYS [12]

BUFFER

TYPE [13]

LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

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Table 4-2. Ball Characteristics

BALL NUMBER

[1]

R6 gpmc_a0 gpmc_a0 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage

T9 gpmc_a1 gpmc_a1 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage

T6 gpmc_a2 gpmc_a2 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage

BALL NAME [2] SIGNAL NAME [3] PN [4]

vin1a_d16 2 I vout3_d16 No 3 O vin2a_d0

vin1a_d0 vin1b_d0 6 I i2c4_scl 7 IO uart5_rxd 8 I gpio7_3

gpmc_a26 gpmc_a16

Driver off 15 I

vin1a_d17 2 I vout3_d17 No 3 O vin2a_d1

vin1a_d1 vin1b_d1 6 I i2c4_sda 7 IO uart5_txd 8 O gpio7_4 14 IO Driver off 15 I

vin1a_d18 2 I vout3_d18 No 3 O vin2a_d2

vin1a_d2 vin1b_d2 6 I uart7_rxd 7 I uart5_ctsn 8 I gpio7_5 14 IO Driver off 15 I

MUXMODE

[5]

4 I

14 IO

4 I

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET REL.

STATE [8]

BALL

RESET REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER [11] HYS [12]

BUFFER

TYPE [13]

LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

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Table 4-2. Ball Characteristics

BALL NUMBER

[1]

T7 gpmc_a3 gpmc_a3 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage

P6 gpmc_a4 gpmc_a4 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage

R9 gpmc_a5 gpmc_a5 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage

BALL NAME [2] SIGNAL NAME [3] PN [4]

qspi1_cs2 1 O vin1a_d19 2 I vout3_d19 No 3 O vin2a_d3

vin1a_d3 vin1b_d3 6 I uart7_txd 7 O uart5_rtsn 8 O gpio7_6 14 IO Driver off 15 I

qspi1_cs3 1 O vin1a_d20 2 I vout3_d20 No 3 O vin2a_d4

vin1a_d4 vin1b_d4 6 I i2c5_scl 7 IO uart6_rxd 8 I gpio1_26 14 IO Driver off 15 I

vin1a_d21 2 I vout3_d21 No 3 O vin2a_d5

vin1a_d5 vin1b_d5 6 I i2c5_sda 7 IO uart6_txd 8 O gpio1_27 14 IO Driver off 15 I

MUXMODE

[5]

4 I

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET REL.

STATE [8]

BALL

RESET REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER [11] HYS [12]

BUFFER

TYPE [13]

LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

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SPRS957I –MARCH 2016–REVISED NOVEMBER 2019

Table 4-2. Ball Characteristics

BALL NUMBER

[1]

R5 gpmc_a6 gpmc_a6 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage

P5 gpmc_a7 gpmc_a7 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage

N7 gpmc_a8 gpmc_a8 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage

R4 gpmc_a9 gpmc_a9 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage

BALL NAME [2] SIGNAL NAME [3] PN [4]

vin1a_d22 2 I vout3_d22 No 3 O vin2a_d6

vin1a_d6 vin1b_d6 6 I uart8_rxd 7 I uart6_ctsn 8 I gpio1_28 14 IO Driver off 15 I

vin1a_d23 2 I vout3_d23 No 3 O vin2a_d7

vin1a_d7 vin1b_d7 6 I uart8_txd 7 O uart6_rtsn 8 O gpio1_29 14 IO Driver off 15 I

vin1a_hsync0 2 I vout3_hsync No 3 O vin1b_hsync1 6 I timer12 7 IO spi4_sclk 8 IO gpio1_30 14 IO Driver off 15 I

vin1a_vsync0 2 I vout3_vsync No 3 O vin1b_vsync1 6 I timer11 7 IO spi4_d1 8 IO gpio1_31 14 IO Driver off 15 I

MUXMODE

[5]

4 I

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET REL.

STATE [8]

BALL

RESET REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER [11] HYS [12]

BUFFER

TYPE [13]

LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

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Table 4-2. Ball Characteristics

BALL NUMBER

[1]

N9 gpmc_a10 gpmc_a10 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage

P9 gpmc_a11 gpmc_a11 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage

P4 gpmc_a12 gpmc_a12 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage

R3 gpmc_a13 gpmc_a13 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage

BALL NAME [2] SIGNAL NAME [3] PN [4]

vin1a_de0 2 I vout3_de No 3 O vin1b_clk1 6 I timer10 7 IO spi4_d0 8 IO gpio2_0 14 IO Driver off 15 I

vin1a_fld0 2 I vout3_fld No 3 O vin2a_fld0

vin1a_fld0 vin1b_de1 6 I timer9 7 IO spi4_cs0 8 IO gpio2_1 14 IO Driver off 15 I

vin2a_clk0 vin1a_clk0

gpmc_a0 5 O vin1b_fld1 6 I timer8 7 IO spi4_cs1 8 IO dma_evt1 9 I gpio2_2 14 IO Driver off 15 I

qspi1_rtclk 1 I vin2a_hsync0

vin1a_hsync0 timer7 7 IO spi4_cs2 8 IO dma_evt2 9 I gpio2_3 14 IO Driver off 15 I

MUXMODE

[5]

4 I

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET REL.

STATE [8]

BALL

RESET REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER [11] HYS [12]

BUFFER

TYPE [13]

LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

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SPRS957I –MARCH 2016–REVISED NOVEMBER 2019

Table 4-2. Ball Characteristics

BALL NUMBER

[1]

T2 gpmc_a14 gpmc_a14 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage

U2 gpmc_a15 gpmc_a15 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage

U1 gpmc_a16 gpmc_a16 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage

P3 gpmc_a17 gpmc_a17 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage

R2 gpmc_a18 gpmc_a18 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage

BALL NAME [2] SIGNAL NAME [3] PN [4]

qspi1_d3 1 IO vin2a_vsync0

vin1a_vsync0 timer6 7 IO spi4_cs3 8 IO gpio2_4 14 IO Driver off 15 I

qspi1_d2 1 IO vin2a_d8

vin1a_d8 timer5 7 IO gpio2_5 14 IO Driver off 15 I

qspi1_d0 1 IO vin2a_d9

vin1a_d9 gpio2_6 14 IO Driver off 15 I

qspi1_d1 1 IO vin2a_d10

vin1a_d10 gpio2_7 14 IO Driver off 15 I

qspi1_sclk 1 IO vin2a_d11

vin1a_d11 gpio2_8 14 IO Driver off 15 I

MUXMODE

[5]

4 I

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET REL.

STATE [8]

BALL

RESET REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER [11] HYS [12]

BUFFER

TYPE [13]

LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

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BALL NUMBER

[1]

(9)

Table 4-2. Ball Characteristics

BALL NAME [2] SIGNAL NAME [3] PN [4]

gpmc_a19 gpmc_a19 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage

mmc2_dat4 1 IO gpmc_a13 2 O vin2a_d12

vin1a_d12 vin2b_d0

vin1b_d0 gpio2_9 14 IO Driver off 15 I

gpmc_a20 gpmc_a20 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage

mmc2_dat5 1 IO gpmc_a14 2 O vin2a_d13

vin1a_d13 vin2b_d1

vin1b_d1 gpio2_10 14 IO Driver off 15 I

gpmc_a21 gpmc_a21 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage

mmc2_dat6 1 IO gpmc_a15 2 O vin2a_d14

vin1a_d14 vin2b_d2

vin1b_d2 gpio2_11 14 IO Driver off 15 I

gpmc_a22 gpmc_a22 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage

mmc2_dat7 1 IO gpmc_a16 2 O vin2a_d15

vin1a_d15 vin2b_d3

vin1b_d3 gpio2_12 14 IO Driver off 15 I

MUXMODE

[5]

4 I

6 I

4 I

6 I

4 I

6 I

4 I

6 I

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET REL.

STATE [8]

BALL

RESET REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER [11] HYS [12]

BUFFER

TYPE [13]

LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

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SPRS957I –MARCH 2016–REVISED NOVEMBER 2019

Table 4-2. Ball Characteristics

BALL NUMBER

[1]

J7 gpmc_a23 gpmc_a23 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage

(9)

BALL NAME [2] SIGNAL NAME [3] PN [4]

mmc2_clk 1 IO gpmc_a17 2 O vin2a_fld0

vin1a_fld0 vin2b_d4

vin1b_d4 gpio2_13 14 IO Driver off 15 I

gpmc_a24 gpmc_a24 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage

mmc2_dat0 1 IO gpmc_a18 2 O vin2b_d5

vin1b_d5 gpio2_14 14 IO Driver off 15 I

gpmc_a25 gpmc_a25 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage

mmc2_dat1 1 IO gpmc_a19 2 O vin2b_d6

vin1b_d6 gpio2_15 14 IO Driver off 15 I

gpmc_a26 gpmc_a26 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage

mmc2_dat2 1 IO gpmc_a20 2 O vin2b_d7

vin1b_d7 gpio2_16 14 IO Driver off 15 I

gpmc_a27 gpmc_a27 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage

mmc2_dat3 1 IO gpmc_a21 2 O vin2b_hsync1

vin1b_hsync1 gpio2_17 14 IO Driver off 15 I

MUXMODE

[5]

4 I

6 I

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET REL.

STATE [8]

BALL

RESET REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER [11] HYS [12]

BUFFER

TYPE [13]

LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

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Table 4-2. Ball Characteristics

BALL NUMBER

[1]

M6 gpmc_ad0 gpmc_ad0 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage

M2 gpmc_ad1 gpmc_ad1 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage

L5 gpmc_ad2 gpmc_ad2 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage

M1 gpmc_ad3 gpmc_ad3 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage

L6 gpmc_ad4 gpmc_ad4 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage

L4 gpmc_ad5 gpmc_ad5 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage

L3 gpmc_ad6 gpmc_ad6 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage

BALL NAME [2] SIGNAL NAME [3] PN [4]

vin1a_d0 2 I vout3_d0 No 3 O gpio1_6 14 IO sysboot0 15 I

vin1a_d1 2 I vout3_d1 No 3 O gpio1_7 14 IO sysboot1 15 I

vin1a_d2 2 I vout3_d2 No 3 O gpio1_8 14 IO sysboot2 15 I

vin1a_d3 2 I vout3_d3 No 3 O gpio1_9 14 IO sysboot3 15 I

vin1a_d4 2 I vout3_d4 No 3 O gpio1_10 14 IO sysboot4 15 I

vin1a_d5 2 I vout3_d5 No 3 O gpio1_11 14 IO sysboot5 15 I

vin1a_d6 2 I vout3_d6 No 3 O gpio1_12 14 IO sysboot6 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET REL.

STATE [8]

BALL

RESET REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER [11] HYS [12]

BUFFER

TYPE [13]

LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

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SPRS957I –MARCH 2016–REVISED NOVEMBER 2019

Table 4-2. Ball Characteristics

BALL NUMBER

[1]

L2 gpmc_ad7 gpmc_ad7 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage

L1 gpmc_ad8 gpmc_ad8 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage

K2 gpmc_ad9 gpmc_ad9 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage

J1 gpmc_ad10 gpmc_ad10 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage

J2 gpmc_ad11 gpmc_ad11 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage

H1 gpmc_ad12 gpmc_ad12 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage

J3 gpmc_ad13 gpmc_ad13 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage

BALL NAME [2] SIGNAL NAME [3] PN [4]

vin1a_d7 2 I vout3_d7 No 3 O gpio1_13 14 IO sysboot7 15 I

vin1a_d8 2 I vout3_d8 No 3 O gpio7_18 14 IO sysboot8 15 I

vin1a_d9 2 I vout3_d9 No 3 O gpio7_19 14 IO sysboot9 15 I

vin1a_d10 2 I vout3_d10 No 3 O gpio7_28 14 IO sysboot10 15 I

vin1a_d11 2 I vout3_d11 No 3 O gpio7_29 14 IO sysboot11 15 I

vin1a_d12 2 I vout3_d12 No 3 O gpio1_18 14 IO sysboot12 15 I

vin1a_d13 2 I vout3_d13 No 3 O gpio1_19 14 IO sysboot13 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET REL.

STATE [8]

BALL

RESET REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER [11] HYS [12]

BUFFER

TYPE [13]

LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

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Table 4-2. Ball Characteristics

BALL NUMBER

[1]

H2 gpmc_ad14 gpmc_ad14 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage

H3 gpmc_ad15 gpmc_ad15 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage

N1 gpmc_advn_ale gpmc_advn_ale 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage

N6 gpmc_ben0 gpmc_ben0 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage

BALL NAME [2] SIGNAL NAME [3] PN [4]

vin1a_d14 2 I vout3_d14 No 3 O gpio1_20 14 IO sysboot14 15 I

vin1a_d15 2 I vout3_d15 No 3 O gpio1_21 14 IO sysboot15 15 I

gpmc_cs6 1 O clkout2 2 O gpmc_wait1 3 I vin2a_vsync0

vin1a_vsync0 gpmc_a2 5 O gpmc_a23 6 O timer3 7 IO i2c3_sda 8 IO dma_evt2 9 I gpio2_23

gpmc_a19 Driver off 15 I

gpmc_cs4 1 O vin2b_de1

vin1b_de1 timer2 7 IO dma_evt3 9 I gpio2_26

gpmc_a21 Driver off 15 I

MUXMODE

[5]

4 I

14 IO

6 I

14 IO

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET REL.

STATE [8]

BALL

RESET REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER [11] HYS [12]

BUFFER

TYPE [13]

LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

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+ 374 hidden pages

Texas Instruments AM5718, AM5716 Datasheet

1 Device Overview

1.1 Features

1.2 Applications

1.3 Description

1.4 Functional Block Diagram

Table of Contents

2 Revision History

3 Device Comparison

3.1 Related Products

4 Terminal Configuration and Functions

4.1 Terminal Assignment

4.1.1 Unused Balls Connection Requirements

4.2 Ball Characteristics