Open-Circuit, Short-Circuit, and Terminated
Fail-Safe
D
–0.3-V to 5.5-V Common-Mode Range With
±200 mV Sensitivity
D
Accepts 5-V Logic Inputs With a 3.3-V V
D
Input Hysteresis . . . 50 mV T yp
D
235 mW With Four Receivers at 32 MHz
D
Pin-to-Pin Compatible With AM26C32,
AM26LS32, and MB570
CC
D OR NS† PACKAGE
(TOP VIEW)
16
1
1B
2
1A
3
1Y
4
G
5
2Y
6
2A
7
2B
GND
†
The NS package is only available
left-ended taped and reeled.
8
15
14
13
12
11
10
V
CC
4B
4A
4Y
G
3Y
3A
9
3B
description
The AM26L V32, BiCMOS, quadruple, differential line receiver with 3-state outputs is designed to be similar to
TIA/EIA-422-B and ITU Recommendation V.11 receivers with reduced common-mode voltage range due to
reduced supply voltage.
The device is optimized for balanced bus transmission at switching rates up to 32 MHz. The enable function
is common to all four receivers and offers a choice of active-high or active-low inputs. The 3-state outputs permit
connection directly to a bus-organized system. Each device features receiver high input impedance and input
hysteresis for increased noise immunity , and input sensitivity of ±200 mV over a common-mode input voltage
range from –0.3 V to 5.5 V . When the inputs are open circuited, the outputs are in the high logic state. This device
is designed using the Texas Instruments (TI) proprietary LinIMPACT-C60 technology, facilitating ultra-low
power consumption without sacrificing speed.
This device offers optimum performance when used with the AM26LV31 quadruple line drivers.
The AM26LV32C is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each receiver)
DIFFERENTIAL
INPUT
VID ≥ 0.2 V
–0.2 V < VID < 0.2 V
VID ≤ –0.2 V
Open, shorted, or
terminated
H = high level, L = low level, X = irrelevant,
Z = high impedance (off), ? = indeterminate
‡
See application information attached.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
‡
XLHZ
ENABLES
GG
H
X
H
X
H
X
H
X
X
L
X
L
X
L
X
L
H
H
?
?
L
L
H
H
LinIMP ACT-C60 and TI are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2000, Texas Instruments Incorporated
1
AM26LV32
LOW-VOLTAGE HIGH-SPEED
QUADRUPLE DIFFERENTIAL LINE RECEIVER
SLLS202D – MAY 1995 – REVISED APRIL 2000
1A
1B
2A
2B
3A
3B
4A
4B
†
4
G
12
G
2
1
6
7
10
9
14
15
≥ 1
EN
11
13
3
1Y
5
2Y
3Y
4Y
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
schematics of equivalent inputs and outputs
EQUIVALENT OF EACH INPUT (A, B)
V
CC
EQUIVALENT OF EACH
ENABLE INPUT (G, G
V
CC
logic diagram (positive logic)
4
G
12
G
2
1A
1
1B
6
2A
7
2B
10
3A
9
3B
14
4A
15
4B
)
TYPICAL OF ALL OUTPUTS (Y)
11
13
3
1Y
5
2Y
3Y
4Y
V
CC
A, B
GND
1.5 kΩ
15 kΩ
1.5 kΩ
7.2 kΩ
7.2 kΩ
Enable
G, G
GND
100 Ω
Y
GND
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
AM26LV32
LOW-VOLTAGE HIGH-SPEED
QUADRUPLE DIFFERENTIAL LINE RECEIVER
SLLS202D – MAY 1995 – REVISED APRIL 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the GND terminal.
2. Differential input voltage is measured at the noninverting input with respect to the corresponding inverting input.
3. The package thermal impedance is calculated in accordance with JESD 51.
Supply voltage, V
High-level input voltage, V
Low-level input voltage, V
Common-mode input voltage, V
Differential input voltage, V
High-level output current, I
Low-level output current, I
Operating free-air temperature, T
CC
IH(EN)
IL(EN)
ID
OH
OL
IC
A
AM26LV32C070°C
33.33.6V
2V
0.8V
–0.35.5V
±5.8
–5mA
5mA
†
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
AM26LV32
A
See Figure 1
LOW-VOLTAGE HIGH-SPEED
QUADRUPLE DIFFERENTIAL LINE RECEIVER
SLLS202D – MAY 1995 – REVISED APRIL 2000
electrical characteristics over recommended supply-voltage and operating free-air temperature
ranges (unless otherwise noted)
Input currentVI = 5.5 V or –0.3 V,All other inputs GND±700µA
I
Supply currentV
CC
Power dissipation capacitance
pd
All typical values are at VCC = 3.3 V and TA = 25°C.
Cpd determines the no-load dynamic current: IS = Cpd × VCC × f + ICC.
‡
I(E)
One channel150pF
CC
= VCC or GND, No load, line inputs open817mA
±50µA
µ
switching characteristics, VCC = 3.3 V, TA = 25°C
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
t
PLH
t
PHL
t
t
t
PZH
t
PZL
t
PHZ
t
PLZ
t
sk(p)
t
sk(o)
t
sk(pp)
§
t
¶
t
#
t
sk(p)
sk(o)
sk(pp)
Propagation delay time, low- to high-level output
Propagation delay time, high- to low-level output
Transistion time (tr or tf)See Figure 15ns
Output-enable time to high levelSee Figure 21740ns
Output-enable time to low levelSee Figure 31040ns
Output-disable time from high levelSee Figure 22040ns
Output-disable time from low levelSee Figure 31640ns
§
Pulse skew46ns
¶
Pulse skew46ns
#
Pulse skew (device to device)69ns
is |t
is the maximum difference in propagation delay times between any two channels of the same device switching in the same direction.
– t
PLH
is the maximum difference in propagation delay times between any two channels of any two devices switching in the same direction.
| of each channel of the same device.
PHL
81620ns
81620ns
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
AM26LV32
LOW-VOLTAGE HIGH-SPEED
QUADRUPLE DIFFERENTIAL LINE RECEIVER
SLLS202D – MAY 1995 – REVISED APRIL 2000
PARAMETER MEASUREMENT INFORMATION
Generator
(see Note B)
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: ZO = 50 Ω, PRR = 10 MHz, tr and tf (10% to 90%)
≤ 2 ns, 50% duty cycle.
C. To test the active-low enable G
A
B
50 Ω50 Ω
V
CC
Figure 1. t
Generator
(see Note B)
GG
(see Note C)
, ground G and apply an inverted waveform G.
PLH
Y
and t
V
O
CL = 15 pF
(see Note A)
PHL
VID = 1 V
50 Ω
A
Input
B
t
PLH
Output
50%50%
10%10%
t
r
Test Circuit and Voltage Waveforms
A
B
G
G
Y
RL = 2 kΩ
CL = 15 pF
(see Note A)
90%90%
V
O
t
PHL
2 V
1 V
V
OH
V
OL
t
f
Input
t
PZH
Output
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: ZO = 50 Ω, PRR = 10 MHz, tr and tf (10% to 90%)
≤ 2 ns, 50% duty cycle.
C. To test the active-low enable G
Figure 2. t
, ground G and apply an inverted waveform G.
and t
PZH
V
CC
(see Note C)
50%
Test Circuit and Voltage Waveforms
PHZ
50%
50%
t
PHZ
VOH – 0.3 V
V
0 V
V
V
CC
OH
off
≈ 0
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
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