Texas instruments AM1802 User Manual

AM1802

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AM1802 ARM Microprocessor

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1 AM1802 ARM Microprocessor

1.1 Features

• Highlights – 300-MHz ARM926EJ-S™ RISC Core – ARM9 Memory Architecture – Enhanced Direct-Memory-Access Controller

3 (EDMA3) – Two External Memory Interfaces – Three Configurable 16550 type UART

Modules – Two Serial Peripheral Interfaces (SPI) – Multimedia Card (MMC)/Secure Digital (SD)

Card Interface with Secure Data I/O (SDIO) – One Master/Slave Inter-Integrated Circuit – USB 2.0 OTG Port With Integrated PHY – One Multichannel Audio Serial Port – 10/100 Mb/s Ethernet MAC (EMAC) – Three 64-Bit General-Purpose Timers – One 64-bit General-Purpose/Watchdog Timer

• 300-MHz ARM926EJ-S™ RISC MPU

• ARM926EJ-S Core – 32-Bit and 16-Bit (Thumb®) Instructions – Single Cycle MAC – ARM® Jazelle® Technology – EmbeddedICE-RT™ for Real-Time Debug

• ARM9 Memory Architecture – 16K-Byte Instruction Cache – 16K-Byte Data Cache – 8K-Byte RAM (Vector Table) – 64K-Byte ROM

• Enhanced Direct-Memory-Access Controller 3 (EDMA3):

– 2 Channel Controllers – 3 Transfer Controllers – 64 Independent DMA Channels – 16 Quick DMA Channels – Programmable Transfer Burst Size

• 128K-Byte On-chip Memory

• 1.8V or 3.3V LVCMOS IOs (except for USB and DDR2 interfaces)

• Two External Memory Interfaces: – EMIFA

• NOR (8-/16-Bit-Wide Data)

SPRS710–NOVEMBER 2010

• NAND (8-/16-Bit-Wide Data)

• 16-Bit SDRAM With 128 MB Address Space

– DDR2/Mobile DDR Memory Controller

• 16-Bit DDR2 SDRAM With 512 MB Address Space or

• 16-Bit mDDR SDRAM With 256 MB Address Space

• Three Configurable 16550 type UART Modules: – With Modem Control Signals – 16-byte FIFO – 16x or 13x Oversampling Option

• Two Serial Peripheral Interfaces (SPI) Each With Multiple Chip-Selects

• One Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO) Interfaces

• One Master/Slave Inter-Integrated Circuit (I2C Bus™)

• One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address/Data Bus For High Bandwidth

• USB 2.0 OTG Port With Integrated PHY (USB0) – USB 2.0 High-/Full-Speed Client – USB 2.0 High-/Full-/Low-Speed Host – End Point 0 (Control) – End Points 1,2,3,4 (Control, Bulk, Interrupt or

ISOC) Rx and Tx

• One Multichannel Audio Serial Port: – Transmit/Receive Clocks – Two Clock Zones and 16 Serial Data Pins – Supports TDM, I2S, and Similar Formats – DIT-Capable – FIFO buffers for Transmit and Receive

• 10/100 Mb/s Ethernet MAC (EMAC): – IEEE 802.3 Compliant – MII Media Independent Interface – RMII Reduced Media Independent Interface – Management Data I/O (MDIO) Module

• Real-Time Clock With 32 KHz Oscillator and Separate Power Rail

• Three One 64-Bit General-Purpose Timers (Each configurable as Two 32-Bit Timers)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2ARM926EJ-S is a trademark of ARM Limited.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

AM1802

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• One 64-bit General-Purpose/Watchdog Timer • Industrial Temperature (Configurable as Two 32-bit General-Purpose Timers)

• 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZWT Suffix], 0.80-mm Ball Pitch

• Community Resources – TI E2E Community – TI Embedded Processors Wiki

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1.2 Trademarks

All trademarks are the property of their respective owners.

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1.3 Description

The device is a Low-power applications processor based on ARM926EJ-S™. The device enables OEMs and ODMs to quickly bring to market devices featuring robust operating

systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core has a coprocessor 15 (CP15), protection module, and Data and program Memory Management Units (MMUs) with table look-aside buffers. It has separate 16K-byte instruction and 16K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also has a 8KB RAM (Vector Table) and 64KB ROM.

The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; one USB2.0 OTG interface; one inter-integrated circuit (I2C) Bus interfaces; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two SPI interfaces with multiple chip selects; four 64-bit general-purpose timers each configurable (one configurable as watchdog) ; up to 9 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; three UART interfaces (each with RTS and CTS); and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed DDR2/Mobile DDR controller.

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The Ethernet Media Access Controller (EMAC) provides an efficient interface between the device and a network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode. Additionally an Management Data Input/Output (MDIO) interface is available for PHY configuration. The EMAC supports both MII and RMII interfaces.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the ARM . These include C compilers, and scheduling, and a Windows™ debugger interface for visibility into source code execution.

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Switched Central Resource (SCR)

16KB

I-Cache

16KB

D-Cache

4KB ETB

ARM926EJ-S CPU

With MMU

ARM Subsystem

JTAG Interface

System Control

Input

Clock(s)

64KB ROM

8KB RAM

(Vector Table)

Power/Sleep

Controller

Multiplexing

PLL/Clock Generator

w/OSC

GeneralPurpose

Timer (x3)

Serial Interfaces

Audio Ports

McASP w/FIFO

DMA

Peripherals

Internal Memory

128KB

RAM

External Memory InterfacesConnectivity

EDMA3

(x2)

EMIFA(8b/16B)

NAND/Flash 16b SDRAM

DDR2/MDDR

Controller

RTC/

32-kHz

OSC

I C

(x1)

SPI (x2)

UART

(x3)

EMAC 10/100

(MII/RMII)

MDIO

USB2.0

OTG Ctlr

PHY

HPI

MMC/SD

(8b) (x1)

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1.4 Functional Block Diagram

SPRS710–NOVEMBER 2010

Figure 1-1. Functional Block Diagram

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2 Device Overview

2.1 Device Characteristics

Table 2-1 provides an overview of the device. The table shows significant features of the device, including

the capacity of on-chip RAM, peripherals, and the package type with pin count.

Table 2-1. Characteristics of the Device

HARDWARE FEATURES AM1802

DDR2/mDDR Controller

EMIFA Flash Card Interface MMC and SD cards supported.

Peripherals Not all peripherals pins

are available at the same time (for more detail, see the Device Configurations section).

On-Chip Memory

JTAG BSDL_ID DEVIDR0 Register 0x0B7D_102F CPU Frequency MHz ARM926 300 MHz (1.2V)

Voltage

Packages 16 mm x 16 mm, 361-Ball 0.80 mm pitch, PBGA (ZWT)

Product Status

(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

(1)

EDMA3

Timers UART 3 (each with RTS and CTS flow control)

SPI 1 (With one hardware chip select) I2C 1 (Master/Slave) Multichannel Audio Serial Port [McASP] 1 (each with transmit/receive, FIFO buffer, 16 serializers) 10/100 Ethernet MAC with Management Data I/O 1 (MII or RMII Interface) USB 2.0 (USB0) High-Speed OTG Controller with on-chip OTG PHY General-Purpose Input/Output Port 9 banks of 16-bit Size (Bytes) 168KB RAM

Organization 8KB RAM (Vector Table)

Core (V) 1.2 V nominal for 300 MHz I/O (V) 1.8V or 3.3 V

Product Preview (PP), Advance Information (AI), PD or Production Data (PD)

4 64-Bit General Purpose (each configurable as 2 separate

DDR2, 16-bit bus width, up to 150 MHz

Mobile DDR, 16-bit bus width, up to 133 MHz

Asynchronous (8/16-bit bus width) RAM, Flash,

16-bit SDRAM, NOR, NAND

64 independent channels, 16 QDMA channels,

2 channel controllers, 3 transfer controllers

32-bit timers, one configurable as Watch Dog)

ARM

16KB I-Cache

16KB D-Cache

64KB ROM

ADDITIONAL MEMORY

128KB RAM

2.2 Device Compatibility

The ARM926EJ-S RISC CPU is compatible with other ARM9 CPUs from ARM Holdings plc.

2.3 ARM Subsystem

The ARM Subsystem includes the following features:

• ARM926EJ-S RISC processor

• ARMv5TEJ (32/16-bit) instruction set

• Little endian

• System Control Co-Processor 15 (CP15)

• MMU

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• 16KB Instruction cache

• 16KB Data cache

• Write Buffer

• Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)

• ARM Interrupt controller

2.3.1 ARM926EJ-S RISC CPU

The ARM Subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications where full memory management, high performance, low die size, and low power are all important. The ARM926EJ-S processor supports the 32-bit ARM and 16 bit THUMB instruction sets, enabling the user to trade off between high performance and high code density. Specifically, the ARM926EJ-S processor supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes, providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code overhead.

The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a complete high performance subsystem, including:

• ARM926EJ -S integer core

• CP15 system control coprocessor

• Memory Management Unit (MMU)

• Separate instruction and data caches

• Write buffer

• Separate instruction and data (internal RAM) interfaces

• Separate instruction and data AHB bus interfaces

• Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)

SPRS710–NOVEMBER 2010

For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available at http://www.arm.com

2.3.2 CP15

The ARM926EJ-S system control coprocessor (CP15) is used to configure and control instruction and data caches, Memory Management Unit (MMU), and other ARM subsystem functions. The CP15 registers are programmed using the MRC and MCR ARM instructions, when the ARM in a privileged mode such as supervisor or system mode.

2.3.3 MMU

A single set of two level page tables stored in main memory is used to control the address translation, permission checks and memory region attributes for both data and instruction accesses. The MMU uses a single unified Translation Lookaside Buffer (TLB) to cache the information held in the page tables. The MMU features are:

• Standard ARM architecture v4 and v5 MMU mapping sizes, domains and access protection scheme.

• Mapping sizes are: – 1MB (sections) – 64KB (large pages) – 4KB (small pages) – 1KB (tiny pages)

• Access permissions for large pages and small pages can be specified separately for each quarter of the page (subpage permissions)

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• Hardware page table walks

• Invalidate entire TLB, using CP15 register 8

• Invalidate TLB entry, selected by MVA, using CP15 register 8

• Lockdown of TLB entries, using CP15 register 10

2.3.4 Caches and Write Buffer

The size of the Instruction cache is 16KB, Data cache is 16KB. Additionally, the caches have the following features:

• Virtual index, virtual tag, and addressed using the Modified Virtual Address (MVA)

• Four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with two dirty bits in the Dcache

• Dcache supports write-through and write-back (or copy back) cache operation, selected by memory region using the C and B bits in the MMU translation tables

• Critical-word first cache refilling

• Cache lockdown registers enable control over which cache ways are used for allocation on a line fill, providing a mechanism for both lockdown, and controlling cache corruption

• Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the TAG RAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the possibility of TLB misses related to the write-back address.

• Cache maintenance operations provide efficient invalidation of, the entire Dcache or Icache, regions of the Dcache or Icache, and regions of virtual memory.

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The write buffer is used for all writes to a noncachable bufferable region, write-through region and write misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for cache line evictions or cleaning of dirty cache lines. The main write buffer has 16-word data buffer and a four-address buffer. The Dcache write-back has eight data word entries and a single address entry.

2.3.5 Advanced High-Performance Bus (AHB)

The ARM Subsystem uses the AHB port of the ARM926EJ-S to connect the ARM to the Config bus and the external memories. Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB by the Config Bus and the external memories bus.

2.3.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)

To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an Embedded Trace Macrocell (ETM). The ARM926ES-J Subsystem in the device also includes the Embedded Trace Buffer (ETB). The ETM consists of two parts:

• Trace Port provides real-time trace capability for the ARM9.

• Triggering facilities provide trigger resources, which include address and data comparators, counter, and sequencers.

The device trace port is not pinned out and is instead only connected to the Embedded Trace Buffer. The ETB has a 4KB buffer memory. ETB enabled debug tools are required to read/interpret the captured trace data.

2.3.7 ARM Memory Mapping

By default the ARM has access to most on and off chip memory areas, including EMIFA, DDR2, and the additional 128K byte on chip SRAM. Likewise almost all of the on chip peripherals are accessible to the ARM by default.

See Table 2-2 for a detailed top level device memory map that includes the ARM memory space.

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2.4 Memory Map Summary

Table 2-2. AM1802 Top Level Memory Map

Start End Address Size ARM Mem Map EDMA Mem Map Master Peripheral Mem Map

Address

0x0000 0000 0x0000 0FFF 4K 0x0000 1000 0x01BB FFFF

0x01BC 0000 0x01BC 0FFF 4K ARM ETB

0x01BC 1000 0x01BC 17FF 2K ARM ETB reg 0x01BC 1800 0x01BC 18FF 256 ARM Ice

0x01BC 1900 0x01BF FFFF

0x01C0 0000 0x01C0 7FFF 32K EDMA3 CC 0x01C0 8000 0x01C0 83FF 1K EDMA3 TC0 0x01C0 8400 0x01C0 87FF 1K EDMA3 TC1 0x01C0 8800 0x01C0 FFFF 0x01C1 0000 0x01C1 0FFF 4K PSC 0 0x01C1 1000 0x01C1 1FFF 4K PLL Controller 0 0x01C1 2000 0x01C1 3FFF 0x01C1 4000 0x01C1 4FFF 4K SYSCFG0 0x01C1 5000 0x01C1 FFFF 0x01C2 0000 0x01C2 0FFF 4K Timer0 0x01C2 1000 0x01C2 1FFF 4K Timer1 0x01C2 2000 0x01C2 2FFF 4K I2C 0 0x01C2 3000 0x01C2 3FFF 4K RTC 0x01C2 4000 0x01C3 FFFF 0x01C4 0000 0x01C4 0FFF 4K MMC/SD 0 0x01C4 1000 0x01C4 1FFF 4K SPI 0 0x01C4 2000 0x01C4 2FFF 4K UART 0 0x01C4 3000 0x01CF FFFF 0x01D0 0000 0x01D0 0FFF 4K McASP 0 Control 0x01D0 1000 0x01D0 1FFF 4K McASP 0 AFIFO Ctrl 0x01D0 2000 0x01D0 2FFF 4K McASP 0 Data

0x01D0 3000 0x01D0 BFFF 0x01D0 C000 0x01D0 CFFF 4K UART 1 0x01D0 D000 0x01D0 DFFF 4K UART 2 0x01D0 E000 0x01DF FFFF

0x01E0 0000 0x01E0 FFFF 64K USB0

0x01E1 0000 0x01E1 3FFF

0x01E1 4000 0x01E1 4FFF 4K Memory Protection Unit 1 (MPU 1)

0x01E1 5000 0x01E1 5FFF 4K Memory Protection Unit 2 (MPU 2)

0x01E1 6000 0x01E1 9FFF

0x01E1 A000 0x01E1 AFFF 4K PLL Controller 1 0x01E1 B000 0x01E1 FFFF 0x01E2 0000 0x01E2 1FFF 8K EMAC Control Module RAM 0x01E2 2000 0x01E2 2FFF 4K EMAC Control Module Registers 0x01E2 3000 0x01E2 3FFF 4K EMAC Control Registers 0x01E2 4000 0x01E2 4FFF 4K EMAC MDIO port 0x01E2 5000 0x01E2 5FFF 0x01E2 6000 0x01E2 6FFF 4K GPIO

memory

Crusher

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Table 2-2. AM1802 Top Level Memory Map (continued)

Start End Address Size ARM Mem Map EDMA Mem Map Master Peripheral Mem Map

Address

0x01E2 7000 0x01E2 7FFF 4K PSC 1

0x01E2 8000 0x01E2 BFFF 0x01E2 C000 0x01E2 CFFF 4K SYSCFG1 0x01E2 D000 0x01E2 FFFF

0x01E3 0000 0x01E3 7FFF 32K EDMA3 CC1

0x01E3 8000 0x01E3 83FF 1K EDMA3 TC2

0x01E3 8400 0x01F0 BFFF

0x01F0 C000 0x01F0 CFFF 4K Timer2

0x01F0 D000 0x01F0 DFFF 4K Timer3

0x01F0 E000 0x01F0 EFFF 4K SPI1

0x01F0 F000 0x3FFF FFFF

0x4000 0000 0x5FFF FFFF 512M EMIFA SDRAM data (CS0) 0x6000 0000 0x61FF FFFF 32M EMIFA async data (CS2) 0x6200 0000 0x63FF FFFF 32M EMIFA async data (CS3) 0x6400 0000 0x65FF FFFF 32M EMIFA async data (CS4) 0x6600 0000 0x67FF FFFF 32M EMIFA async data (CS5) 0x6800 0000 0x6800 7FFF 32K EMIFA Control Regs 0x6800 8000 0x7FFF FFFF 0x8000 0000 0x8001 FFFF 128K On-chip RAM

0x8002 0000 0xAFFF FFFF 0xB000 0000 0xB000 7FFF 32K DDR2 Control Regs 0xB000 8000 0xBFFF FFFF 0xC000 0000 0xDFFF FFFF 512M DDR2 Data 0xE000 0000 0xFFFC FFFF

0xFFFD 0000 0xFFFD FFFF 64K ARM local

ROM 0xFFFE 0000 0xFFFE DFFF 0xFFFE E000 0xFFFE FFFF 8K ARM Interrupt

Controller

0xFFFF 0000 0xFFFF 1FFF 8K ARM local

RAM

0xFFFF 2000 0xFFFF FFFF

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10987654321

DVDD3318_C

GP6[1]

VSS

NC_L1

GP6[3]

NC_L2

RSV3

NC_N1

NC_N3NC_N2

RSV3

NC_P3

RSV3

DVDD3318_C

DDR_A[11]

GP7[7]/

BOOT[7]

DD3318_C

DD18

DDR_DVDD18 DDR_DVDD18

DDR_D[15]

DDR_RAS

DDR_CLKP

DDR_CLKN

DDR_A[2]DDR_A[10]

GP6[0]

DDR_A[13]

DDR_CAS

DDR_A[5]

DDR_CKE

DDR_BA[0]

DDR_A[9] DDR_A[1]

DDR_WE

DDR_D[10]

DDR_A[7]

DDR_A[0] DDR_D[12]

DDR_A[12] DDR_A[3]

DDR_CS

DDR_A[6]

DDR_DQM[1]

VSS

DDR_DVDD18

GP7[4]/

BOOT[4]

DDR_VREF

DDR_BA[1]

DDR_A[8]

DDR_A[4]

DDR_BA[2]

VSS

DDR_D[13]

DD18

NC_M3

DDR_DVDD18DDR_DVDD18DDR_DVDD18DDR_DVDD18

DVDD3318_C

GP7[5]/

BOOT[5]

GP7[6]/

BOOT[6]

DDR_DVDD18 DDR_DVDD18 DDR_DVDD18

GP7[1]/

BOOT[1]

GP7[2]/

BOOT[2]

GP7[3]/

BOOT[3]

GP7[14] GP7[15]

GP7[0]/

BOOT[0]

GP7[11] GP7[12] GP7[13]

GP7[8] GP7[9] GP7[10]

A B

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2.5 Pin Assignments

2.5.1 Pin Map (Bottom View)

SPRS710–NOVEMBER 2010

Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings.

The following graphics show the bottom view of the ZWT package pin assignments in four quadrants (A, B, C, and D). The pin assignments for both packages are identical.

Figure 2-1. Pin Map (Quad A)

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191817161514131211

NC_P15

DVDD3318_C

USB_CVDD

DVDD3318_C

DDR_DQGATE0

DVDD18

DDR_DQGATE1

DDR_D[9] DDR_D[8]DDR_D[11]

DVDD18

RTC_CVDD

RESET

USB0_DM USB0_DP

NC_R18

USB0_VDDA33 USB0_VBUS

NC_P18

RMII_CRS_DVRMII_MHZ_50_CLK

RMII_RXER

RMII_RXD[1]

GP6[10]

NC_P19

PLL0_VDDA

GP6[12]

USB0_VDDA18

RMII_TXEN

DDR_D[1] RMII_TXD[1]

OSCVSS

DDR_D[2] RMII_TXD[0] RMII_RXD[0]

NC_V19

EMU1

GP6[5]

USB0_VDDA12

TDI

NC_N16

GP6[8]

NC_T16

RESETOUT/

GP6[15]

RSV2

RTCK/

GP8[0]

OSCOUT

DDR_D[0]

GP6[9]

NC_U19

TRST

OSCIN

GP6[6]

NC_V18

NC_W14

NC_R19

DVDD3318_B

PLL0_VSSA

TMS

GP6[13]

NC PLL1_VSSA

PLL1_VDDA

NC_P14

USB0_ID

NC_R15

CLKOUT/

GP6[14]

USB0_DRVVBUS

DDR_DQS[0]

GP6[11]

DDR_DQM[0]

DDR_D[3]

DDR_D[4]

DDR_D[6]

DDR_ZP

DDR_D[5]

DDR_D[7]

DDR_D[14]

DDR_DQS[1]

DVDD3318_C

AA B

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Figure 2-2. Pin Map (Quad B)

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EMA_A[8]/

GP5[8]

EMA_A[14]/

MMCSD0_DAT[7]/

GP5[14]

EMA_A[15]/

MMCSD0_DAT[6]/

GP5[15]

EMA_A[10]/

GP5[10]

EMA_A[9]/

GP5[9]

EMA_A[13]/

GP5[13]

EMA_A[12]/

GP5[12]

EMA_A[16]/

MMCSD0_DAT[5]/

GP4[0]

EMA_A[18]/

MMCSD0_DAT[3]/

GP4[2]

DD3318_B

DD18

EMA_A[6]/

GP5[6]

EMA_A[5]/

GP5[5]

EMA_A[2]/

GP5[2]

EMA_A7/

GP5[7]

EMA_A[4]/

GP5[4]

SPI0_SIMO/

GP8[5]/

MII_CRS

SPI0_SCS[5]/ UART0_RXD/

GP8[4]/

MII_RXD[3]

SPI1_SCS[1]/

GP2[15]/

TM64P2_IN12

SPI0_SCS[4]/ UART0_TXD/

GP8[3]/

MII_RXD[2]

SPI0_CLK/

GP1[8]/

MII_RXCLK

SPI1_SCS[3]/ UART1_RXD/

GP1[1]

SPI1_SCS[0]/

GP2[14]/

TM64P3_IN12

EMA_OE/

GP3[10]

SPI1_SCS[4]/ UART2_TXD/

GP1[2]

EMA_A[3]/

GP5[3]

DD18

RTC_VSS

EMA_WAIT[0]/

GP3[8]

EMA_RAS/

GP2[5]

SPI0_SCS[3] UART0_CTS//

GP8[2]/

MII_RXD[1]

SPI0_SCS[0]/

TM64P1_OUT12/

GP1[6]/

MDIO_D/

TM64P1_IN12

SPI0_SOMI/

GP8[6]/

MII_RXER

SPI0_SCS[2] UART0_RTS//

GP8[1]/

MII_RXD[0]

SPI1_SCS[7]/

I2C0_SCL/

TM64P2_OUT12/

GP1[5]

SPI1_SIMO/

GP2[10]

SPI1_CLK/

GP2[13]

EMA_CS[3]/

GP3[14]

SPI1_ENA/

GP2[12]

RTC_XO

EMA_CS[2]/

GP3[15]

EMA_WAIT[1]/

GP2[1]

EMA_A[20]/

MMCSD0_DAT[1]/

GP4[4]

EMA_BA[1]/

GP2[9]

SPI0_ENA/

MII_RXDV

EMA_CS[5]/

GP3[12]

SPI1_SCS[5]/ UART2_RXD/

GP1[3]

EMA_A[0]/

GP5[0]

EMA_BA[0]/

GP2[8]

EMA_A[1]/

GP5[1]

DD3318_B

SPI0_SCS[1]/

TM64P0_OUT12/

GP1[7]/

MDIO_CLK/

TM64P0_IN12

DD3318_A

SPI1_SCS[6]/

I2C0_SDA/

TM64P3_OUT12/

GP1[4]

EMA_CS[0]/

GP2[0]

SPI1_SOMI/

GP2[11]

TDO

TCK

EMU0

RTC_XI

RSVDN

SPI1_SCS[2]/

UART1_TXD/

GP1[0]

EMA_A[11]/

GP5[11]

EMA_A[17]/

MMCSD0_DAT[4]/

GP4[1]

DD3318_B

DD18

DD3318_A

DD18

DD3318_B

A B

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Figure 2-3. Pin Map (Quad C)

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EMA_D[15]/

GP3[7]

AXR15/ GP0[7]

ACLKR/ GP0[15]

ACLKX/ GP0[14]

AHCLKX/

USB_REFCLKIN/

GP0[10]

UART1_CTS

AFSX/

GP0[12]

AFSR/

GP0[13]

AXR9/

GP0[1]

AXR4/ GP1[12]/ MII_COL

AXR5/

GP1[13]/

MII_TXCLK

AXR7/

GP1[15]

AXR10/ GP0[2]

AXR1/

GP1[9]/

MII_TXD[1]

AXR3/

GP1[11]/

MII_TXD[3]

AXR2/

GP1[10]/

MII_TXD[2]

GP8[10]

RTC_ALARM/

GP0[8]/

UART2_CTS

DEEPSLEEP

AXR0/

GP8[7]/

MII_TXD[0]

GP8[14] GP8[8]

VSS

GP8[12]

AXR8/

GP0[0]

AXR12/ GP0[4]

EMA_D[4]/

GP4[12]

AXR14/ GP0[6]

EMA_WEN_DQM[1]/

GP2[2]

EMA_D[0]/

GP4[8]

EMA_A[19]/

MMCSD0_DAT[2]/

GP4[3]

EMA_D[9]/

GP3[1]

EMA_A_R /

GP3[9]

MMCSD0_CLK/

GP4[7]

EMA_D[8]/

GP3[0]

EMA_D[13]/

GP3[5]

GP6[4]

GP6[2]

AMUTE/

GP0[9]

UART2_RTS/

DD3318_A

EMA_WE/

GP3[11]

EMA_D[10]/

GP3[2]

EMA_D[3]/

GP4[11]

EMA_SDCKE/

GP2[6]

EMA_D[14]/

GP3[6]

EMA_D[7]/

GP4[15]

EMA_D[1]/

GP4[9]

EMA_A[22]/

MMCSD0_CMD/

GP4[6]

EMA_D[2]/

GP4[10]

EMA_A[21]/

MMCSD0_DAT[0]/

GP4[5]

GP8[13]

AHCLKR/

GP0[11]

UART1_RTS

EMA_D[12]/

GP3[4]

EMA_WEN_DQM[0]/

GP2[3]

EMA_CLK/

GP2[7]

AXR6/

GP1[14]/

MII_TXEN

AXR11/ GP0[3]

EMA_D[6]/

GP4[14]

EMA_D[11]/

GP3[3]

EMA_D[5]/

GP4[13]

GP8[11]

GP8[9]

GP8[15]

AXR13/

GP0[5]

EMA_CS[4]/

GP3[13]

EMA_CAS/

GP2[4]

DD3318_B

DD18

DD3318_B

DD18

VSS

DD3318_A

NC_J1 NC_J2

DD3318_C

A B

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2.6 Pin Multiplexing Control

Figure 2-4. Pin Map (Quad D)

Device level pin multiplexing is controlled by registers PINMUX0 - PINMUX19 in the SYSCFG module. For the device family, pin multiplexing can be controlled on a pin-by-pin basis. Each pin that is multiplexed

with several different functions has a corresponding 4-bit field in one of the PINMUX registers. Pin multiplexing selects which of several peripheral pin functions controls the pin's IO buffer output data

and output enable values only. The default pin multiplexing control for almost every pin is to select 'none' of the peripheral functions in which case the pin's IO buffer is held tri-stated.

Note that the input from each pin is always routed to all of the peripherals that share the pin; the PINMUX registers have no effect on input from a pin.

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2.7 Terminal Functions

Table 2-3 to Table 2-20 identify the external signal names, the associated pin/ball numbers along with the

mechanical package designator, the pin type (I, O, IO, OZ, or PWR), whether the pin/ball has any internal pullup/pulldown resistors, whether the pin/ball is configurable as an IO in GPIO mode, and a functional pin description.

2.7.1 Device Reset and JTAG

Table 2-3. Reset and JTAG Terminal Functions

SIGNAL

NAME NO.

RESET K14 I IPU B Device reset input RESETOUT / GP6[15] T17 O

TMS L16 I IPU B JTAG test mode select TDI M16 I IPU B JTAG test data input TDO J18 O IPU B JTAG test data output TCK J15 I IPU B JTAG test clock TRST L17 I IPD B JTAG test reset EMU0 J16 I/O IPU B Emulation pin EMU1 K16 I/O IPU B Emulation pin RTCK/ GP8[0]

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.

(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor. CP[n] = configurable pull-up/pull-down (where n is the pin group) using

the PUPDENA and PUPDSEL registers in the System Module.

(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can

be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power

supply DVDD3318_C. (4) Open drain mode for RESETOUT function. (5) GP8[0] is initially configured as a reserved function after reset and will not be in a predictable state. This signal will only be stable after

the GPIO configuration for this pin has been completed. Users should carefully consider the system implications of this pin being in an

unknown state after reset.

(5)

K17 I/O IPD B JTAG Test Clock Return Clock Output

TYPE

(1)

PULL

RESET

(4)

CP[21] C Reset output

JTAG

(2)

POWER

GROUP

(3)

DESCRIPTION

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2.7.2 High-Frequency Oscillator and PLL

Table 2-4. High-Frequency Oscillator and PLL Terminal Functions

SIGNAL

NAME NO.

CLKOUT / GP6[14] T18 O CP[22] C PLL Observation Clock

OSCIN L19 I — — Oscillator input OSCOUT K19 O — — Oscillator output OSCVSS L18 GND — — Oscillator ground

PLL0_VDDA L15 PWR — — PLL analog VDD(1.2-V filtered supply) PLL0_VSSA M17 GND — — PLL analog VSS(for filter)

PLL1_VDDA N15 PWR — — PLL analog VDD(1.2-V filtered supply) PLL1_VSSA M15 GND — — PLL analog VSS(for filter)

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for

that particular peripheral. (2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using

the PUPDENA and PUPDSEL registers in the System Module. (3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can

be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of

power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power

supply DVDD3318_C.

TYPE

(1)

PULL

1.2-V OSCILLATOR

1.2-V PLL0

1.2-V PLL1

(2)

POWER

GROUP

(3)

DESCRIPTION

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2.7.3 Real-Time Clock and 32-kHz Oscillator

Table 2-5. Real-Time Clock (RTC) and 1.2-V, 32-kHz Oscillator Terminal Functions

SIGNAL

NAME NO.

TYPE

(1)

PULL

RTC_XI J19 I — — RTC 32-kHz oscillator input RTC_XO H19 O — — RTC 32-kHz oscillator output RTC_ALARM / UART2_CTS / GP0[8] / DEEPSLEEP F4 O CP[0] A RTC Alarm

RTC_CVDD L14 PWR — — RTC_V

H18 GND — — Oscillator ground

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for

that particular peripheral. (2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using

the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the

device is out of reset. During reset, all of the pins associated with these registers are pulled down. If the application requires a pull-up,

an external pull-up can be used. For electrical specifications on the pull-up and and internal pull-down circuits, see the Device Operating

Conditions section. (3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can

be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of

power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power

supply DVDD3318_C.

POWER

(2)

GROUP

(3)

DESCRIPTION

RTC module core power (isolated from chip CVDD)

2.7.4 DEEPSLEEP Power Control

Table 2-6. DEEPSLEEP Power Control Terminal Functions

SIGNAL

NAME NO.

TYPE

(1)

PULL

RTC_ALARM / UART2_CTS / GP0[8] / DEEPSLEEP F4 I CP[0] A DEEPSLEEP power control output