Texas instruments AM1707 User Manual

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AM1707 ARM Microprocessor

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1 AM1707 ARM Microprocessor

1.1 Features

123

• Highlights – 375/456-MHz ARM926EJ-S™ RISC Core – ARM9 Memory Architecture – Programmable Real-Time Unit Subsystem – Enhanced Direct-Memory-Access Controller

3 (EDMA3) • Two External Memory Interfaces: – Two External Memory Interfaces – EMIFA – Three Configurable 16550 type UART • NOR (8-/16-Bit-Wide Data)

Modules – Two Serial Peripheral Interfaces (SPI) – Multimedia Card (MMC)/Secure Digital (SD) Space

Card Interface with Secure Data I/O (SDIO) – Two Master/Slave Inter-Integrated Circuit – USB 2.0 OTG Port With Integrated PHY Address Space – Three Multichannel Audio Serial Ports • Three Configurable 16550 type UART Modules: – 10/100 Mb/s Ethernet MAC (EMAC) – UART0 With Modem Control Signals – One 64-Bit General-Purpose Timer – 16-byte FIFO – One 64-bit General-Purpose/Watchdog Timer – 16x or 13x Oversampling Option – Three Enhanced Pulse Width Modulators – Autoflow control signals (CTS, RTS) on – Three 32-Bit Enhanced Capture Modules

• Applications – Industrial Automation – Home Automation – Test and Measurement – Portable Data Terminals – Educational Consoles – Power Protection Systems

• 375/456-MHz ARM926EJ-S™ RISC Core – 32-Bit and 16-Bit (Thumb®) Instructions – Single Cycle MAC – ARM®Jazelle®Technology – EmbeddedICE-RT™ for Real-Time Debug

• ARM9 Memory Architecture – 16K-Byte Instruction Cache – 16K-Byte Data Cache – 8K-Byte RAM (Vector Table) – 64K-Byte ROM

• Enhanced Direct-Memory-Access Controller 3 (EDMA3):

– 2 Transfer Controllers

– 32 Independent DMA Channels – 8 Quick DMA Channels – Programmable Transfer Burst Size

• 128K-Byte RAM Memory

• 3.3V LVCMOS IOs (except for USB interfaces)

• NAND (8-/16-Bit-Wide Data)

• 16-Bit SDRAM With 128MB Address

– EMIFB

• 32-Bit or 16-Bit SDRAM With 256MB

UART0 only

• LCD Controller

• Two Serial Peripheral Interfaces (SPI) Each With One Chip-Select

• Programmable Real-Time Unit Subsystem (PRUSS)

– Two Independent Programmable Realtime

Unit (PRU) Cores

• 32-Bit Load/Store RISC architecture

• 4K Byte instruction RAM per core

• 512 Bytes data RAM per core

• PRU Subsystem (PRUSS) can be disabled via software to save power

– Standard power management mechanism

• Clock gating

• Entire subsystem under a single PSC clock gating domain

– Dedicated interrupt controller – Dedicated switched central resource

• Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)

• Two Master/Slave Inter-Integrated Circuit (I2C

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2ARM926EJ-S, EmbeddedICE-RT, ETM9, CoreSight are trademarks of ARM Limited. 3ARM, Jazelle are registered trademarks of ARM Limited.

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Bus™) Timers)

• One Host-Port Interface (HPI) With 16-Bit-Wide • Three Enhanced Pulse Width Modulators Muxed Address/Data Bus For High Bandwidth (eHRPWM):

• USB 1.1 OHCI (Host) With Integrated PHY – Dedicated 16-Bit Time-Base Counter With (USB1) Period And Frequency Control

• USB 2.0 OTG Port With Integrated PHY (USB0) – 6 Single Edge, 6 Dual Edge Symmetric or 3 – USB 2.0 High-/Full-Speed Client – USB 2.0 High-/Full-/Low-Speed Host – End Point 0 (Control) – End Points 1,2,3,4 (Control, Bulk, Interrupt or

Dual Edge Asymmetric Outputs – Dead-Band Generation – PWM Chopping by High-Frequency Carrier – Trip Zone Input

ISOC) Rx and Tx • Three 32-Bit Enhanced Capture Modules

• Three Multichannel Audio Serial Ports: – Six Clock Zones and 28 Serial Data Pins – Supports TDM, I2S, and Similar Formats – DIT-Capable (McASP2) – FIFO buffers for Transmit and Receive

• 10/100 Mb/s Ethernet MAC (EMAC): – IEEE 802.3 Compliant (3.3-V I/O Only) – RMII Media Independent Interface – Management Data I/O (MDIO) Module

• Real-Time Clock With 32 KHz Oscillator and Separate Power Rail

• One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)

• One 64-bit General-Purpose/Watchdog Timer (Configurable as Two 32-bit General-Purpose

(eCAP): – Configurable as 3 Capture Inputs or 3

Auxiliary Pulse Width Modulator (APWM) outputs

– Single Shot Capture of up to Four Event

Time-Stamps

• Two 32-Bit Enhanced Quadrature Encoder Pulse Modules (eQEP)

• 256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch

• Commercial, Industrial, Automotive or Extended Temperature

• Community Resources – TI E2E Community – TI Embedded Processors Wiki

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1.2 Trademarks

All trademarks are the property of their respective owners.

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1.3 Description

The device is a low-power ARM microprocessor based on an ARM926EJ-S™. The device enables OEMs and ODMs to quickly bring to market devices featuring robust operating

systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core has a coprocessor 15 (CP15), protection module, and Data and program Memory Management Units (MMUs) with table look-aside buffers. It has separate 16K-byte instruction and 16K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also has a 8KB RAM (Vector Table) and 64KB ROM.

The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; two inter-integrated circuit (I2C) Bus interfaces; 3 multichannel audio serial port (McASP) with 16/12/4 serializers and FIFO buffers; 2 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host port interface (HPI) ; up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UART interfaces (one with RTS and CTS); 3 enhanced high-resolution pulse width modulator (eHRPWM) peripherals; 3 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; 2 32-bit enhanced quadrature pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.

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The Ethernet Media Access Controller (EMAC) provides an efficient interface between the device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode. Additionally an Management Data Input/Output (MDIO) interface is available for PHY configuration.

The HPI, I2C, SPI, USB1.1 and USB2.0 ports allow the device to easily control peripheral devices and/or communicate with host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the ARM. These include C compilers and a Windows™ debugger interface for visibility into source code execution.

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Switched Central Resource (SCR)

16 KB

I-Cache

16 KB

D-Cache

4 KB ETB

ARM926EJ-S CPU

With MMU

ARM Subsystem

JTAG Interface

System Control

Input

Clock(s)

64 KB ROM

8 KB RAM

(Vector Table)

Power/Sleep

Controller

Multiplexing

RTC/

32-KHz

OSC

PLL/Clock Generator

w/OSC

GeneralPurpose

Timer

GeneralPurpose

Timer

(Watchdog)

Serial Interfaces

I C

(2)

SPI

(2)

UART

(3)

Audio Ports

McASP w/FIFO

(3)

DMA

Peripherals

Display

Internal Memory

LCD

Ctlr

128 KB

RAM

External Memory Interfaces

Connectivity

EDMA3

Control Timers

eHRPWM

(3)

eCAP

(3)

eQEP

(2)

(10/100)

EMAC

(RMII)

MDIO

USB1.1

OHCI Ctlr

PHY

USB2.0

OTG Ctlr

PHY

HPI

MMC/SD

(8b)

EMIFA(8b/16B)

NAND/Flash 16b SDRAM

EMIFB

SDRAM Only

(16b/32b)

GPIO

Customizable Interface

PRU

Subsystem

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1.4 Functional Block Diagram

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1 AM1707 ARM Microprocessor ........................ 1

1.1 Features .............................................. 1 6.11 External Memory Interface A (EMIFA) ............. 66

1.2 Trademarks .......................................... 3

1.3 Description ........................................... 4

1.4 Functional Block Diagram ............................ 5

2 Revision History ......................................... 7

3 Device Overview ........................................ 8

3.1 Device Characteristics ............................... 8

3.2 Device Compatibility ................................. 9

3.3 ARM Subsystem ..................................... 9

3.4 Memory Map Summary ............................. 12

3.5 Pin Assignments .................................... 15

3.6 Terminal Functions ................................. 16

4 Device Configuration ................................. 34

4.1 Boot Modes ......................................... 34

4.2 SYSCFG Module ................................... 35

4.3 Pullup/Pulldown Resistors .......................... 37

5 Device Operating Conditions ....................... 38

5.1 Absolute Maximum Ratings Over Operating Junction Temperature Range

(Unless Otherwise Noted) ................................. 38

5.2 Recommended Operating Conditions .............. 39

5.3 Notes on Recommended Power-On Hours (POH)

...................................................... 40

5.4 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction

Temperature (Unless Otherwise Noted) ............ 41

6 Peripheral Information and Electrical

Specifications .......................................... 42

6.1 Parameter Information .............................. 42

6.2 Recommended Clock and Control Signal Transition

Behavior ............................................ 43

6.3 Power Supplies ..................................... 43

6.4 Unused USB0 (USB2.0) and USB1 (USB1.1) Pin

Configurations ...................................... 43

6.5 Reset ............................................... 45

6.6 Crystal Oscillator or External Clock Input .......... 48

6.7 Clock PLLs ......................................... 50

6.8 Interrupts ............................................ 54

6.9 General-Purpose Input/Output (GPIO) ............. 58

6.10 EDMA ............................................... 61

6.12 External Memory Interface B (EMIFB) ............. 75

6.13 Memory Protection Units ........................... 82

6.14 MMC / SD / SDIO (MMCSD) ....................... 85

6.15 Ethernet Media Access Controller (EMAC) ......... 88

6.16 Management Data Input/Output (MDIO) ........... 93

6.17 Multichannel Audio Serial Ports (McASP0, McASP1,

and McASP2) ....................................... 95

6.18 Serial Peripheral Interface Ports (SPI0, SPI1) .... 108

6.19 Enhanced Capture (eCAP) Peripheral ............ 126

6.20 Enhanced Quadrature Encoder (eQEP) Peripheral

..................................................... 129

6.21 Enhanced High-Resolution Pulse-Width Modulator

(eHRPWM) ........................................ 131

6.22 LCD Controller .................................... 135

6.23 Timers ............................................. 150

6.24 Inter-Integrated Circuit Serial Ports (I2C0, I2C1)

..................................................... 152

6.25 Universal Asynchronous Receiver/Transmitter

(UART) ............................................ 157

6.26 USB1 Host Controller Registers (USB1.1 OHCI)

..................................................... 159

6.27 USB0 OTG (USB2.0 OTG) ........................ 161

6.28 Host-Port Interface (UHPI) ........................ 169

6.29 Power and Sleep Controller (PSC) ................ 176

6.30 Programmable Real-Time Unit Subsystem (PRUSS)

..................................................... 179

6.31 Emulation Logic ................................... 182

6.32 IEEE 1149.1 JTAG ................................ 188

6.33 Real Time Clock (RTC) ........................... 190

7 Device and Documentation Support ............. 193

7.1 Device Support .................................... 193

7.2 Documentation Support ........................... 193

8 Mechanical Packaging and Orderable

Information ............................................ 194

8.1 Device and Development-Support Tool

Nomenclature ..................................... 194

8.2 Packaging Materials Information .................. 194

8.3 Thermal Data for ZKB ............................. 195

8.4 Mechanical Drawings ............................. 195

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2 Revision History

This data manual revision history highlights the changes made to the SPRS637A device-specific data manual to make it an SPRS637B revision.

Table 2-1. Revision History

ADDITIONS/MODIFICATIONS/DELETIONS

Global - Changed SPI td(SCSL_SPC)S min from P to 2P Global - Replaced all "CLKIN" references with "OSCIN" Global - Updated SPI Electrical parameters

Added Section 5.3, Notes on Recommended Power-On Hours (POH).

Section 6.5- Updated "All pins are tri-stated with the exception of RESETOUT which remains active through the reset sequence" to " All

pins are tri-stated with the exception of RESETOUT, which remains active through the reset sequence, and RTCK/GP7[14]. If an emulator is driving TCK into the device during reset, then RTCK/GP7[14] will drive out RTCK. If TCK is not being driven into the device during reset, then RTCK/GP7[14] will drive low."

Updated Warm Reset Timing Diagram - Figure 6-5 Updated the PLL diagram - Figure 6-9

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3 Device Overview

3.1 Device Characteristics

Table 3-1 provides an overview of the device . The table shows significant features of the device, including

the capacity of on-chip RAM, peripherals, and the package type with pin count.

Table 3-1. Characteristics of the device

HARDWARE FEATURES AM1707

EMIFB 16/32bit, upto 512Mb SDRAM EMIFA Asynchronous (8/16-bit bus width) RAM, Flash, 16bit upto 128Mb SDRAM, NOR, NAND Flash Card Interface MMC and SD cards supported. EDMA3 32 independent channels, 8 QDMA channels, 2 Transfer controllers

Timers UART 3 (one with RTS and CTS flow control)

SPI 2 (Each with one hardware chip select) I2C 2 (both Master/Slave)

Peripherals Not all peripherals pins

are available at the same time (for more detail, see the Device Configurations section).

On-Chip Memory

JTAG BSDL_ID DEVIDR0 register CPU Frequency MHz ARM926 375 MHz (1.2V) or 456 MHz (1.3V)

Voltage

Package 17 mm x 17 mm, 256-Ball 1 mm pitch, PBGA (ZKB)

Product Status

(1) ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and

other specifications are subject to change without notice.

(1)

Multichannel Audio Serial Port [McASP]

10/100 Ethernet MAC with Management Data 1 (RMII Interface) I/O

eHRPWM 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs eCAP 3 32-bit capture inputs or 3 32-bit auxiliary PWM outputs eQEP 2 32-bit QEP channels with 4 inputs/channel UHPI 1 (16-bit multiplexed address/data) USB 2.0 (USB0) High-Speed OTG Controller with on-chip OTG PHY USB 1.1 (USB1) Full-Speed OHCI (as host) with on-chip PHY General-Purpose

Input/Output Port PRU Subsystem

(PRUSS) LCD Controller 1 Size (Bytes) 168KB RAM, 64KB ROM

Organization

Core (V) I/O (V) 3.3 V

Product Preview (PP), Advance Information (AI), or Production Data (PD)

2 64-Bit General Purpose (configurable as 2 separate 32-bit timers, 1 configurable as

Watch Dog)

3 (each with transmit/receive, FIFO buffer, 16/12/4 serializers)

8 banks of 16-bit

2 Programmable PRU Cores

ARM

16KB I-Cache

16KB D-Cache

8KB RAM (Vector Table)

64KB ROM

ADDITIONAL MEMORY

128KB RAM

0x8B7D F02F (Silicon Revision 1.1) 0x9B7D F02F (Silicon Revision 2.0)

1.2 V nominal for 375 MHz version

1.3 V nominal for 456 MHz version

375 MHz Versions -PD

456 MHz Version - AI

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3.2 Device Compatibility

The ARM926EJ-S RISC CPU is compatible with other ARM9 CPUs from ARM Holdings plc.

3.3 ARM Subsystem

The ARM Subsystem includes the following features:

• ARM926EJ-S RISC processor

• ARMv5TEJ (32/16-bit) instruction set

• Little endian

• System Control Co-Processor 15 (CP15)

• MMU

• 16KB Instruction cache

• 16KB Data cache

• Write Buffer

• Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)

• ARM Interrupt controller

3.3.1 ARM926EJ-S RISC CPU

The ARM Subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications where full memory management, high performance, low die size, and low power are all important. The ARM926EJ-S processor supports the 32-bit ARM and 16 bit THUMB instruction sets, enabling the user to trade off between high performance and high code density. Specifically, the ARM926EJ-S processor supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes, providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code overhead.

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The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a complete high performance subsystem, including:

• ARM926EJ -S integer core

• CP15 system control coprocessor

• Memory Management Unit (MMU)

• Separate instruction and data caches

• Write buffer

• Separate instruction and data (internal RAM) interfaces

• Separate instruction and data AHB bus interfaces

• Embedded Trace Module and Embedded Trace Buffer (ETM/ETB) For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available

at http://www.arm.com

3.3.2 CP15

The ARM926EJ-S system control coprocessor (CP15) is used to configure and control instruction and data caches, Memory Management Unit (MMU), and other ARM subsystem functions. The CP15 registers are programmed using the MRC and MCR ARM instructions, when the ARM in a privileged mode such as supervisor or system mode.

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3.3.3 MMU

A single set of two level page tables stored in main memory is used to control the address translation, permission checks and memory region attributes for both data and instruction accesses. The MMU uses a single unified Translation Lookaside Buffer (TLB) to cache the information held in the page tables. The MMU features are:

• Standard ARM architecture v4 and v5 MMU mapping sizes, domains and access protection scheme.

• Mapping sizes are: – 1MB (sections) – 64KB (large pages) – 4KB (small pages) – 1KB (tiny pages)

• Access permissions for large pages and small pages can be specified separately for each quarter of the page (subpage permissions)

• Hardware page table walks

• Invalidate entire TLB, using CP15 register 8

• Invalidate TLB entry, selected by MVA, using CP15 register 8

• Lockdown of TLB entries, using CP15 register 10

3.3.4 Caches and Write Buffer

The size of the Instruction cache is 16KB, Data cache is 16KB. Additionally, the caches have the following features:

• Virtual index, virtual tag, and addressed using the Modified Virtual Address (MVA)

• Four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with two dirty bits in the Dcache

• Dcache supports write-through and write-back (or copy back) cache operation, selected by memory region using the C and B bits in the MMU translation tables

• Critical-word first cache refilling

• Cache lockdown registers enable control over which cache ways are used for allocation on a line fill, providing a mechanism for both lockdown, and controlling cache corruption

• Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the TAG RAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the possibility of TLB misses related to the write-back address.

• Cache maintenance operations provide efficient invalidation of, the entire Dcache or Icache, regions of the Dcache or Icache, and regions of virtual memory.

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The write buffer is used for all writes to a noncachable bufferable region, write-through region and write misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for cache line evictions or cleaning of dirty cache lines. The main write buffer has 16-word data buffer and a four-address buffer. The Dcache write-back has eight data word entries and a single address entry.

3.3.5 Advanced High-Performance Bus (AHB)

The ARM Subsystem uses the AHB port of the ARM926EJ-S to connect the ARM to the Config bus and the external memories. Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB by the Config Bus and the external memories bus.

3.3.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)

To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an Embedded Trace Macrocell (ETM). The ARM926EJ-S Subsystem in the device also includes the Embedded Trace Buffer (ETB). The ETM consists of two parts:

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• Trace Port provides real-time trace capability for the ARM9.

• Triggering facilities provide trigger resources, which include address and data comparators, counter, and sequencers.

The device trace port is not pinned out and is instead only connected to the Embedded Trace Buffer. The ETB has a 4KB buffer memory. ETB enabled debug tools are required to read/interpret the captured trace data.

This device uses ETM9™ version r2p2 and ETB version r0p1. Documentation on the ETM and ETB is available from ARM Ltd. Reference the ' CoreSight™ ETM9™ Technical Reference Manual, revision r0p1' and the 'ETM9 Technical Reference Manual, revision r2p2'.

3.3.7 ARM Memory Mapping

By default the ARM has access to most on and off chip memory areas, EMIFA, EMIFB, and the additional 128K byte on chip SRAM. Likewise almost all of the on chip peripherals are accessible to the ARM by default.

See Table 3-2 for a detailed top level device memory map that includes the ARM memory space.

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3.4 Memory Map Summary

Table 3-2. AM1707 Top Level Memory Map

Start Address End Address Size ARM Mem Map EDMA Mem PRUSS Mem Master LCDC

0x0000 0000 0x0000 0FFF 4K - PRUSS Local

0x0000 1000 0x01BB FFFF

0x01BC 0000 0x01BC 0FFF 4K ARM ETB -

memory 0x01BC 1000 0x01BC 17FF 2K ARM ETB reg 0x01BC 1800 0x01BC 18FF 256 ARM Ice -

Crusher 0x01BC 1900 0x01BF FFFF 0x01C0 0000 0x01C0 7FFF 32K EDMA3 Channel Controller 0x01C0 8000 0x01C0 83FF 1024 EDMA3 Transfer Controller 0 0x01C0 8400 0x01C0 87FF 1024 EDMA3 Transfer Controller 1 0x01C0 8800 0x01C0 FFFF 0x01C1 0000 0x01C1 0FFF 4K PSC 0 0x01C1 1000 0x01C1 1FFF 4K PLL Controller 0x01C1 2000 0x01C1 3FFF 0x01C1 4000 0x01C1 4FFF 4K SYSCFG 0x01C1 5000 0x01C1 FFFF 0x01C2 0000 0x01C2 0FFF 4K Timer64P 0 0x01C2 1000 0x01C2 1FFF 4K Timer64P 1 0x01C2 2000 0x01C2 2FFF 4K I2C 0 0x01C2 3000 0x01C2 3FFF 4K RTC 0x01C2 4000 0x01C3 FFFF - 0x01C4 0000 0x01C4 0FFF 4K MMC/SD 0 0x01C4 1000 0x01C4 1FFF 4K SPI 0 0x01C4 2000 0x01C4 2FFF 4K UART 0 0x01C4 3000 0x01CF FFFF 0x01D0 0000 0x01D0 0FFF 4K McASP 0 Control 0x01D0 1000 0x01D0 1FFF 4K McASP 0 AFIFO Control 0x01D0 2000 0x01D0 2FFF 4K McASP 0 Data 0x01D0 3000 0x01D0 3FFF 0x01D0 4000 0x01D0 4FFF 4K McASP 1 Control 0x01D0 5000 0x01D0 5FFF 4K McASP 1 AFIFO Control 0x01D0 6000 0x01D0 6FFF 4K McASP 1 Data 0x01D0 7000 0x01D0 7FFF 0x01D0 8000 0x01D0 8FFF 4K McASP 2 Control 0x01D0 9000 0x01D0 9FFF 4K McASP 2 AFIFO Control 0x01D0 A000 0x01D0 AFFF 4K McASP 2 Data 0x01D0 B000 0x01D0 BFFF 0x01D0 C000 0x01D0 CFFF 4K UART 1 0x01D0 D000 0x01D0 DFFF 4K UART 2 0x01D0 E000 0x01DF FFFF - -

0x01E0 0000 0x01E0 FFFF 64K USB0 0x01E1 0000 0x01E1 0FFF 4K UHPI -

Map Map Peripheral Mem

Mem Map Map

Address

Space

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Table 3-2. AM1707 Top Level Memory Map (continued)

Start Address End Address Size ARM Mem Map EDMA Mem PRUSS Mem Master LCDC

0x01E1 1000 0x01E1 1FFF 0x01E1 2000 0x01E1 2FFF 4K SPI 1 0x01E1 3000 0x01E1 3FFF 4K LCD Controller 0x01E1 4000 0x01E1 4FFF 4K Memory Protection Unit 1 (MPU 1) 0x01E1 5000 0x01E1 5FFF 4K Memory Protection Unit 2 (MPU 2) 0x01E1 6000 0x01E1 FFFF 0x01E2 0000 0x01E2 1FFF 8K EMAC Control Module RAM 0x01E2 2000 0x01E2 2FFF 4K EMAC Control Module Registers 0x01E2 3000 0x01E2 3FFF 4K EMAC Control Registers 0x01E2 4000 0x01E2 4FFF 4K EMAC MDIO port 0x01E2 5000 0x01E2 5FFF 4K USB1 0x01E2 6000 0x01E2 6FFF 4K GPIO 0x01E2 7000 0x01E2 7FFF 4K PSC 1 0x01E2 8000 0x01E2 8FFF 4K I2C 1 0x01E2 9000 0x01EF FFFF 0x01F0 0000 0x01F0 0FFF 4K eHRPWM 0 0x01F0 1000 0x01F0 1FFF 4K HRPWM 0 0x01F0 2000 0x01F0 2FFF 4K eHRPWM 1 0x01F0 3000 0x01F0 3FFF 4K HRPWM 1 0x01F0 4000 0x01F0 4FFF 4K eHRPWM 2 0x01F0 5000 0x01F0 5FFF 4K HRPWM 2 0x01F0 6000 0x01F0 6FFF 4K ECAP 0 0x01F0 7000 0x01F0 7FFF 4K ECAP 1 0x01F0 8000 0x01F0 8FFF 4K ECAP 2 -

0x01F0 9000 0x01F0 9FFF 4K EQEP 0 0x01F0 A000 0x01F0 AFFF 4K EQEP 1 0x01F0 B000 0x3FFF FFFF -

0x4000 0000 0x47FF FFFF 128M EMIFA SDRAM data (CS0) -

0x4800 0000 0x5FFF FFFF

0x6000 0000 0x61FF FFFF 32M EMIFA async data (CS2) -

0x6200 0000 0x63FF FFFF 32M EMIFA async data (CS3) -

0x6400 0000 0x65FF FFFF 32M EMIFA async data (CS4) -

0x6600 0000 0x67FF FFFF 32M EMIFA async data (CS5) -

0x6800 0000 0x6800 7FFF 32K EMIFA Control Registers -

0x6800 8000 0x7FFF FFFF -

0x8000 0000 0x8001 FFFF 128K On-chip RAM -

0x8002 0000 0xAFFF FFFF -

0xB000 0000 0xB000 7FFF 32K EMIFB Control Registers

0xB000 8000 0xBFFF FFFF 0xC000 0000 0xCFFF FFFF 256M EMIFB SDRAM Data 0xD000 0000 0xFFFC FFFF 0xFFFD 0000 0xFFFD FFFF 64K ARM local -

ROM 0xFFFE 0000 0xFFFE DFFF 0xFFFE E000 0xFFFE FFFF 8K ARM Interrupt -

Controller

Map Map Peripheral Mem

Mem Map Map

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Table 3-2. AM1707 Top Level Memory Map (continued)

Start Address End Address Size ARM Mem Map EDMA Mem PRUSS Mem Master LCDC

0xFFFF 0000 0xFFFF 1FFF 8K ARM local - ARM local

RAM RAM (PRU 0

0xFFFF 2000 0xFFFF FFFF -

Map Map Peripheral Mem

Mem Map Map

Only)

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AXR1[0]/

GP4[0]

AXR1[11]/

GP5[11]

SPI0_CLK/

EQEP1I/

GP5[2]/

BOOT[2]

SPI1_CLK/

EQEP1S/

GP5[7]/

BOOT[7]

1 2 3 4 5 6

EMA_CS[3]/

AMUTE2/

GP2[6]

EMA_CS[0] UHPI_HAS//

GP2[4]

EMA_A[0]/ LCD_D[7]/

GP1[0]

EMA_A[4]/ LCD_D[3]/

GP1[4]

EMA_A[8]/

LCD_PCLK/

GP1[8]

EMA_SDCKE/

GP2[0]

EMA_D[0]/

MMCSD_DAT[0]/

UHPI_HD[0]/

GP0[0]/

BOOT[12]

EMA_D[9]/

UHPI_HD[9]/

LCD_D[9]/

GP0[9]

15 16

AXR1[1]/

GP4[1]

UART0_RXD/

I2C0_SDA/

TM64P0_IN12/

GP5[8]/

BOOT[8]

SPI1_ENA/

UART2_RXD/

GP5[12]

SPI0_ENA

UART0_CTS//

EQEP0A/

GP5[3]/

BOOT[3]

SPI0_SOMI[0]/

EQEP0I/

GP5[0]/

BOOT[0]

EMA_OE

UHPI_HDS1//

AXR0[13]/

GP2[7]

EMA_BA[0]/

LCD_D[4]/

GP1[14]

EMA_A[1]/

MMCSD_CLK/

UHPI_HCNTL0/

GP1[1]

EMA_A[5]/ LCD_D[2]/

GP1[5]

EMA_A[9]/

LCD_HSYNC/

GP1[9]

EMA_CLK/

OBSCLK/

AHCLKR2/

GP1[15]

EMA_D[2]/

MMCSD_DAT[2]/

UHPI_HD[2]/

GP0[2]

EMA_D[10]/

UHPI_HD[10]/

LCD_D[10]/

GP0[10]

EMA_D[1]/

MMCSD_DAT[1]/

UHPI_HD[1]/

GP0[1]

AXR1[3]/

EQEP1A/

GP4[3]

AXR1[2]/

GP4[2]

UART0_TXD/

I2C0_SCL/

TM64P0_OUT12/

GP5[9]/

BOOT[9]

SPI1_SCS[0]/ UART2_TXD/

GP5[13]

SPI1_SOMI[0]/

I2C1_SCL/

GP5[5]/

BOOT[5]

SPI0_SIMO[0]/

EQEP0S/

GP5[1]/

BOOT[1]

EMA_CS[2] UHPI_HCS//

GP2[5]/

BOOT[15]

EMA_BA[1]/

LCD_D[5]/

UHPI_HHWIL/

GP1[13]

EMA_A[2]/ MMCSD_CMD/ UHPI_HCNTL1/

GP1[2]

EMA_A[6]/ LCD_D[1]/

GP1[6]

EMA_A[11]/

GP1[11]

LCD_AC_

ENB_CS

EMA_WE_

DQM[1]

UHPI_HDS2//

AXR0[14]/

GP2[8]

EMA_D[4]/

MMCSD_DAT[4]/

UHPI_HD[4]/

GP0[4]

EMA_D[12]/

UHPI_HD[12]/

LCD_D[12]/

GP0[12]

EMA_D[3]/

MMCSD_DAT[3]/

UHPI_HD[3]/

GP0[3]

EMA_D[11]/

UHPI_HD[11]/

LCD_D[11]

GP0[11]

AXR1[5]/

EPWM2B/

GP4[5]

AXR1[4]/

EQEP1B/

GP4[4]

AXR1[10]/

GP5[10]

SPI0_SCS[0] UART0_RTS//

EQEP0B/

GP5[4]/

BOOT[4]

SPI1_SIMO[0]/

I2C1_SDA/

GP5[6]/

BOOT[6]

EMA_WAIT[0]/

GP2[10]

UHPI_HRDY

EMA_RAS/

EMA_CS[5]/

GP2[2]

EMA_A[10]/

LCD_VSYNC/

GP1[10]

EMA_A[3]/ LCD_D[6]/

GP1[3]

EMA_A[7]/ LCD_D[0]/

GP1[7]

EMA_A[12]/ LCD_MCLK/

GP1[12]

EMA_D[8]/

UHPI_HD[8]/

LCD_D[8]/

GP0[8]

EMA_D[6]/

MMCSD_DAT[6]/

UHPI_HD[6]/

GP0[6]

EMA_D[14]/

UHPI_HD[14]/

LCD_D[14]/

GP0[14]

EMA_D[5]/

MMCSD_DAT[5]/

UHPI_HD[5]/

GP0[5]

EMA_D[13]/

UHPI_HD[13]/

LCD_D[13]/

GP0[13]

AXR1[9]/

GP4[9]

AXR1[8]/

EPWM1A/

GP4[8]

AXR1[7]/

EPWM1B/

GP4[7]

AXR1[6]/

EPWM2A/

GP4[6]

EMA_WEW/

UHPI_HR /

AXR0[12]/

GP2[3]/

BOOT[14]]

EMA_WE_

DQM[0]

UHPI_HINT//

AXR0[15]/

GP2[9]

EMA_D[7]/

MMCSD_DAT[7]/

UHPI_HD[7]/

GP0[7]/

BOOT[13]

EMA_D[15]/

UHPI_HD[15]/

LCD_D[15]/

GP0[15]

AHCLKR1/

GP4[11]

ACLKR1/

ECAP2/ APWM2/ GP4[12]

AFSR1/ GP4[13]

AMUTE0/

RESETOUT

DVDDEMB_CAS EMB_D[22] EMB_D[23]

EMA_CAS

EMA_CS[4]//

GP2[1]

RTCK/GP7[14]

AHCLKX1/ EPWM0B/

GP3[14]

ACLKX1/

EPWM0A/

GP3[15]

AFSX1/

EPWMSYNCI/

EPWMSYNCO/

GP4[10]

DVDDEMB_D[20]

EMB_WE_

DQM[0]/ GP5[15]

EMB_WE EMB_D[21]CV

TMS

TDI

TDO TRST

EMU0/GP7[15]

EMB_D[5]/

GP6[5]

EMB_D[19]

EMB_D[6]/

GP6[6]

EMB_D[7]/

GP6[7]

RTC_XI

RTC_XO

TCK

USB0_

VDDA33

EMB_D[3]/

GP6[3]

EMB_D[17] EMB_D[18]

EMB_D[4]/

GP6[4]

RTC_CV

RTC_V

RESET USB0_DM

EMB_D[1]/

GP6[1]

EMB_D[31] EMB_D[16]

EMB_D[2]/

GP6[2]

OSCOUT

OSCIN

NC USB0_DP

RSV1

EMB_D[15]/

GP6[15]

EMB_D[29] EMB_D[30]

EMB_D[0]/

GP6[0]

PLL0_VSSA

OSCVSS

USB0_

VDDA18

USB0_

DRVVBUS/

GP4[15]

EMB_D[13]/

GP6[13]

EMB_D[27] EMB_D[28]

EMB_D[14]/

GP6[14]

PLL0_VDDA

USB0_ID

USB0_VBUS

AMUTE1/

EHRPWMTZ/

GP4[14]

AFSX0/

GP2[13]/

BOOT[10]

UART1_TXD/

AXR0[10]/

GP3[10]

AXR0[6]/

RMII_RXER/

ACLKR2/

GP3[6]

AXR0[2]/

RMII_TXEN/

AXR2[3]/

GP3[2]

EMB_CS[0]

EMB_A[0]/

GP7[2]

EMB_A[4]/

GP7[6]

EMB_A[8]/

GP7[10]

EMB_D[9]/

GP6[9]

EMB_D[10]/

GP6[10]

EMB_D[11]/

GP6[11]

EMB_D[12]/

GP6[12]

USB1_

VDDA33

USB1_

VDDA18

USB0_

VDDA12

AFSR0/

GP3[12]

ACLKX0/

ECAP0/ APWM0/ GP2[12]

UART1_RXD/

AXR0[9]/

GP3[9]

AXR0[5]/

RMII_RXD[1]/

AFSX2/ GP3[5]

AXR0[1]/

RMII_TXD[1]/

ACLKX2/

GP3[1]

EMB_BA[0]/

GP7[1]

EMB_A[1]/

GP7[3]

EMB_A[5]/

GP7[7]

EMB_A[9]/

GP7[11]

EMB_SDCKE EMB_CLK

EMB_WE_

DQM[1]/ GP5[14]

EMB_D[8]/

GP6[8]

RSV2 VSSUSB1_DM

ACLKR0/

ECAP1/ APWM1/ GP2[15]

AHCLKX0/ AHCLKX2/

USB_

REFCLKIN/

GP2[11]

AXR0[8]/ MDIO_D/

GP3[8]

AXR0[4]/

RMII_RXD[0]/

AXR2[1]/

GP3[4]

AXR0[0]/

RMII_TXD[0]/

AFSR2/

GP3[0]

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

EMB_BA[1]/

GP7[0]

EMB_A[2]/

GP7[4]

EMB_A[6]/

GP7[8]

EMB_A[11]/

GP7[13]

EMB_WE_

DQM[2]

EMB_D[25]

EMB_A[12]/

GP3[13]

USB1_DP

AHCLKR0/

RMII_MHZ_

50_CLK/ GP2[14]/

BOOT[11]

AXR0[11]/

AXR2[0]/

GP3[11]

AXR0[7]/

MDIO_CLK/

GP3[7]

AXR0[3]/

RMII_CRS_DV/

AXR2[2]/

GP3[3]

EMB_RAS

EMB_A[10]/

GP7[12]

EMB_A[3]/

GP7[5]

EMB_A[7]/

GP7[9]

EMB_WE_

DQM[3]

EMB_D[24] EMB_D[26] V

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3.5 Pin Assignments

Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings.

3.5.1 Pin Map (Bottom View)

Figure 3-1 shows the pin assignments for the ZKB package.

SPRS637B–FEBRUARY 2010–REVISED AUGUST 2010

Figure 3-1. Pin Map (ZKB)

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3.6 Terminal Functions

Table 3-3 to Table 3-23 identify the external signal names, the associated pin/ball numbers along with the

mechanical package designator, the pin type (I, O, IO, OZ, or PWR), whether the pin/ball has any internal pullup/pulldown resistors, whether the pin/ball is configurable as an IO in GPIO mode, and a functional pin description.

3.6.1 Device Reset and JTAG

Table 3-3. Reset and JTAG Terminal Functions

SIGNAL NAME TYPE

RESET G3 I Device reset input AMUTE0/ RESETOUT L4 O

TMS J1 I IPU JTAG test mode select TDI J2 I IPU JTAG test data input TDO J3 O IPD JTAG test data output TCK H3 I IPU JTAG test clock TRST J4 I IPD JTAG test reset EMU[0]/GP7[15] J5 I/O IPU Emulation Signal RTCK/GP7[14] K1 I/O IPD JTAG Test Clock Return Clock Output

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for

that particular peripheral. (2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor (3) Open drain mode for RESETOUT function.

PIN No.

ZKB

(1)

(3)

(2)

PULL

RESET

IPD Reset output. Multiplexed with McASP0 mute output.

JTAG

DESCRIPTION

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3.6.2 High-Frequency Oscillator and PLL

Table 3-4. High-Frequency Oscillator and PLL Terminal Functions

SIGNAL NAME TYPE

EMA_CLK/OBSCLK/AHCLKR2/ GP1[15]

OSCIN F2 I Oscillator input OSCOUT F1 O Oscillator output OSCVSS E2 GND Oscillator ground

PLL0_VDDA D1 PWR PLL analog VDD(1.2-V filtered supply) PLL0_VSSA E1 GND PLL analog VSS(for filter)

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for

that particular peripheral. (2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

PIN No.

ZKB

R12 O IPU PLL Observation Clock

(1)

PULL

1.2-V OSCILLATOR

(2)

1.2-V PLL

DESCRIPTION

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3.6.3 Real-Time Clock and 32-kHz Oscillator

Table 3-5. Real-Time Clock (RTC) and 1.2-V, 32-kHz Oscillator Terminal Functions

SIGNAL NAME TYPE

RTC_CVDD G1 PWR RTC module core power (isolated from rest of chip CVDD) RTC_XI H1 I Low-frequency (32-kHz) oscillator receiver for real-time clock RTC_XO H2 O Low-frequency (32-kHz) oscillator driver for real-time clock RTC_V

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for

that particular peripheral. (2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

PIN No.

ZKB

G2 GND Oscillator ground (for filter)

(1)

PULL

(2)

DESCRIPTION

3.6.4 External Memory Interface A (ASYNC, SDRAM)

Table 3-6. External Memory Interface A (EMIFA) Terminal Functions

SIGNAL NAME TYPE

EMA_D[15]/UHPI_HD[15]/LCD_D[15]/GP0[15] M16 I/O IPD EMA_D[14]/UHPI_HD[14]/LCD_D[14]/GP0[14] N14 I/O IPD EMA_D[13]/UHPI_HD[13]/LCD_D[13]/GP0[13] N16 I/O IPD EMA_D[12]/UHPI_HD[12]/LCD_D[12]/GP0[12] P14 I/O IPD EMA_D[11]/UHPI_HD[11]/LCD_D[11]/GP0[11] P16 I/O IPD EMA_D[10]/UHPI_HD[10]/LCD_D[10]/GP0[10] R14 I/O IPD EMA_D[9]/UHPI_HD[9]/LCD_D[9]/GP0[9] T14 I/O IPD EMA_D[8]/UHPI_HD[8]/LCD_D[8]/GP0[8] N12 I/O IPD

EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/BOOT[13] M15 I/O IPU EMA_D[6]/MMCSD_DAT[6]/UHPI_HD[6]/GP0[6] N13 I/O IPU

EMA_D[5]/MMCSD_DAT[5]/UHPI_HD[5]/GP0[5] N15 I/O IPU EMA_D[4]/MMCSD_DAT[4]/UHPI_HD[4]/GP0[4] P13 I/O IPU EMA_D[3]/MMCSD_DAT[3]/UHPI_HD[3]/GP0[3] P15 I/O IPU EMA_D[2]/MMCSD_DAT[2]/UHPI_HD[2]/GP0[2] R13 I/O IPU EMA_D[1]/MMCSD_DAT[1]/UHPI_HD[1]/GP0[1] R15 I/O IPU

EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/BOOT[12] T13 I/O IPU

No.

ZKB

(1)

PULL

(2)

MUXED DESCRIPTION

UHPI, LCD, GPIO

MMC/SD, UHPI, GPIO, BOOT

MMC/SD, UHPI, GPIO

MMC/SD, UHPI, GPIO, BOOT

EMIFA data bus

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name

highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured

function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different

types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

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Table 3-6. External Memory Interface A (EMIFA) Terminal Functions (continued)

SIGNAL NAME TYPE

EMA_A[12]/LCD_MCLK/GP1[12] N11 O IPU EMA_A[11]/ LCD_AC_ENB_CS/GP1[11] P11 O IPU EMA_A[10]/LCD_VSYNC/GP1[10] N8 O IPU EMA_A[9]/LCD_HSYNC/GP1[9] R11 O IPU EMA_A[8]/LCD_PCLK/GP1[8] T11 O IPU EMA_A[7]/LCD_D[0]/GP1[7] N10 O IPD EMA_A[6]/LCD_D[1]/GP1[6] P10 O IPD EMA_A[5]/LCD_D[2]/GP1[5] R10 O IPD EMA_A[4]/LCD_D[3]/GP1[4] T10 O IPD EMA_A[3]/LCD_D[6]/GP1[3] N9 O IPD EMA_A[2]/MMCSD_CMD/UHPI_HCNTL1/GP1[2] P9 O IPU EMA_A[1]/MMCSD_CLK/UHPI_HCNTL0/GP1[1] R9 O IPU EMIFA address bus. EMA_A[0]/LCD_D[7]/GP1[0] T9 O IPD LCD, GPIO

EMA_BA[1]/LCD_D[5]/UHPI_HHWIL/GP1[13] P8 O IPU EMA_BA[0]/LCD_D[4]/GP1[14] R8 O IPU LCD, GPIO EMA_CLK/OBSCLK/AHCLKR2/GP1[15] R12 O IPU EMIFA clock

EMA_SDCKE/GP2[0] T12 O IPU GPIO

EMA_RAS /EMA_CS[5]/GP2[2] N7 O IPU

EMA_CAS /EMA_CS[4]/GP2[1] L16 O IPU

EMA_RAS/ EMA_CS[5] /GP2[2] N7 O IPU EMA_CAS/ EMA_CS[4] /GP2[1] L16 O IPU

EMA_CS[3] /AMUTE2/GP2[6] T7 O IPU McASP2, GPIO EMA_CS[2] /UHPI_HCS/GP2[5]/BOOT[15] P7 O IPU

EMA_CS[0] /UHPI_HAS/GP2[4] T8 O IPU UHPI, GPIO

EMA_WE /UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14] M13 O IPU

EMA_WE_DQM[1] /UHPI_HDS2/AXR0[14]/GP2[8] P12 O IPU enable/data mask for

EMA_WE_DQM[0] /UHPI_HINT/AXR0[15]/GP2[9] M14 O IPU enable/data mask for

EMA_OE /UHPI_HDS1/AXR0[13]/GP2[7] R7 O IPU EMIFA output enable

EMA_WAIT[0]/ UHPI_HRDY/GP2[10] N6 I IPU UHPI, GPIO

No.

ZKB

(1)

PULL

(2)

MUXED DESCRIPTION

LCD, GPIO EMIFA address bus

MMCSD, UHPI, GPIO

LCD, UHPI, GPIO

McASP2, GPIO, OBSCLK

EMIF A chip select, GPIO

EMIF A SDRAM, GPIO

UHPI, GPIO, BOOT

UHPI, MCASP0, EMIFA SDRAM write GPIO, BOOT enable

UHPI, McASP, GPIO

UHPI, McASP0, GPIO

EMIFA bank address

EMIFA SDRAM clock enable

EMIFA SDRAM row address strobe

EMIFA SDRAM column address strobe

EMIFA Async Chip Select

EMIFA SDRAM chip select

EMIFA write EMA_D[15:8]

EMIFA write EMA_D[7:0]

EMIFA wait input/interrupt

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3.6.5 External Memory Interface B (SDRAM only)

Table 3-7. External Memory Interface B (EMIFB) Terminal Functions

SIGNAL NAME TYPE

EMB_D[31] G14 O IPD EMB_D[30] F15 O IPD EMB_D[29] F14 O IPD EMB_D[28] E15 O IPD EMB_D[27] E14 O IPD EMB_D[26] A14 O IPD EMB_D[25] B14 O IPD EMB_D[24] A13 O IPD EMB_D[23] L15 O IPD EMB_D[22] L14 O IPD EMB_D[21] K16 O IPD EMB_D[20] K13 O IPD EMB_D[19] J14 O IPD EMB_D[18] H15 O IPD EMB_D[17] H14 O IPD EMB_D[16] G15 O IPD EMB_D[15]/GP6[15] F13 I/O IPD EMB_D[14]/GP6[14] E16 I/O IPD EMB_D[13]/GP6[13] E13 I/O IPD EMB_D[12]/GP6[12] D16 I/O IPD EMB_D[11]/GP6[11] D15 I/O IPD EMB_D[10]/GP6[10] D14 I/O IPD EMB_D[9]/GP6[9] D13 I/O IPD EMB_D[8]/GP6[8] C16 I/O IPD EMB_D[7]/GP6[7] J16 I/O IPD EMB_D[6]/GP6[6] J15 I/O IPD EMB_D[5]/GP6[5] J13 I/O IPD EMB_D[4]/GP6[4] H16 I/O IPD EMB_D[3]/GP6[3] H13 I/O IPD EMB_D[2]/GP6[2] G16 I/O IPD EMB_D[1]/GP6[1] G13 I/O IPD EMB_D[0]/GP6[0] F16 I/O IPD EMB_A[12]/GP3[13] B15 O IPD EMB_A[11]/GP7[13] B12 O IPD EMB_A[10]/GP7[12] A9 O IPD EMB_A[9]/GP7[11] C12 O IPD EMB_A[8]/GP7[10] D12 O IPD EMB_A[7]/GP7[9] A11 O IPD EMB_A[6]/GP7[8] B11 O IPD EMB_A[5]/GP7[7] C11 O IPD

PIN No.

ZKB

(1)

PULL

SPRS637B–FEBRUARY 2010–REVISED AUGUST 2010

(2)

MUXED DESCRIPTION

EMIFB SDRAM data bus

GPIO

EMIFB SDRAM row/column address bus

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name

highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured

function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different

types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

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Table 3-7. External Memory Interface B (EMIFB) Terminal Functions (continued)

SIGNAL NAME TYPE

EMB_A[4]/GP7[6] D11 O IPD EMB_A[3]/GP7[5] A10 O IPD EMB_A[2]/GP7[4] B10 O IPD EMB_A[1]/GP7[3] C10 O IPD GPIO EMB_A[0]/GP7[2] D10 O IPD EMB_BA[1]/GP7[0] B9 O IPU EMB_BA[0]/GP7[1] C9 O IPU EMB_CLK C14 O IPU EMIF SDRAM clock EMB_SDCKE C13 I/O IPU EMIFB SDRAM clock enable EMB_WE K15 O IPU EMIFB write enable

EMB_RAS A8 O IPU EMB_CAS L13 O IPU EMIFB column address strobe

EMB_CS[0] D9 O IPU EMIFB SDRAM chip select 0 EMB_WE_DQM[3] A12 O IPU EMB_WE_DQM[2] B13 O IPU EMB_WE_DQM[1] /GP5[14] C15 O IPU EMB_WE_DQM[0] /GP5[15] K14 O IPU

PIN No.

ZKB

(1)

PULL

(2)

MUXED DESCRIPTION

EMIFB SDRAM row/column address

EMIFB SDRAM bank address

EMIFB SDRAM row address strobe

EMIFB write enable/data mask

GPIO

for EMB_D

3.6.6 Serial Peripheral Interface Modules (SPI0, SPI1)

Table 3-8. Serial Peripheral Interface (SPI) Terminal Functions

SIGNAL NAME TYPE

SPI0_SCS[0] /UART0_RTS/EQEP0B/GP5[4]/BOOT[4] N4 I/O IPU SPI0 chip select

SPI0_ENA /UART0_CTS/EQEP0A/GP5[3]/BOOT[3] R5 I/O IPU SPI0 enable SPI0_CLK/EQEP1I/GP5[2]/BOOT[2] T5 I/O IPD eQEP1, GPIO, BOOT SPI0 clock SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] P6 I/O IPD

SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0] R6 I/O IPD

SPI1_SCS[0] /UART2_TXD/GP5[13] P4 I/O IPU SPI1 chip select SPI1_ENA /UART2_RXD/GP5[12] R4 I/O IPU SPI1 enable SPI1_CLK/EQEP1S/GP5[7]/BOOT[7] T6 I/O IPD eQEP1, GPIO, BOOT SPI1 clock

SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6] N5 I/O IPU

SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5] P5 I/O IPU

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name

highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured

function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different

types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

No.

ZKB

SPI0

SPI1

(1)

PULL

(2)

MUXED DESCRIPTION

UART0, EQEP0B, GPIO, BOOT

UART0, EQEP0A, GPIO, BOOT

eQEP0, GPIO, BOOT

UART2, GPIO

I2C1, GPIO, BOOT

SPI0 data slave-in-master-out

SPI0 data slave-out-master-in

SPI1 data slave-in-master-out

SPI1 data slave-out-master-in

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3.6.7 Enhanced Capture/Auxiliary PWM Modules (eCAP0, eCAP1, eCAP2)

The eCAP Module pins function as either input captures or auxilary PWM 32-bit outputs, depending upon how the eCAP module is programmed.

Table 3-9. Enhanced Capture Module (eCAP) Terminal Functions

SIGNAL NAME TYPE

eCAP0

ACLKX0/ECAP0/APWM0/GP2[12] C5 I/O IPD McASP0, GPIO

eCAP1

ACLKR0/ECAP1/APWM1/GP2[15] B4 I/O IPD McASP0, GPIO

eCAP2

ACLKR1/ECAP2/APWM2/GP4[12] L2 I/O IPD McASP1, GPIO

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name

highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured

function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different

types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

No.

ZKB

(1)

PULL

(2)

MUXED DESCRIPTION

enhanced capture 0 input or auxiliary PWM 0 output

enhanced capture 1 input or auxiliary PWM 1 output

enhanced capture 2 input or auxiliary PWM 2 output

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3.6.8 Enhanced Pulse Width Modulators (eHRPWM0, eHRPWM1, eHRPWM2)

Table 3-10. Enhanced Pulse Width Modulator (eHRPWM) Terminal Functions

SIGNAL NAME TYPE

ACLKX1/EPWM0A/GP3[15] K3 I/O IPD AHCLKX1/EPWM0B/GP3[14] K2 I/O IPD eHRPWM0 B output AMUTE1/EPWMTZ/GP4[14] D4 I/O IPD

AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10] K4 I/O IPD

AXR1[8]/EPWM1A/GP4[8] M2 I/O IPD AXR1[7]/EPWM1B/GP4[7] M3 I/O IPD eHRPWM1 B output AMUTE1/EPWMTZ/GP4[14] D4 I/O IPD

AXR1[6]/EPWM2A/GP4[6] M4 I/O IPD AXR1[5]/EPWM2B/GP4[5] N1 I/O IPD eHRPWM2 B output AMUTE1/EPWMTZ/GP4[14] D4 I/O IPD

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name

highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured

function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different

types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

No.

ZKB

eHRPWM0

eHRPWM1

eHRPWM2

(1)

PULL

(2)

MUXED DESCRIPTION

eHRPWM0 A output

McASP1, GPIO

McASP1, eHRPWM1, eHRPWM0 trip zone GPIO, eHRPWM2 input

McASP1, eHRPWM0, eHRPWM0 module or GPIO sync output to

McASP1, GPIO

McASP1, eHRPWM1, eHRPWM1 trip zone GPIO, eHRPWM2 input

McASP1, GPIO

McASP1, eHRPWM1, eHRPWM2 trip zone GPIO, eHRPWM2 input

(with high-resolution)

Sync input to

external PWM

eHRPWM1 A output (with high-resolution)

eHRPWM2 A output (with high-resolution)

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3.6.9 Enhanced Quadrature Encoder Pulse Module (eQEP)

Table 3-11. Enhanced Quadrature Encoder Pulse Module (eQEP) Terminal Functions

SIGNAL NAME TYPE

SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3] R5 I IPU

SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4] N4 I IPU SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0] R6 I IPD eQEP0 index

SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] P6 I IPD eQEP0 strobe

AXR1[3]/EQEP1A/GP4[3] P1 I IPD

AXR1[4]/EQEP1B/GP4[4] N2 I IPD SPI0_CLK/EQEP1I/GP5[2]/BOOT[2] T5 I IPD eQEP1 index

SPI1_CLK/EQEP1S/GP5[7]/BOOT[7] T6 I IPD eQEP1 strobe

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name

highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured

function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different

types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

No.

ZKB

eQEP0

eQEP1

(1)

PULL

(2)

MUXED DESCRIPTION

SPIO, UART0, GPIO, BOOT

SPI1, GPIO, BOOT

McASP1, GPIO

SPI1, GPIO, BOOT

EQEP0A quadrature input

EQEP0B quadrature input

eQEP1 quadrature input

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3.6.10 Boot

Table 3-12. Boot Mode Selection Terminal Functions

SIGNAL NAME TYPE

EMA_CS[2]/UHPI_HCS/GP2[5]/BOOT[15] P7 I IPU EMIFA, UHPI, GPIO EMA_WE/UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14] M13 I IPU EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/BOOT[13] M15 I IPU

EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/BOOT[12] T13 I IPU AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11] A4 I IPD AFSX0/GP2[13]/BOOT[10] D5 I IPD McASP0, GPIO UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9] P3 I IPU

UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8] R3 I IPU SPI1_CLK/EQEP1S/GP5[7]/BOOT[7] T6 I IPD SPI1, eQEP1, GPIO

SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6] N5 I IPU SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5] P5 I IPU

SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4] N4 I IPU

SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3] R5 I IPU SPI0_CLK/EQEP1I/GP5[2]/BOOT[2] T5 I IPD SPIO, eQEP1, GPIO

SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] P6 I IPD SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0] R6 I IPD

(1) Boot decoding will be defined in the ROM datasheet. (2) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name

highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured

function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different

types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (3) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

PIN No.

ZKB

(2)

PULL

(3)

(1)

MUXED DESCRIPTION

EMIFA, UHPI, McASP0, GPIO

EMIFA, MMC/SD, UHPI, GPIO

McASP0, EMAC, GPIO

UART0, I2C0, Timer0, GPIO

SPI1, I2C1, GPIO

SPI0, UART0, eQEP0, GPIO

SPI0, eQEP0, GPIO

Boot Mode Selection Pins

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3.6.11 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)

Table 3-13. Universal Asynchronous Receiver/Transmitter (UART) Terminal Functions

SIGNAL NAME TYPE

UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8] R3 I IPU UART0 receive data

UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9] P3 O IPU

SPI0_SCS[0]/ UART0_RTS /EQEP0B/GP5[4]/BOOT[4] N4 O IPU

SPI0_ENA/ UART0_CTS /EQEP0A/GP5[3]/BOOT[3] R5 I IPU

UART1_RXD/AXR0[9]/GP3[9] UART1_TXD/AXR0[10]/GP3[10]

SPI1_ENA/UART2_RXD/GP5[12] R4 I IPU UART2 receive data SPI1_SCS[0]/UART2_TXD/GP5[13] P4 O IPU

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name

highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured

function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different

types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor (3) As these signals are internally pulled down while the device is in reset, it is necessary to externally pull them high with resistors if

UART1 boot mode is used.

(3)

No. ZKB UART0

UART1

C6 I IPD UART1 receive data D6 O IPD

UART2

(1)

PULL

(2)

MUXED DESCRIPTION

I2C0, BOOT, Timer0, GPIO,

I2C0, Timer0, GPIO, UART0 transmit BOOT data

UART0

SPIO, eQEP0, GPIO, BOOT

McASP0, GPIO

SPI1, GPIO

ready-to-send output UART0

clear-to-send input

UART1 transmit data

UART2 transmit data

3.6.12 Inter-Integrated Circuit Modules(I2C0, I2C1)

Table 3-14. Inter-Integrated Circuit (I2C) Terminal Functions

SIGNAL NAME TYPE

UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8] R3 I/O IPU I2C0 serial data

UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9] P3 I/O IPU I2C0 serial clock

SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6] N5 I/O IPU I2C1 serial data SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5] P5 I/O IPU I2C1 serial clock

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.

(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

No. ZKB

I2C0

I2C1

(1)

PULL

(2)

MUXED DESCRIPTION

UART0, Timer0, GPIO, BOOT

SPI1, GPIO, BOOT

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3.6.13 Timers

Table 3-15. Timers Terminal Functions

SIGNAL NAME TYPE

UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8] R3 I IPU Timer0 lower input UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9] P3 O IPU

TIMER1 (Watchdog )

No external pins. The Timer1 peripheral signals are not pinned out as external pins.

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

No.

ZKB

TIMER0

(1)

PULL

(2)

UART0, I2C0, GPIO, BOOT

MUXED DESCRIPTION

Timer0 lower output

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3.6.14 Universal Host-Port Interface (UHPI)

Table 3-16. Universal Host-Port Interface (UHPI) Terminal Functions

SIGNAL NAME TYPE

BOOT[13] GPIO, BOOT EMA_D[6]/MMCSD_DAT[6]/UHPI_HD[6]/GP0[6] N13 I/O IPU EMA_D[5]/MMCSD_DAT[5]/UHPI_HD[5]/GP0[5] N15 I/O IPU EMA_D[4]/MMCSD_DAT[4]/UHPI_HD[4]/GP0[4] P13 I/O IPU EMA_D[3]/MMCSD_DAT[3]/UHPI_HD[3]/GP0[3] P15 I/O IPU EMA_D[2]/MMCSD_DAT[2]/UHPI_HD[2]/GP0[2] R13 I/O IPU EMA_D[1]/MMCSD_DAT[1]/UHPI_HD[1]/GP0[1] R15 I/O IPU EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/ EMIFA, MMC/SD,

BOOT[12] GPIO, BOOT EMA_A[2]/MMCSD_CMD/UHPI_HCNTL1/GP1[2] P9 I/O IPU EMIFA,

EMA_A[1]/MMCSD_CLK/UHPI_HCNTL0/GP1[1] R9 I/O IPU

EMA_BA[1]/LCD_D[5]/UHPI_HHWIL/GP1[13] P8 I/O IPU EMIFA, LCD, GPIO

EMA_WE/UHPI_HRW /AXR0[12]/GP2[3]/BOOT[14] M13 I/O IPU UHPI read/write

EMA_CS[2]/ UHPI_HCS /GP2[5]/BOOT[15] P7 I/O IPU UHPI chip select EMA_WE_DQM[1]/ UHPI_HDS2 /AXR0[14]/GP2[8] P12 I/O IPU

EMA_OE/ UHPI_HDS1 /AXR0[13]/GP2[7] R7 I/O IPU EMA_WE_DQM[0]/ UHPI_HINT /AXR0[15]/GP2[9] M14 I/O IPU UHPI host interrupt EMA_WAIT[0]/ UHPI_HRDY /GP2[10] N6 I/O IPU UHPI ready EMA_CS[0]/ UHPI_HAS /GP2[4] T8 I/O IPU UHPI address strobe

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

No.

ZKB

M15 I/O IPU

T13 I/O IPU

(1)

PULL

(2)

MUXED DESCRIPTION

EMIFA, LCD, GPIO

UHPI data bus

EMIFA, MMC/SD, GPIO

MMCSD_CMD, UHPI access control GPIO

UHPI half-word identification control

EMIFA, McASP, GPIO, BOOT

EMIFA, GPIO, BOOT

EMIFA, McASP0, GPIO

EMIFA, GPIO

UHPI data strobe

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3.6.15 Multichannel Audio Serial Ports (McASP0, McASP1, McASP2)

Table 3-17. Multichannel Audio Serial Ports (McASPs) Terminal Functions

SIGNAL NAME TYPE

McASP0

EMA_WE_DQM[0]/UHPI_HINT/AXR0[15]/GP2[9] M14 I/O IPU EMA_WE_DQM[1]/UHPI_HDS2/AXR0[14]/GP2[8] P12 I/O IPU EMA_OE/UHPI_HDS1/AXR0[13]/GP2[7] R7 I/O IPU

EMA_WE/UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14] M13 I/O IPU AXR0[11]/ AXR2[0]/GP3[11] A5 I/O IPD McASP2, GPIO

UART1_TXD/AXR0[10]/GP3[10] D6 I/O IPD GPIO UART1_RXD/AXR0[9]/GP3[9] C6 I/O IPD GPIO

AXR0[8]/MDIO_D/GP3[8] B6 I/O IPU AXR0[7]/MDIO_CLK/GP3[7] A6 I/O IPD AXR0[6]/RMII_RXER/ACLKR2/GP3[6] D7 I/O IPD AXR0[5]/RMII_RXD[1]/AFSX2/GP3[5] C7 I/O IPD AXR0[4]/RMII_RXD[0]/AXR2[1]/GP3[4] B7 I/O IPD AXR0[3]/RMII_CRS_DV/AXR2[2]/GP3[3] A7 I/O IPD AXR0[2]/RMII_TXEN/AXR2[3]/GP3[2] D8 I/O IPD AXR0[1]/RMII_TXD[1]/ACLKX2/GP3[1] C8 I/O IPD AXR0[0]/RMII_TXD[0]/AFSR2/GP3[0] B8 I/O IPD

AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11] B5 I/O IPD

ACLKX0/ECAP0/APWM0/GP2[12] C5 I/O IPD eCAP0, GPIO

AFSX0/GP2[13]/BOOT[10] D5 I/O IPD GPIO, BOOT

AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11] A4 I/O IPD

ACLKR0/ECAP1/APWM1/GP2[15] B4 I/O IPD eCAP1, GPIO

AFSR0/GP3[12] C4 I/O IPD GPIO

AMUTE0/RESETOUT L4 I/O IPD RESETOUT

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

No.

ZKB

(1)

PULL

(2)

MUXED DESCRIPTION

EMIFA, UHPI, GPIO

EMIFA, UHPI, GPIO, BOOT

MDIO, GPIO data

EMAC, McASP2, GPIO

McASP2, USB, McASP1 transmit GPIO master clock

EMAC, GPIO, McASP0 receive BOOT master clock

McASP0 serial

McASP0 transmit bit clock

McASP0 transmit frame sync

McASP0 receive bit clock

McASP0 receive frame sync

McASP0 mute output

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ADVANCEINFORMATION

AM1707

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SPRS637B–FEBRUARY 2010–REVISED AUGUST 2010

Table 3-17. Multichannel Audio Serial Ports (McASPs) Terminal Functions (continued)

SIGNAL NAME TYPE

McASP1

AXR1[11]/GP5[11] T4 I/O IPU AXR1[10]/GP5[10] N3 I/O IPU GPIO AXR1[9]/GP4[9] M1 I/O IPD

AXR1[8]/EPWM1A/GP4[8] M2 I/O IPD

AXR1[7]/EPWM1B/GP4[7] M3 I/O IPD

AXR1[6]/EPWM2A/GP4[6] M4 I/O IPD

AXR1[5]/EPWM2B/GP4[5] N1 I/O IPD AXR1[4]/EQEP1B/GP4[4] N2 I/O IPD

AXR1[3]/EQEP1A/GP4[3] P1 I/O IPD AXR1[2]/GP4[2] P2 I/O IPD AXR1[1]/GP4[1] R2 I/O IPD GPIO AXR1[0]/GP4[0] T3 I/O IPD

AHCLKX1/EPWM0B/GP3[14] K2 I/O IPD

ACLKX1/EPWM0A/GP3[15] K3 I/O IPD

AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10] K4 I/O IPD

AHCLKR1/GP4[11] L1 I/O IPD GPIO

ACLKR1/ECAP2/APWM2/GP4[12] L2 I/O IPD eCAP2, GPIO

AFSR1/GP4[13] L3 I/O IPD GPIO

AMUTE1/EPWMTZ/GP4[14] D4 I/O IPD

McASP2

AXR0[0]/RMII_TXD[0]/AFSR2/GP3[0] B8 I/O IPD AXR0[2]/RMII_TXEN/AXR2[3]/GP3[2] D8 I/O IPD AXR0[3]/RMII_CRS_DV/AXR2[2]/GP3[3] A7 I/O IPD AXR0[4]/RMII_RXD[0]/AXR2[1]/GP3[4] B7 I/O IPD AXR0[11]/AXR2[0]/GP3[11] A5 I/O IPD

AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11] B5 I/O IPD

AXR0[1]/RMII_TXD[1]/ACLKX2/GP3[1] C8 I/O IPD

AXR0[5]/RMII_RXD[1]/AFSX2/GP3[5] C7 I/O IPD

EMA_CLK/OBSCLK/AHCLKR2/GP1[15] R12 I/O IPU

AXR0[6]/RMII_RXER/ACLKR2/GP3[6] D7 I/O IPD

EMA_CS[3]/AMUTE2/GP2[6] T7 I/O IPU EMIFA, GPIO

No.

ZKB

(1)

PULL

(2)

MUXED DESCRIPTION

eHRPWM1 A, GPIO

eHRPWM1 B, GPIO

eHRPWM2 A, GPIO

eHRPWM2 B, GPIO

eQEP1, GPIO

eHRPWM0, McASP1 transmit GPIO master clock

eHRPWM0, McASP1 transmit GPIO bit clock

eHRPWM0, McASP1 transmit GPIO frame sync

eHRPWM0, eHRPWM1, McASP1 mute eHRPWM2, output GPIO

McASP0, McASP2 serial EMAC, GPIO data

McASP0, USB, McASP2 transmit GPIO master clock

McASP0, McASP2 transmit EMAC, GPIO bit clock

McASP0, McASP2 transmit EMAC, GPIO frame sync

EMIFA, GPIO, McASP2 receive OBSCLK master clock

McASP0, McASP2 receive EMAC, GPIO bit clock

McASP1 serial data

McASP1 receive master clock

McASP1 receive bit clock

McASP1 receive frame sync

McASP2 mute output

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ADVANCEINFORMATION

AM1707

SPRS637B–FEBRUARY 2010–REVISED AUGUST 2010

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3.6.16 Universal Serial Bus Modules (USB0, USB1)

Table 3-18. Universal Serial Bus (USB) Terminal Functions

SIGNAL NAME TYPE

USB0_DM G4 A NA USB0 PHY data minus USB0_DP F4 A NA USB0 PHY data plus USB0_VDDA33 H5 PWR NA USB0 PHY 3.3-V supply USB0_VDDA18 E3 PWR NA USB0 PHY 1.8-V supply input USB0_VDDA12 USB0_ID D2 A NA USB0 PHY identification (mini-A or mini-B plug) USB0_VBUS D3 A NA USB0 bus voltage USB0_DRVVBUS/GP4[15] E4 0 IPD GPIO USB0 controller VBUS control output.

AHCLKX0/AHCLKX2/USB_REFCLKIN/ GP2[11]

USB1_DM B3 A NA USB1 PHY data minus USB1_DP A3 A NA USB1 PHY data plus USB1_VDDA33 C1 PWR NA USB1 PHY 3.3-V supply USB1_VDDA18 C2 PWR NA USB1 PHY 1.8-V supply

AHCLKX0/AHCLKX2/USB_REFCLKIN/ GP2[11]

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor (3) Core power supply LDO output for USB PHY. This pin must be connected via a 0.22 uF capacitor to VSS.

(3)

No.

ZKB

C3 PWR NA USB0 PHY 1.2-V LDO output for bypass cap

B5 I IPD USB_REFCLKIN. Optional clock input.

USB1 1.1 OHCI (USB1)

B5 I IPD NA USB_REFCLKIN. Optional clock input.

(1)

USB0 2.0 OTG (USB0)

PULL

(2)

MUXED DESCRIPTION

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