Texas instruments AM1705 ADVANCE INFORMATION

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AM1705 ARM Microprocessor

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1 AM1705 ARM Microprocessor

1.1 Features

123

• Highlights – 375/456-MHz ARM926EJ-S™ RISC Core – ARM9 Memory Architecture – Programmable Real-Time Unit Subsystem – Enhanced Direct-Memory-Access Controller

3 (EDMA3) • Two External Memory Interfaces: – Two External Memory Interfaces – EMIFA – Three Configurable 16550 type UART • NOR (8-Bit-Wide Data)

Modules – Two Serial Peripheral Interfaces (SPI) – Multimedia Card (MMC)/Secure Digital (SD) Space

Card Interface with Secure Data I/O (SDIO) – Two Master/Slave Inter-Integrated Circuit – USB 2.0 OTG Port With Integrated PHY – Two Multichannel Audio Serial Ports – 10/100 Mb/s Ethernet MAC (EMAC) – One 64-Bit General-Purpose Timer UART0 only – One 64-bit General-Purpose/Watchdog Timer • Two Serial Peripheral Interfaces (SPI) Each – Three Enhanced Pulse Width Modulators – Three 32-Bit Enhanced Capture Modules

• Applications – Industrial Automation – Home Automation – Test and Measurement – Portable Data Terminals – Educational Consoles – Power Protection Systems

• 375/456-MHz ARM926EJ-S™ RISC Core – 32-Bit and 16-Bit (Thumb®) Instructions – Single Cycle MAC – ARM®Jazelle®Technology – EmbeddedICE-RT™ for Real-Time Debug

• ARM9 Memory Architecture – 16K-Byte Instruction Cache – 16K-Byte Data Cache – 8K-Byte RAM (Vector Table) – 64K-Byte ROM

• Enhanced Direct-Memory-Access Controller 3 (EDMA3):

– 2 Transfer Controllers

– 32 Independent DMA Channels – 8 Quick DMA Channels – Programmable Transfer Burst Size

• 128K-Byte RAM Memory

• 3.3V LVCMOS IOs (except for USB interface)

– EMIFB

• 16-Bit SDRAM With 256MB Address

• Three Configurable 16550 type UART Modules: – UART0 With Modem Control Signals – 16-byte FIFO – 16x or 13x Oversampling Option – Autoflow control signals (CTS, RTS) on

With One Chip-Select

• Programmable Real-Time Unit Subsystem (PRUSS)

– Two Independent Programmable Realtime

Unit (PRU) Cores

• 32-Bit Load/Store RISC architecture

• 4K Byte instruction RAM per core

• 512 Bytes data RAM per core

• PRU Subsystem (PRUSS) can be disabled via software to save power

– Standard power management mechanism

• Clock gating

• Entire subsystem under a single PSC clock gating domain

– Dedicated interrupt controller – Dedicated switched central resource

• Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)

• Two Master/Slave Inter-Integrated Circuit (I2C Bus™)

• USB 2.0 OTG Port With Integrated PHY (USB0) – USB 2.0 Full-Speed Client – USB 2.0 Full-/Low-Speed Host

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2ARM926EJ-S, EmbeddedICE-RT, ETM9, CoreSight are trademarks of ARM Limited. 3ARM, Jazelle are registered trademarks of ARM Limited.

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– End Point 0 (Control) – 6 Single Edge, 6 Dual Edge Symmetric or 3 – End Points 1,2,3,4 (Control, Bulk, Interrupt or

Dual Edge Asymmetric Outputs

ISOC) Rx and Tx – Dead-Band Generation

• Two Multichannel Audio Serial Ports: – PWM Chopping by High-Frequency Carrier – Six Clock Zones and 28 Serial Data Pins – Trip Zone Input – Supports TDM, I2S, and Similar Formats • Three 32-Bit Enhanced Capture Modules – FIFO buffers for Transmit and Receive

• 10/100 Mb/s Ethernet MAC (EMAC): – IEEE 802.3 Compliant (3.3-V I/O Only) – RMII Media Independent Interface – Management Data I/O (MDIO) Module

• One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)

• One 64-bit General-Purpose/Watchdog Timer (Configurable as Two 32-bit General-Purpose Timers)

• Three Enhanced Pulse Width Modulators (eHRPWM):

– Dedicated 16-Bit Time-Base Counter With

Period And Frequency Control

(eCAP): – Configurable as 3 Capture Inputs or 3

Auxiliary Pulse Width Modulator (APWM) outputs

– Single Shot Capture of up to Four Event

Time-Stamps

• Two 32-Bit Enhanced Quadrature Encoder Pulse Modules (eQEP)

• 176-pin PowerPAD™ Plastic Quad Flat Pack [PTP suffix], 0.5-mm Pin Pitch

• Commercial, Industrial, or Extended Temperature

• Community Resources – TI E2E Community – TI Embedded Processors Wiki

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1.2 Trademarks

All trademarks are the property of their respective owners.

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1.3 Description

The device is a low-power ARM microprocessor based on an ARM926EJ-S™. The device enables OEMs and ODMs to quickly bring to market devices featuring robust operating

systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core has a coprocessor 15 (CP15), protection module, and Data and program Memory Management Units (MMUs) with table look-aside buffers. It has separate 16K-byte instruction and 16K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also has a 8KB RAM (Vector Table) and 64KB ROM.

The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; two inter-integrated circuit (I2C) Bus interfaces; 3 multichannel audio serial port (McASP) with serializers and FIFO buffers; 2 64-bit general-purpose timers each configurable (one configurable as watchdog); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UART interfaces (one with RTS and CTS); 3 enhanced high-resolution pulse width modulator (eHRPWM) peripherals; 3 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; 2 32-bit enhanced quadrature pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.

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The Ethernet Media Access Controller (EMAC) provides an efficient interface between the device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode. Additionally an Management Data Input/Output (MDIO) interface is available for PHY configuration.

TheI2C, SPI, and USB2.0 ports allow the device to easily control peripheral devices and/or communicate with host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the ARM. These include C compilers and a Windows™ debugger interface for visibility into source code execution.

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Switched Central Resource (SCR)

16 KB

I-Cache

16 KB

D-Cache

4 KB ETB

ARM926EJ-S CPU

With MMU

ARM Subsystem

JTAG Interface

System Control

Input

Clock(s)

64 KB ROM

8 KB RAM

(Vector Table)

Power/Sleep

Controller

Multiplexing

PLL/Clock Generator

w/OSC

GeneralPurpose

Timer

GeneralPurpose

Timer

(Watchdog)

Serial Interfaces

I C

(2)

2

SPI

(2)

UART

(3)

Audio Ports

McASP w/FIFO

(2)

DMA

Peripherals

External Memory Interfaces

Connectivity

EDMA3

Control Timers

eHRPWM

(3)

eCAP

(3)

eQEP

(2)

(10/100)

EMAC

(RMII)

MDIO

USB2.0

OTG Ctlr

PHY

MMC/SD

(8b)

EMIFB

SDRAM Only

(16b/32b)

GPIO 128 KB

RAM

Shared Memory

EMIFA

NAND/ Flash

(8b)

PRU

Subsystem

Customizable Interface

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1.4 Functional Block Diagram

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1 AM1705 ARM Microprocessor ........................ 1 6.9 General-Purpose Input/Output (GPIO) ............. 53

1.1 Features .............................................. 1 6.10 EDMA ............................................... 56

1.2 Trademarks .......................................... 3

1.3 Description ........................................... 4

1.4 Functional Block Diagram ............................ 5

2 Revision History ......................................... 7

3 Device Overview ........................................ 8

3.1 Device Characteristics ............................... 8

3.2 Device Compatibility ................................. 9

3.3 ARM Subsystem ..................................... 9

3.4 Memory Map Summary ............................. 12

3.5 Pin Assignments .................................... 14

3.6 Terminal Functions ................................. 15

4 Device Configuration ................................. 30

4.1 Boot Modes ......................................... 30

4.2 SYSCFG Module ................................... 31

4.3 Pullup/Pulldown Resistors .......................... 33

5 Device Operating Conditions ....................... 34

5.1 Absolute Maximum Ratings Over Operating Junction Temperature Range

(Unless Otherwise Noted) ................................. 34

5.2 Recommended Operating Conditions .............. 35

5.3 Notes on Recommended Power-On Hours (POH)

...................................................... 36

5.4 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction

Temperature (Unless Otherwise Noted) ............ 37

6 Peripheral Information and Electrical

Specifications .......................................... 38

6.1 Parameter Information .............................. 38

6.2 Recommended Clock and Control Signal Transition

Behavior ............................................ 39

6.3 Power Supplies ..................................... 39

6.4 Unused USB0 (USB2.0) Pin Configurations ....... 39

6.5 Reset ............................................... 40

6.6 Crystal Oscillator or External Clock Input .......... 43 PowerPAD™ Package ............................ 157

6.7 Clock PLLs ......................................... 45 8.5 Mechanical Drawings ............................. 158

6.8 Interrupts ............................................ 49

6.11 External Memory Interface A (EMIFA) ............. 61

6.12 External Memory Interface B (EMIFB) ............. 67

6.13 Memory Protection Units ........................... 72

6.14 MMC / SD / SDIO (MMCSD) ....................... 75

6.15 Ethernet Media Access Controller (EMAC) ......... 78

6.16 Management Data Input/Output (MDIO) ........... 83

6.17 Multichannel Audio Serial Ports (McASP0,

McASP1) ............................................ 85

6.18 Serial Peripheral Interface Ports (SPI0, SPI1) ..... 96

6.19 Enhanced Capture (eCAP) Peripheral ............ 114

6.20 Enhanced Quadrature Encoder (eQEP) Peripheral

..................................................... 117

6.21 Enhanced High-Resolution Pulse-Width Modulator

(eHRPWM) ........................................ 119

6.22 Timers ............................................. 123

6.23 Inter-Integrated Circuit Serial Ports (I2C0, I2C1)

..................................................... 125

6.24 Universal Asynchronous Receiver/Transmitter

(UART) ............................................ 130

6.25 USB0 OTG (USB2.0 OTG) ........................ 132

6.26 Power and Sleep Controller (PSC) ................ 140

6.27 Programmable Real-Time Unit Subsystem (PRUSS)

..................................................... 143

6.28 Emulation Logic ................................... 146

6.29 IEEE 1149.1 JTAG ................................ 152

7 Device and Documentation Support ............. 154

7.1 Device Support .................................... 154

7.2 Documentation Support ........................... 154

8 Mechanical Packaging and Orderable

Information ............................................ 155

8.1 Device and Development-Support Tool

Nomenclature ..................................... 155

8.2 Packaging Materials Information .................. 155

8.3 Thermal Data for PTP ............................. 157

8.4 Supplementary Information About the 176-pin PTP

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2 Revision History

This data manual revision history highlights the changes made to the SPRS657A device-specific data manual to make it an SPRS657B revision.

Table 2-1. Revision History

ADDITIONS/MODIFICATIONS/DELETIONS

Global - Changed SPI td(SCSL_SPC)S min from P to 2P Global - Replaced all "CLKIN" references with "OSCIN" Global - Updated SPI Electrical parameters Global - Document updated to indicate that the AM1705 does not support high-speed operation on USB0.

Figure 3-1 - Updated muxing on pins 116 and 118.

Added Section 5.3, Notes on Recommended Power-On Hours (POH).

Section 6.5- Updated "All pins are tri-stated with the exception of RESETOUT which remains active through the reset sequence" to " All

pins are tri-stated with the exception of RTCK/GP7[14]. If an emulator is driving TCK into the device during reset, then RTCK/GP7[14] will drive out RTCK. If TCK is not being driven into the device during reset, then RTCK/GP7[14] will drive low."

Updated the PLL diagram - Figure 6-9

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3 Device Overview

3.1 Device Characteristics

Table 3-1 provides an overview of the device . The table shows significant features of the device, including

the capacity of on-chip RAM, peripherals, and the package type with pin count.

Table 3-1. Characteristics of the Device

HARDWARE FEATURES AM1705

EMIFB 16-bit , upto 512Mb SDRAM EMIFA Asynchronous (8/16-bit bus width) RAM, Flash, NOR, NAND Flash Card Interface MMC and SD cards supported. EDMA3 32 independent channels, 8 QDMA channels, 2 Transfer controllers

Timers UART 3 (one with RTS and CTS flow control)

SPI 2 (Each with one hardware chip select) I2C 2 (both Master/Slave) Multichannel Audio

Serial Port [McASP] 10/100 Ethernet MAC

Peripherals I/O Not all peripherals pins

are available at the same time (for more detail, see the Device Configurations section).

On-Chip Memory

JTAG BSDL_ID DEVIDR0 register CPU Frequency MHz ARM926 375 MHz (1.2V) or 456 MHz (1.3V)

Voltage

Package 24 mm x 24 mm, 176-Pin, 0.5 mm pitch, TQFP (PTP)

Product Status

(1) ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and

other specifications are subject to change without notice.

(1)

with Management Data 1 (RMII Interface)

eHRPWM 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs eCAP 3 32-bit capture inputs or 3 32-bit auxiliary PWM outputs eQEP 2 32-bit QEP channels with 4 inputs/channel USB 2.0 (USB0) Full-Speed/Low-Speed OTG Controller with on-chip OTG PHY General-Purpose

Input/Output Port PRU Subsystem

(PRUSS) Size (Bytes) 168KB RAM, 64KB ROM

Organization

Core (V) I/O (V) 3.3 V

Product Preview (PP), Advance Information (AI), or Production Data (PD)

2 64-Bit General Purpose (configurable as 2 separate 32-bit timers, 1 configurable as

Watch Dog)

2(each with transmit/receive, FIFO buffer, 16/12/4 serializers)

8 banks of 16-bit

2 Programmable PRU Cores

ARM

16KB I-Cache

16KB D-Cache

8KB RAM (Vector Table)

64KB ROM

ADDITIONAL MEMORY

128KB RAM

0x8B7D F02F (Silicon Revision 1.1) 0x9B7D F02F (Silicon Revision 2.0)

1.2 V nominal for 375 MHz version

1.3 V nominal for 456 MHz version

375 MHz Versions -PD

456 MHz Version - AI

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3.2 Device Compatibility

The ARM926EJ-S RISC CPU is compatible with other ARM9 CPUs from ARM Holdings plc.

3.3 ARM Subsystem

The ARM Subsystem includes the following features:

• ARM926EJ-S RISC processor

• ARMv5TEJ (32/16-bit) instruction set

• Little endian

• System Control Co-Processor 15 (CP15)

• MMU

• 16KB Instruction cache

• 16KB Data cache

• Write Buffer

• Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)

• ARM Interrupt controller

3.3.1 ARM926EJ-S RISC CPU

The ARM Subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications where full memory management, high performance, low die size, and low power are all important. The ARM926EJ-S processor supports the 32-bit ARM and 16 bit THUMB instruction sets, enabling the user to trade off between high performance and high code density. Specifically, the ARM926EJ-S processor supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes, providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code overhead.

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The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a complete high performance subsystem, including:

• ARM926EJ -S integer core

• CP15 system control coprocessor

• Memory Management Unit (MMU)

• Separate instruction and data caches

• Write buffer

• Separate instruction and data (internal RAM) interfaces

• Separate instruction and data AHB bus interfaces

• Embedded Trace Module and Embedded Trace Buffer (ETM/ETB) For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available

at http://www.arm.com

3.3.2 CP15

The ARM926EJ-S system control coprocessor (CP15) is used to configure and control instruction and data caches, Memory Management Unit (MMU), and other ARM subsystem functions. The CP15 registers are programmed using the MRC and MCR ARM instructions, when the ARM in a privileged mode such as supervisor or system mode.

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3.3.3 MMU

A single set of two level page tables stored in main memory is used to control the address translation, permission checks and memory region attributes for both data and instruction accesses. The MMU uses a single unified Translation Lookaside Buffer (TLB) to cache the information held in the page tables. The MMU features are:

• Standard ARM architecture v4 and v5 MMU mapping sizes, domains and access protection scheme.

• Mapping sizes are: – 1MB (sections) – 64KB (large pages) – 4KB (small pages) – 1KB (tiny pages)

• Access permissions for large pages and small pages can be specified separately for each quarter of the page (subpage permissions)

• Hardware page table walks

• Invalidate entire TLB, using CP15 register 8

• Invalidate TLB entry, selected by MVA, using CP15 register 8

• Lockdown of TLB entries, using CP15 register 10

3.3.4 Caches and Write Buffer

The size of the Instruction cache is 16KB, Data cache is 16KB. Additionally, the caches have the following features:

• Virtual index, virtual tag, and addressed using the Modified Virtual Address (MVA)

• Four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with two dirty bits in the Dcache

• Dcache supports write-through and write-back (or copy back) cache operation, selected by memory region using the C and B bits in the MMU translation tables

• Critical-word first cache refilling

• Cache lockdown registers enable control over which cache ways are used for allocation on a line fill, providing a mechanism for both lockdown, and controlling cache corruption

• Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the TAG RAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the possibility of TLB misses related to the write-back address.

• Cache maintenance operations provide efficient invalidation of, the entire Dcache or Icache, regions of the Dcache or Icache, and regions of virtual memory.

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The write buffer is used for all writes to a noncachable bufferable region, write-through region and write misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for cache line evictions or cleaning of dirty cache lines. The main write buffer has 16-word data buffer and a four-address buffer. The Dcache write-back has eight data word entries and a single address entry.

3.3.5 Advanced High-Performance Bus (AHB)

The ARM Subsystem uses the AHB port of the ARM926EJ-S to connect the ARM to the Config bus and the external memories. Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB by the Config Bus and the external memories bus.

3.3.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)

To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an Embedded Trace Macrocell (ETM). The ARM926EJ-S Subsystem in the device also includes the Embedded Trace Buffer (ETB). The ETM consists of two parts:

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• Trace Port provides real-time trace capability for the ARM9.

• Triggering facilities provide trigger resources, which include address and data comparators, counter, and sequencers.

The device trace port is not pinned out and is instead only connected to the Embedded Trace Buffer. The ETB has a 4KB buffer memory. ETB enabled debug tools are required to read/interpret the captured trace data.

This device uses ETM9™ version r2p2 and ETB version r0p1. Documentation on the ETM and ETB is available from ARM Ltd. Reference the ' CoreSight™ ETM9™ Technical Reference Manual, revision r0p1' and the 'ETM9 Technical Reference Manual, revision r2p2'.

3.3.7 ARM Memory Mapping

By default the ARM has access to most on and off chip memory areas, EMIFA, EMIFB, and the additional 128K byte on chip SRAM. Likewise almost all of the on chip peripherals are accessible to the ARM by default.

See Table 3-2 for a detailed top level device memory map that includes the ARM memory space.

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3.4 Memory Map Summary

Table 3-2. AM1705 Top Level Memory Map

Start Address End Address Size ARM Mem Map EDMA Mem PRUSS Mem Master Peripheral

0x0000 0000 0x0000 0FFF 4K - PRUSS Local

0x0000 1000 0x01BB FFFF 0x01BC 0000 0x01BC 0FFF 4K ARM ETB memory 0x01BC 1000 0x01BC 17FF 2K ARM ETB reg 0x01BC 1800 0x01BC 18FF 256 ARM Ice Crusher 0x01BC 1900 0x01BF FFFF 0x01C0 0000 0x01C0 7FFF 32K EDMA3 Channel Controller 0x01C0 8000 0x01C0 83FF 1024 EDMA3 Transfer Controller 0 0x01C0 8400 0x01C0 87FF 1024 EDMA3 Transfer Controller 1 0x01C0 8800 0x01C0 FFFF 0x01C1 0000 0x01C1 0FFF 4K PSC 0 0x01C1 1000 0x01C1 1FFF 4K PLL Controller 0x01C1 2000 0x01C1 3FFF 0x01C1 4000 0x01C1 4FFF 4K SYSCFG 0x01C1 5000 0x01C1 FFFF 0x01C2 0000 0x01C2 0FFF 4K Timer64P 0 0x01C2 1000 0x01C2 1FFF 4K Timer64P 1 0x01C2 2000 0x01C2 2FFF 4K I2C 0 0x01C2 3000 0x01C2 3FFF 0x01C2 4000 0x01C3 FFFF 0x01C4 0000 0x01C4 0FFF 4K MMC/SD 0 0x01C4 1000 0x01C4 1FFF 4K SPI 0 0x01C4 2000 0x01C4 2FFF 4K UART 0 0x01C4 3000 0x01CF FFFF 0x01D0 0000 0x01D0 0FFF 4K McASP 0 Control 0x01D0 1000 0x01D0 1FFF 4K McASP 0 AFIFO Control 0x01D0 2000 0x01D0 2FFF 4K McASP 0 Data 0x01D0 3000 0x01D0 3FFF 0x01D0 4000 0x01D0 4FFF 4K McASP 1 Control 0x01D0 5000 0x01D0 5FFF 4K McASP 1 AFIFO Control 0x01D0 6000 0x01D0 6FFF 4K McASP 1 Data 0x01D0 7000 0x01D0 BFFF 0x01D0 C000 0x01D0 CFFF 4K UART 1 0x01D0 D000 0x01D0 DFFF 4K UART 2 0x01D0 E000 0x01DF FFFF

0x01E0 0000 0x01E0 FFFF 64K USB0

0x01E1 0000 0x01E1 1FFF -

0x01E1 2000 0x01E1 2FFF 4K SPI 1

0x01E1 3000 0x01E1 3FFF -

0x01E1 4000 0x01E1 4FFF 4K Memory Protection Unit 1 (MPU 1)

0x01E1 5000 0x01E1 5FFF 4K Memory Protection Unit 2 (MPU 2)

0x01E1 6000 0x01E1 FFFF -

0x01E2 0000 0x01E2 1FFF 8K EMAC Control Module RAM

0x01E2 2000 0x01E2 2FFF 4K EMAC Control Module Registers

Map Map Mem Map

Address

Space

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Table 3-2. AM1705 Top Level Memory Map (continued)

Start Address End Address Size ARM Mem Map EDMA Mem PRUSS Mem Master Peripheral

0x01E2 3000 0x01E2 3FFF 4K EMAC Control Registers

0x01E2 4000 0x01E2 4FFF 4K EMAC MDIO port

0x01E2 5000 0x01E2 5FFF -

0x01E2 6000 0x01E2 6FFF 4K GPIO

0x01E2 7000 0x01E2 7FFF 4K PSC 1

0x01E2 8000 0x01E2 8FFF 4K I2C 1

0x01E2 9000 0x01EF FFFF -

0x01F0 0000 0x01F0 0FFF 4K eHRPWM 0

0x01F0 1000 0x01F0 1FFF 4K HRPWM 0

0x01F0 2000 0x01F0 2FFF 4K eHRPWM 1

0x01F0 3000 0x01F0 3FFF 4K HRPWM 1

0x01F0 4000 0x01F0 4FFF 4K eHRPWM 2

0x01F0 5000 0x01F0 5FFF 4K HRPWM 2

0x01F0 6000 0x01F0 6FFF 4K ECAP 0

0x01F0 7000 0x01F0 7FFF 4K ECAP 1

0x01F0 8000 0x01F0 8FFF 4K ECAP 2

0x01F0 9000 0x01F0 9FFF 4K EQEP 0 0x01F0 A000 0x01F0 AFFF 4K EQEP 1 0x01F0 B000 0x5FFF FFFF -

0x6000 0000 0x61FF FFFF 32M EMIFA async data (CS2)

0x6200 0000 0x63FF FFFF 32M EMIFA async data (CS3)

0x6400 0000 0x65FF FFFF 32M EMIFA async data (CS4)

0x6600 0000 0x67FF FFFF 32M EMIFA async data (CS5)

0x6800 0000 0x6800 7FFF 32K EMIFA Control Registers

0x6800 8000 0x7FFF FFFF -

0x8000 0000 0x8001 FFFF 128K On-chip RAM

0x8002 0000 0xAFFF FFFF -

0xB000 0000 0xB000 7FFF 32K EMIFB Control Registers

0xB000 8000 0xBFFF FFFF 0xC000 0000 0xCFFF FFFF 256M EMIFB SDRAM Data 0xD000 0000 0xFFFC FFFF 0xFFFD 0000 0xFFFD FFFF 64K ARM local ROM 0xFFFE 0000 0xFFFE DFFF -

0xFFFE E000 0xFFFE FFFF 8K ARM Interrupt Controller -

0xFFFF 0000 0xFFFF 1FFF 8K ARM local RAM - ARM local -

0xFFFF 2000 0xFFFF FFFF -

Map Map Mem Map

RAM (PRU 0

Only)

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133

RSV2

134

USB0_VDDA12

135

USB0_VDDA18

136

NC

137

USB0_DP

138

USB0_DM

139

NC

140

USB0_VDDA33

141

PLL0_VDDA

142 143

OSCIN

144 145

OSCOUT

146

RESET

147 148

RSV4

149

RSV3

150

RTCK/GP7[14]

152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176

PLL0_VSSA

OSCVSS

CV

DD

TRST

TMS

TDI

TCK TDO

RV

DD

AFSX1/EPWMSYNCI/EPWMSYNC0/GP4[10]

DV

DD

AFSR1/GP4[13]

AXR1[8]/EPWM1A/GP4[8] AXR1[7]/EPWM1B/GP4[7] AXR1[6]/EPWM2A/GP4[6] AXR1[5]/EPWM2B/GP4[5]

1

AXR1[0]/GP4[0]

2

UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8]

3

UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]

4

AXR1[10]/GP5[10]

5

DV

DD

6

AXR1[11]/GP5[11]

7

SPI1_ENA/UART2_RXD/GP5[12]

8

SPI1_SCS[0]/UART2_TXD/GP5[13]

9

SPI0_SCS[0] UART0_RTS/ /EQEP0B/GP5[4]/BOOT[4]

10

11

SPI0_CLK/EQEP1I/GP5[2]/BOOT[2]

12

13

SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5]

14

SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6]

15

16

SPI1_CLK/EQEP1S/GP5[7]/BOOT[7]

17

SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0]

18

19

EMA_WAIT[0]/GP2[10]

2021222324

25

EMA_BA[0]/GP1[14]

262728293031323334353637383940

41

CV

DD

SPI0_ENA UART0_CTS/ /EQEP0A/GP5[3]/BOOT[3]

DV

DD

SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1]

CV

DD

EMA_CS[3]/GP2[6]

EMA_OE/AXR0[13]/GP2[7]

EMA_CS[2]/GP2[5]/BOOT[15]

DV

DD

EMA_BA[1]/GP1[13]

EMA_A[10]/GP1[10]

CV

DD

EMA_A[0]/GP1[0]

EMA_A[1]/MMCSD_CLK/GP1[1]

EMA_A[2]/MMCSD_CMD/GP1[2]

EMA_A[3]/GP1[3]

DV

DD

EMA_A[4]/GP1[4]

EMA_A[5]/GP1[5]

EMA_A[6]/GP1[6]

EMA_A[7]/GP1[7]

CV

DD

EMA_A[8]/GP1[8]

EMA_A[9]/GP1[9]

EMA_A[11]/GP1[11]

EMA_A[12]/GP1[12]

DV

DD

EMA_D[0]/MMCSD_DAT[0]/GP0[0]/BOOT[12]

151

DV

DD

CV

DD

DV

DD

AHCLKX1/EPWM0B/GP3[14]

CV

DD

ACLKX1/EPWM0A/GP3[15]

ACLKR1/ECAP2/APWM2/GP4[12]

CV

DD

DV

DD

AXR1[4]/EQEP1B/GP4[4] AXR1[3]/EQEP1A/GP4[3]

AXR1[2]/GP4[2] AXR1[1]/GP4[1]

42

43

44

88

EMB_SDCKE

87

DV

DD

86

EMB_CLK

85

EMB_WE_DQM[1]/GP5[14]

84

EMB_D[8]/GP6[8]

83

EMB_D[9]/GP6[9]

82

EMB_D[10]/GP6[10]

81

DV

DD

80

EMB_D[11]/GP6[11]

79

EMB_D[12]/GP6[12]

78

EMB_D[13]/GP6[13]

77

CV

DD

76

EMB_D[14]/GP6[14] 75 74

EMB_D[15]/GP6[15] 73

EMB_D[0]/GP6[0] 72

EMB_D[1]/GP6[1] 71

DV

DD

70

EMB_D[2]/GP6[2] 69

CV

DD

68

EMB_D[3]/GP6[3] 67

RV

DD

66

EMB_D[4]/GP6[4] 65

DV

DD

64

EMB_D[5]/GP6[5] 63

EMB_D[6]/GP6[6] 62

EMB_D[7]/GP6[7] 61

CV

DD

60

EMB_WE_DQM[0]/GP5[15] 59

EMB_WE 58

DV

DD

57

EMB_CAS 56

CV

DD

55

EMA_WE/AXR0[12]/GP2[3]/BOOT[14] 54

EMA_D[7]/MMCSD_DAT[7]/GP0[7]/BOOT[13] 53

DV

DD

52

EMA_D[6]/MMCSD_DAT[6]/GP0[6] 51

EMA_D[5]/MMCSD_DAT[5]/GP0[5] 50

CV

DD

49

EMA_D[4]/MMCSD_DAT[4]/GP0[4] 48

EMA_D[3]/MMCSD_DAT[3]/GP0[3] 47

DV

DD

46

EMA_D[2]/MMCSD_DAT[2]/GP0[2] 45

EMA_D[1]/MMCSD_DAT[1]/GP0[1]

DV

DD

132

AMUTE1/EPWMTZ/GP4[14]

131

AFSR0/GP3[12]

130

ACLKR0/ECAP1/APWM1/GP2[15]

129

AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11]

128

DV

DD

127

AFSX0/GP2[13]/BOOT[10]

126

ACLKX0/ECAP0/APWM0/GP2[12]

125

AHCLKX0/USB_REFCLKIN/GP2[11]

124

AXR0[11]/GP3[11]

123

UART1_TXD/AXR0[10]/GP3[10]

122

UART1_RXD/AXR0[9]/GP3[9]

121

AXR0[8]/MDIO_D/GP3[8]

120

AXR0[7]/MDIO_CLK/GP3[7]

119

118

AXR0[6]/RMII_RXER/GP3[6]

117

AXR0[5]/RMII_RXD[1]/GP3[5]

116

AXR0[4]/RMII_RXD[0]/GP3[4]

115

AXR0[3]/RMII_CRS_DV/GP3[3]

114

113

AXR0[2]/RMII_TXEN/GP3[2]

112

AXR0[1]/RMII_TXD[1]/GP3[1]

111

AXR0[0]/RMII_TXD[0]/GP3[0]

110

EMB_RAS

109

DV

DD

108

EMB_CS[0]

107

EMB_BA[0]/GP7[1]

106

EMB_BA[1]/GP7[0]

105

EMB_A[10]/GP7[12]

104

103

EMB_A[0]/GP7[2]

102

EMB_A[1]/GP7[3]

101

EMB_A[2]/GP7[4]

100

EMB_A[3]/GP7[5]

99

98

EMB_A[4]/GP7[6]

97

EMB_A[5]/GP7[7]

96

EMB_A[6]/GP7[8]

95

EMB_A[7]/GP7[9]

94

EMB_A[8]/GP7[10]

93

92

EMB_A[9]/GP7[11]91EMB_A[11]/GP7[13]

90

89

EMB_A[12]/GP3[13]

DV

DD

DV

DD

CV

DD

DV

DD

CV

DD

CV

DD

V

(177)

SS

Thermal Pad

AM1705

SPRS657B–FEBRUARY 2010–REVISED OCTOBER 2010

3.5 Pin Assignments

Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings.

3.5.1 Pin Map (Bottom View)

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Figure 3-1. Pin Map (PTP)

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3.6 Terminal Functions

Table 3-3 to Table 3-20 identify the external signal names, the associated pin/ball numbers along with the

mechanical package designator, the pin type (I, O, IO, OZ, or PWR), whether the pin/ball has any internal pullup/pulldown resistors, whether the pin/ball is configurable as an IO in GPIO mode, and a functional pin description.

3.6.1 Device Reset and JTAG

Table 3-3. Reset and JTAG Terminal Functions

SIGNAL NAME TYPE

RESET 146 I Device reset input

TMS 152 I IPU JTAG test mode select TDI 153 I IPU JTAG test data input TDO 156 O IPD JTAG test data output TCK 155 I IPU JTAG test clock TRST 150 I IPD JTAG test reset RTCK / GP7[14] 157 I/O IPD JTAG Test Clock Return Clock Output

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.

(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

PIN NO

PTP

(1)

PULL

RESET

JTAG

(2)

DESCRIPTION

3.6.2 High-Frequency Oscillator and PLL

Table 3-4. High-Frequency Oscillator and PLL Terminal Functions

SIGNAL NAME TYPE

OSCIN 143 I Oscillator input OSCOUT 145 O Oscillator output OSCVSS 144 GND Oscillator ground

PLL0_VDDA 141 PWR PLL analog VDD(1.2-V filtered supply) PLL0_VSSA 142 GND PLL analog VSS(for filter)

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.

(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

PIN NO

PTP

(1)

PULL

1.2-V OSCILLATOR

1.2-V PLL

(2)

DESCRIPTION

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3.6.3 External Memory Interface A (ASYNC)

Table 3-5. External Memory Interface A (EMIFA) Terminal Functions

SIGNAL NAME TYPE

EMA_D[7]/MMCSD_DAT[7]/GP0[7]/BOOT[13] 54 I/O IPU EMA_D[6]/MMCSD_DAT[6]/GP0[6] 52 I/O IPU

EMA_D[5]/MMCSD_DAT[5]/GP0[5] 51 I/O IPU EMA_D[4]/MMCSD_DAT[4]/GP0[4] 49 I/O IPU EMA_D[3]/MMCSD_DAT[3]/GP0[3] 48 I/O IPU EMA_D[2]/MMCSD_DAT[2]/GP0[2] 46 I/O IPU EMA_D[1]/MMCSD_DAT[1]/GP0[1] 45 I/O IPU

EMA_D[0]/MMCSD_DAT[0]/GP0[0]/BOOT[12] 44 I/O IPU EMA_A[12]/GP1[12] 42 O IPU

EMA_A[11]/ GP1[11] 41 O IPU EMA_A[10]/GP1[10] 27 O IPU EMA_A[9]/GP1[9] 40 O IPU EMA_A[8]/GP1[8] 39 O IPU EMA_A[7]/GP1[7] 37 O IPD EMA_A[6]/GP1[6] 36 O IPD EMA_A[5]/GP1[5] 35 O IPD EMA_A[4]/GP1[4] 34 O IPD EMA_A[3]/GP1[3] 32 O IPD EMA_A[2]/MMCSD_CMD/GP1[2] 31 O IPU EMA_A[1]/MMCSD_CLK/GP1[1] 30 O IPU EMIFA address bus EMA_A[0]/GP1[0] 29 O IPD EMA_BA[1]/GP1[13] 26 O IPU EMA_BA[0]/GP1[14] 25 O IPU GPIO EMA_CS[3] /GP2[6] 21 O IPU GPIO EMA_CS[2]/GP2[5]/BOOT[15] 23 O IPU GPIO, BOOT EMA_OE /AXR0[13]/GP2[7] 22 O IPU McASP0, GPIO EMIFA output enable

EMA_WAIT[0]/ GP2[10] 19 I IPU GPIO

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.

(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

NO

PTP

(1)

PULL

(2)

MUXED DESCRIPTION

MMC/SD, GPIO, BOOT

MMC/SD, GPIO EMIFA data bus

MMC/SD, GPIO, BOOT

GPIO EMIFA address bus

MMCSD, GPIO

GPIO

EMIFA bank address

EMIFA Async Chip Select

EMIFA wait input/interrupt

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3.6.4 External Memory Interface B (only SDRAM )

Table 3-6. External Memory Interface B (EMIFB) Terminal Functions

SIGNAL NAME TYPE

EMB_D[15]/GP6[15] 74 I/O IPD EMB_D[14]/GP6[14] 76 I/O IPD EMB_D[13]/GP6[13] 78 I/O IPD EMB_D[12]/GP6[12] 79 I/O IPD EMB_D[11]/GP6[11] 80 I/O IPD EMB_D[10]/GP6[10] 82 I/O IPD EMB_D[9]/GP6[9] 83 I/O IPD EMB_D[8]/GP6[8] 84 I/O IPD EMB_D[7]/GP6[7] 62 I/O IPD EMB_D[6]/GP6[6] 63 I/O IPD EMB_D[5]/GP6[5] 64 I/O IPD EMB_D[4]/GP6[4] 66 I/O IPD EMB_D[3]/GP6[3] 68 I/O IPD EMB_D[2]/GP6[2] 70 I/O IPD EMB_D[1]/GP6[1] 72 I/O IPD EMB_D[0]/GP6[0] 73 I/O IPD EMB_A[12]/GP3[13] 89 O IPD EMB_A[11]/GP7[13] 91 O IPD EMB_A[10]/GP7[12] 105 O IPD EMB_A[9]/GP7[11] 92 O IPD EMB_A[8]/GP7[10] 94 O IPD EMB_A[7]/GP7[9] 95 O IPD EMB_A[6]/GP7[8] 96 O IPD EMB_A[5]/GP7[7] 97 O IPD EMB_A[4]/GP7[6] 98 O IPD EMB_A[3]/GP7[5] 100 O IPD EMB_A[2]/GP7[4] 101 O IPD EMB_A[1]/GP7[3] 102 O IPD GPIO EMB_A[0]/GP7[2] 103 O IPD EMB_BA[1]/GP7[0] 106 O IPU EMB_BA[0]/GP7[1] 107 O IPU EMB_CLK 86 O IPU EMIF SDRAM clock EMB_SDCKE 88 I/O IPU EMIFB SDRAM clock enable EMB_WE 59 O IPU EMIFB write enable

EMB_RAS 110 O IPU EMB_CAS 57 O IPU EMIFB column address strobe

EMB_CS[0] 108 O IPU EMIFB SDRAM chip select 0 EMB_WE_DQM[1] /GP5[14] 85 O IPU EMB_WE_DQM[0] /GP5[15] 60 O IPU

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.

(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

PIN NO

PTP

(1)

PULL

(2)

MUXED DESCRIPTION

GPIO EMIFB SDRAM data bus

GPIO

EMIFB SDRAM row/column address bus

EMIFB SDRAM row/column address

EMIFB SDRAM bank address

EMIFB SDRAM row address strobe

EMIFB write enable/data mask for EMB_D

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3.6.5 Serial Peripheral Interface Modules (SPI0, SPI1)

Table 3-7. Serial Peripheral Interface (SPI) Terminal Functions

SIGNAL NAME TYPE

SPI0_SCS[0] /UART0_RTS/EQEP0B/GP5[4]/BOOT[4] 9 I/O IPU SPI0 chip select

SPI0_ENA /UART0_CTS/EQEP0A/GP5[3]/BOOT[3] 12 I/O IPU SPI0 enable SPI0_CLK/EQEP1I/GP5[2]/BOOT[2] 11 I/O IPD eQEP1, GPIO, BOOT SPI0 clock SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] 18 I/O IPD

SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0] 17 I/O IPD

SPI1_SCS[0] /UART2_TXD/GP5[13] 8 I/O IPU SPI1 chip select SPI1_ENA /UART2_RXD/GP5[12] 7 I/O IPU SPI1 enable SPI1_CLK/EQEP1S/GP5[7]/BOOT[7] 16 I/O IPD eQEP1, GPIO, BOOT SPI1 clock

SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6] 14 I/O IPU

SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5] 13 I/O IPU

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.

(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

PIN NO

PTP

SPI0

SPI1

(1)

PULL

(2)

MUXED DESCRIPTION

UART0, EQEP0B, GPIO, BOOT

UART0, EQEP0A, GPIO, BOOT

eQEP0, GPIO, BOOT

UART2, GPIO

I2C1, GPIO, BOOT

SPI0 data slave-in-master-out

SPI0 data slave-out-master-in

SPI1 data slave-in-master-out

SPI1 data slave-out-master-in

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3.6.6 Enhanced Capture/Auxiliary PWM Modules (eCAP0, eCAP1, eCAP2)

The eCAP Module pins function as either input captures or auxiliary PWM 32-bit outputs, depending upon how the eCAP module is programmed.

Table 3-8. Enhanced Capture Module (eCAP) Terminal Functions

SIGNAL NAME TYPE

ACLKX0/ECAP0/APWM0/GP2[12] 126 I/O IPD McASP0, GPIO input or auxiliary

ACLKR0/ECAP1/APWM1/GP2[15] 130 I/O IPD McASP0, GPIO input or auxiliary

ACLKR1/ECAP2/APWM2/GP4[12] 165 I/O IPD McASP1, GPIO input or auxiliary

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.

(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

PIN NO

PTP

eCAP0

eCAP1

eCAP2

(1)

PULL

(2)

MUXED DESCRIPTION

enhanced capture 0 PWM 0 output

enhanced capture 1 PWM 1 output

enhanced capture 2 PWM 2 output

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3.6.7 Enhanced Pulse Width Modulators (eHRPWM0, eHRPWM1, eHRPWM2)

Table 3-9. Enhanced Pulse Width Modulator (eHRPWM) Terminal Functions

SIGNAL NAME TYPE

ACLKX1/EPWM0A/GP3[15] 162 I/O IPD (with

AHCLKX1/EPWM0B/GP3[14] 160 I/O IPD eHRPWM0 B output

AMUTE1/EPWMTZ/GP4[14] 132 I/O IPD eHRPWM1, GPIO,

AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10] 163 I/O IPD

AXR1[8]/EPWM1A/GP4[8] 168 I/O IPD AXR1[7]/EPWM1B/GP4[7] 169 I/O IPD eHRPWM1 B output

AMUTE1/EPWMTZ/GP4[14] 132 I/O IPD eHRPWM0, GPIO,

AXR1[6]/EPWM2A/GP4[6] 170 I/O IPD AXR1[5]/EPWM2B/GP4[5] 171 I/O IPD eHRPWM2 B output

AMUTE1/EPWMTZ/GP4[14] 132 I/O IPD eHRPWM0, GPIO,

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.

(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

PIN NO

PTP

eHRPWM0

eHRPWM1

eHRPWM2

(1)

PULL

(2)

MUXED DESCRIPTION

eHRPWM0 A output

McASP1, GPIO

McASP1, eHRPWM2

McASP1, eHRPWM0 module eHRPWM0, GPIO or sync output to

McASP1, GPIO

McASP1, eHRPWM2

McASP1, GPIO

McASP1, eHRPWM2

high-resolution)

eHRPWM0 trip zone input

Sync input to

external PWM

eHRPWM1 A (with high-resolution)

eHRPWM1 trip zone input

eHRPWM2 A (with high-resolution)

eHRPWM2 trip zone input

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3.6.8 Enhanced Quadrature Encoder Pulse Module (eQEP)

Table 3-10. Enhanced Quadrature Encoder Pulse Module (eQEP) Terminal Functions

SIGNAL NAME TYPE

SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3] 12 I IPU

SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4] 9 I IPU SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0] 17 I IPD eQEP0 index

SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] 18 I IPD eQEP0 strobe

AXR1[3]/EQEP1A/GP4[3] 174 I IPD

AXR1[4]/EQEP1B/GP4[4] 173 I IPD SPI0_CLK/EQEP1I/GP5[2]/BOOT[2] 11 I IPD SPI0, GPIO, BOOT eQEP1 index

SPI1_CLK/EQEP1S/GP5[7]/BOOT[7] 16 I IPD SPI1, GPIO, BOOT eQEP1 strobe

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.

(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

PIN NO

PTP

eQEP0

eQEP1

(1)

PULL

(2)

MUXED DESCRIPTION

SPIO, UART0, GPIO, BOOT

SPI0, GPIO, BOOT

McASP1, GPIO

eQEP0A quadrature input

eQEP0B quadrature input

eQEP1A quadrature input

eQEP1B quadrature input

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3.6.9 Boot

PULL

(1)

(3)

MUXED DESCRIPTION

EMIFA, McASP0, GPIO

EMIFA, MMC/SD, GPIO

McASP0, EMAC, GPIO

UART0, I2C0, Timer0, GPIO

SPI1, I2C1, GPIO

SPI0, UART0, eQEP0, GPIO

SPI0, eQEP0, GPIO

Boot Selection Signals

Table 3-11. Boot Terminal Functions

SIGNAL NAME TYPE

EMA_CS[2]/GP2[5]/BOOT[15] 23 I IPU EMIFA, GPIO EMA_WE/AXR0[12]/GP2[3]/BOOT[14] 55 I IPU EMA_D[7]/MMCSD_DAT[7]/GP0[7]/BOOT[13] 54 I IPU

EMA_D[0]/MMCSD_DAT[0]/GP0[0]/BOOT[12] 44 I IPU AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11] 129 I IPD AFSX0/GP2[13]/BOOT[10] 127 I IPD McASP0, GPIO UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9] 3 I IPU

UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8] 2 I IPU SPI1_CLK/EQEP1S/GP5[7]/BOOT[7] 16 I IPD SPI1, eQEP1, GPIO

SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6] 14 I IPU SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5] 13 I IPU

SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4] 9 I IPU

SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3] 12 I IPU SPI0_CLK/EQEP1I/GP5[2]/BOOT[2] 11 I IPD SPIO, eQEP1, GPIO

SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] 18 I IPD SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0] 17 I IPD

(1) Boot decoding will be defined in the ROM datasheet. (2) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.

(3) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

PIN NO

PTP

(2)

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3.6.10 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)

Table 3-12. Universal Asynchronous Receiver/Transmitter (UART) Terminal Functions

SIGNAL NAME TYPE

UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8] 2 I IPU

UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9] 3 O IPU

SPI0_SCS[0]/ UART0_RTS /EQEP0B/GP5[4]/BOOT[4] 9 O IPU ready-to-send

SPI0_ENA/ UART0_CTS /EQEP0A/GP5[3]/BOOT[3] 12 I IPU

UART1_RXD/AXR0[9]/GP3[9]

UART1_TXD/AXR0[10]/GP3[10]

SPI1_ENA/UART2_RXD/GP5[12] 7 I IPU

SPI1_SCS[0]/UART2_TXD/GP5[13] 8 O IPU

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different

types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor (3) As these signals are internally pulled down while the device is in reset, it is necessary to externally pull them high with resistors if

UART1 boot mode is used.

(3)

PIN NO

PTP

UART0

UART1

122 I IPD

123 O IPD

UART2

(1)

PULL

(2)

MUXED DESCRIPTION

I2C0, BOOT, UART0 receive Timer0, GPIO, data

I2C0, Timer0, UART0 transmit GPIO, BOOT data

UART0

SPIO, eQEP0, GPIO, BOOT

McASP0, GPIO

SPI1, GPIO

output UART0

clear-to-send input

UART1 receive data

UART1 transmit data

UART2 receive data

UART2 transmit data

3.6.11 Inter-Integrated Circuit Modules(I2C0, I2C1)

Table 3-13. Inter-Integrated Circuit (I2C) Terminal Functions

SIGNAL NAME TYPE

UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8] 2 I/O IPU I2C0 serial data

UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9] 3 I/O IPU I2C0 serial clock

SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6] 14 I/O IPU I2C1 serial data SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5] 13 I/O IPU I2C1 serial clock

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name

highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured

function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different

types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

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PIN NO

PTP

I2C0

I2C1

(1)

PULL

(2)

UART0, Timer0, GPIO, BOOT

SPI1, GPIO, BOOT

MUXED DESCRIPTION

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3.6.12 Timers

Table 3-14. Timers Terminal Functions

SIGNAL NAME TYPE

UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8] 2 I IPU Timer0 lower input UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9] 3 O IPU

No external pins. The Timer1 peripheral pins are not pinned out as external pins.

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name

highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured

function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different

types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

PIN NO

PTP

TIMER0

TIMER1 (Watchdog )

(1)

PULL

(2)

UART0, I2C0, GPIO, BOOT

MUXED DESCRIPTION

Timer0 lower output

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3.6.13 Multichannel Audio Serial Ports (McASP0, McASP1)

Table 3-15. Multichannel Audio Serial Ports (McASPs) Terminal Functions

SIGNAL NAME TYPE

EMA_OE/AXR0[13]/GP2[7] 22 I/O IPU EMIFA, GPIO EMA_WE/AXR0[12]/GP2[3]/BOOT[14] 55 I/O IPU

AXR0[11] / GP3[11] 124 I/O IPD UART1_TXD/AXR0[10]/GP3[10] 123 I/O IPD GPIO

UART1_RXD/AXR0[9]/GP3[9] 122 I/O IPD GPIO

AXR0[8]/MDIO_D/GP3[8] 121 I/O IPU AXR0[7]/MDIO_CLK/GP3[7] 120 I/O IPD AXR0[6]/RMII_RXER/GP3[6] 118 I/O IPD AXR0[5]/RMII_RXD[1]/GP3[5] 117 I/O IPD AXR0[4]/RMII_RXD[0]/GP3[4] 116 I/O IPD AXR0[3]/RMII_CRS_DV/GP3[3] 115 I/O IPD EMAC, GPIO AXR0[2]/RMII_TXEN/GP3[2] 113 I/O IPD AXR0[1]/RMII_TXD[1]/GP3[1] 112 I/O IPD AXR0[0]/RMII_TXD[0]/GP3[0] 111 I/O IPD

AHCLKX0/USB_REFCLKIN/GP2[11] 125 I/O IPD USB, GPIO transmit master

ACLKX0/ECAP0/APWM0/GP2[12] 126 I/O IPD eCAP0, GPIO transmit bit

AFSX0/GP2[13]/BOOT[10] 127 I/O IPD GPIO, BOOT transmit frame

AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11] 129 I/O IPD

ACLKR0/ECAP1/APWM1/GP2[15] 130 I/O IPD eCAP1, GPIO

AFSR0/GP3[12] 131 I/O IPD GPIO

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name

highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured

function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different

types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

PIN NO

PTP

McASP0

(1)

PULL

(2)

MUXED DESCRIPTION

EMIFA, GPIO, BOOT

McASP2, GPIO

MDIO, GPIO

EMAC, GPIO, McASP0 receive BOOT master clock

McASP0 serial data

McASP0 clock

McASP0 sync

McASP0 receive bit clock

McASP0 receive frame sync

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Table 3-15. Multichannel Audio Serial Ports (McASPs) Terminal Functions (continued)

SIGNAL NAME TYPE

AXR1[11]/GP5[11] 6 I/O IPU AXR1[10]/GP5[10] 4 I/O IPU

AXR1[8]/EPWM1A/GP4[8] 168 I/O IPD

AXR1[7]/EPWM1B/GP4[7] 169 I/O IPD

AXR1[6]/EPWM2A/GP4[6] 170 I/O IPD

AXR1[5]/EPWM2B/GP4[5] 171 I/O IPD AXR1[4]/EQEP1B/GP4[4] 173 I/O IPD

AXR1[3]/EQEP1A/GP4[3] 174 I/O IPD AXR1[2]/GP4[2] 175 I/O IPD AXR1[1]/GP4[1] 176 I/O IPD GPIO AXR1[0]/GP4[0] 1 I/O IPD

AHCLKX1/EPWM0B/GP3[14] 160 I/O IPD transmit master

ACLKX1/EPWM0A/GP3[15] 162 I/O IPD transmit bit

AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10] 163 I/O IPD transmit frame

ACLKR1/ECAP2/APWM2/GP4[12] 165 I/O IPD eCAP2, GPIO

AFSR1/GP4[13] 166 I/O IPD GPIO

AMUTE1/EPWMTZ/GP4[14] 132 O IPD

PIN NO

PTP

McASP1

(1)

PULL

(2)

MUXED DESCRIPTION

GPIO

eHRPWM1 A, GPIO

eHRPWM1 B, GPIO

eHRPWM2 A, GPIO

eHRPWM2 B, GPIO

eQEP, GPIO

eHRPWM0, GPIO

eHRPWM0, eHRPWM1, McASP1 mute eHRPWM2, output GPIO

McASP1 serial data

McASP1 clock

McASP1 sync

McASP1 receive bit clock

McASP1 receive frame sync

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3.6.14 Universal Serial Bus Modules (USB0)

Table 3-16. Universal Serial Bus (USB) Terminal Functions

SIGNAL NAME TYPE

USB0_DM 138 A USB0 PHY data minus USB0_DP 137 A USB0 PHY data plus USB0_VDDA33 140 PWR USB0 PHY 3.3-V supply USB0_VDDA18 135 PWR USB0 PHY 1.8-V supply input USB0_VDDA12

AHCLKX0/USB_REFCLKIN/GP2[11] 125 I IPD USB_REFCLKIN. Optional clock input.

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name

highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured

function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different

types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor (3) Core power supply LDO output for USB PHY. This pin must be connected via a 0.22 uF capacitor to VSS.

(3)

PIN NO

PTP

USB0 2.0 OTG (USB0)

134 PWR USB0 PHY 1.2-V LDO output for bypass cap

(1)

PULL

(2)

DESCRIPTION

3.6.15 Ethernet Media Access Controller (EMAC)

Table 3-17. Ethernet Media Access Controller (EMAC) Terminal Functions

SIGNAL NAME TYPE

AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11] 129 I/O IPD McASP0, GPIO, BOOT clock input or

AXR0[6]/RMII_RXER/GP3[6] 118 I IPD AXR0[5]/RMII_RXD[1]/GP3[5] 117 I IPD

AXR0[4]/RMII_RXD[0]/GP3[4] 116 I IPD AXR0[3]/RMII_CRS_DV/GP3[3] 115 I IPD McASP0, GPIO

AXR0[2]/RMII_TXEN/GP3[2] 113 O IPD AXR0[1]/RMII_TXD[1]/GP3[1] 112 O IPD

AXR0[0]/RMII_TXD[0]/GP3[0] 111 O IPD

AXR0[8]/MDIO_D/GP3[8] 121 I/O IPU AXR0[7]/MDIO_CLK/GP3[7] 120 O IPD

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name

highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured

function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different

types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

PIN NO

PTP

RMII

MDIO

(1)

PULL

(2)

McASP0, GPIO MDIO data clock

MUXED DESCRIPTION

EMAC 50-MHz output

EMAC RMII receiver error

EMAC RMII receive data

EMAC RMII carrier sense data valid

EMAC RMII transmit enable

EMAC RMII trasmit data

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3.6.16 Multimedia Card/Secure Digital (MMC/SD)

Table 3-18. Multimedia Card/Secure Digital (MMC/SD) Terminal Functions

SIGNAL NAME TYPE

EMA_A[1]/MMCSD_CLK/GP1[1] 30 O IPU MMCSD Clock EMA_A[2]/MMCSD_CMD/GP1[2] 31 I/O IPU MMCSD Command EMA_D[7]/MMCSD_DAT[7]/GP0[7]/BOOT[13] 54 I/O IPU EMIFA, GPIO, BOOT EMA_D[6]/MMCSD_DAT[6]/GP0[6] 52 I/O IPU EMA_D[5]/MMCSD_DAT[5]/GP0[5] 51 I/O IPU EMA_D[4]/MMCSD_DAT[4]/GP0[4] 49 I/O IPU EMA_D[3]/MMCSD_DAT[3]/GP0[3] 48 I/O IPU EMA_D[2]/MMCSD_DAT[2]/GP0[2] 46 I/O IPU EMA_D[1]/MMCSD_DAT[1]/GP0[1] 45 I/O IPU EMA_D[0]/MMCSD_DAT[0]/GP0[0]/BOOT[12] 44 I/O IPU EMIFA, GPIO, BOOT

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name

highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured

function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different

types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

NO

PTP

(1)

PULL

(2)

MUXED DESCRIPTION

EMIFA, GPIO

EMIFA, GPIO MMC/SD data

3.6.17 Reserved and No Connect

Table 3-19. Reserved and No Connect Terminal Functions

SIGNAL NAME TYPE

RSV2 133 PWR

RSV3 149 PWR RSV4 148 I Reserved. This pin may be tied high or low.

NC 136 - No Connect (leave unconnected) NC 139 - No Connect (leave unconnected)

(1) PWR = Supply voltage.

PIN NO

PTP

(1)

Reserved. For proper device operation, this pin must be tied directly to CVDD.

DESCRIPTION

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3.6.18 Supply and Ground

Table 3-20. Supply and Ground Terminal Functions

SIGNAL NAME TYPE

CVDD (Core supply) 77, 93, 104, PWR Core supply voltage pins

RVDD (Internal RAM supply) 67, 159 PWR Internal ram supply voltage pins

DVDD (I/O supply) 87, 90, 99, PWR I/O supply voltage pins

VSS (Ground) 177 GND Ground pins

(1) PWR = Supply voltage, GND - Ground.

PIN NO

PTP

10, 20, 28, 38, 50, 56, 61, 69,

114, 147, 154, 161, 167

5, 15, 24, 33, 43, 47, 53, 58, 65, 71, 75, 81,

109, 119, 128, 151, 158, 164, 172

(1)

DESCRIPTION

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4 Device Configuration

4.1 Boot Modes

This device supports a variety of boot modes through an internal ROM bootloader. This device does not support dedicated hardware boot modes; therefore, all boot modes utilize the internal ROM. The input states of the BOOT pins are sampled and latched into the BOOTCFG register, which is part of the system configuration (SYSCFG) module, when device reset is deasserted. Boot mode selection is determined by the values of the BOOT pins

The following boot modes are supported:

• NAND Flash boot – 8-bit NAND

• NOR Flash boot – NOR Direct boot (8-bit or 16-bit) – NOR Legacy boot (8-bit or 16-bit) – NOR AIS boot (8-bit or 16-bit)

• I2C0 / I2C1 Boot – EEPROM (Master Mode) – External Host (Slave Mode)

• SPI0 / SPI1 Boot – Serial Flash (Master Mode) – SERIAL EEPROM (Master Mode) – External Host (Slave Mode)

• UART0 / UART1 / UART2 Boot – External Host

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Specifications and Main Features

Frequently Asked Questions

User Manual

1 AM1705 ARM Microprocessor

1.1 Features

1.2 Trademarks

1.3 Description

1.4 Functional Block Diagram

2 Revision History

3 Device Overview

3.1 Device Characteristics

3.2 Device Compatibility

3.3 ARM Subsystem

3.3.1 ARM926EJ-S RISC CPU

3.3.2 CP15

3.3.3 MMU

3.3.4 Caches and Write Buffer

3.3.5 Advanced High-Performance Bus (AHB)

3.3.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)

3.3.7 ARM Memory Mapping

3.4 Memory Map Summary

3.5 Pin Assignments

3.5.1 Pin Map (Bottom View)

3.6 Terminal Functions

3.6.1 Device Reset and JTAG

3.6.2 High-Frequency Oscillator and PLL

3.6.3 External Memory Interface A (ASYNC)

3.6.4 External Memory Interface B (only SDRAM )

3.6.5 Serial Peripheral Interface Modules (SPI0, SPI1)

3.6.6 Enhanced Capture/Auxiliary PWM Modules (eCAP0, eCAP1, eCAP2)

3.6.7 Enhanced Pulse Width Modulators (eHRPWM0, eHRPWM1, eHRPWM2)

3.6.8 Enhanced Quadrature Encoder Pulse Module (eQEP)

3.6.9 Boot

3.6.10 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)

3.6.11 Inter-Integrated Circuit Modules(I2C0, I2C1)

3.6.12 Timers

3.6.13 Multichannel Audio Serial Ports (McASP0, McASP1)

3.6.14 Universal Serial Bus Modules (USB0)

3.6.15 Ethernet Media Access Controller (EMAC)

3.6.16 Multimedia Card/Secure Digital (MMC/SD)

3.6.17 Reserved and No Connect

3.6.18 Supply and Ground

4 Device Configuration

4.1 Boot Modes