TEXAS INSTRUMENTS ADS8517 Technical data

ADS8517

ADS8517

SuccessiveApproximationRegister(SAR)

Comparator

CDAC

Ref

Buffer

BUF

ADC

REF

REF

CAP

R1

IN

40kW20kW

2.5-V

InternalReference

6kW

Parallel

and

Serial

DataOut

and

Control

Clock

40kW

10kW

R2

IN

REFD

Parallel
Data

PWRD
BYTE
BUSY
CS
R/C
SB/BTC
TAG
SDATA
DATACLK

EXT/INT

ADS8517

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.......................................................................................................................................................................................... SLAS527 – SEPTEMBER 2008

16-Bit, 200-kSPS, Low-Power, Sampling ANALOG-TO-DIGITAL CONVERTER

with Internal Reference and Parallel/Serial Interface

1

FEATURES APPLICATIONS

23

• 200-kHz Minimum Sampling Rate

• 4-V, 5-V, and ± 10-V Input Ranges with

High-Impedance Input

• ± 1.5 LSB Max INL

• +1.5/ – 1 LSB Max/Min DNL, 16 Bits NMC

• ± 2-mV Max BPZ, ± 0.6 ppm/ ° C BPZ Drift

• ± 2-mV Max UPZ, ± 0.15 ppm/ ° C UPZ Drift

• 88.8-dB SINAD with 10-kHz Input

• SPI™-Compatible Serial Output With

Daisy-Chain (TAG), SPI Master/Slave Feature

• Full Parallel Interface

• Binary Twos Complement or Straight Binary

Output Code Formats

• Single 4.5-V to 5.5-V Analog Supply, 1.65-V to

5.5-V Interface Supply

• Uses Internal 2.5-V or External Reference

• No External Precision Resistors Required

• Low Power Dissipation (ADC+REF+BUF):

– 47 mW Typ, 60 mW Max at 200 kSPS

• 50- µ W Max Power-Down Mode

• Pin-Compatible with 16-Bit ADS7807 and

ADS8507 , and 12-Bit ADS7806 and ADS8506

• SO-28 Package (TSSOP-28 Available Q2, 2009)

• Portable Test Equipment

• USB Data Acquisition Module

• Medical Equipment

• Industrial Process Control

• Digital Signal Processing

• Instrumentation

DESCRIPTION

The ADS8517 is a complete low-power, single 5-V
supply, 16-bit sampling analog-to-digital (A/D)
converter. It contains a complete, 16-bit,
capacitor-based, successive approximation register
(SAR) A/D converter with sample-and-hold, clock,
reference, and data interface. The converter can be
configured for a variety of input ranges including ± 10
V, 4 V, and 5 V. For most input ranges, the input
voltage can swing to 25 V or – 25 V without damage
to the device.

An SPI-compatible serial interface allows data to be
synchronized to an internal or external clock. A full
parallel interface using the selectable BYTE pin is
also provided to allow the maximum system design
flexibility. The ADS8517 is specified at a 200-kHz
sampling rate over the industrial – 40 ° C to +85 ° C
temperature range.

1

2 SPI is a trademark of Motorola, Inc.
3 All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright © 2008, Texas Instruments Incorporated

ADS8517

SLAS527 – SEPTEMBER 2008 ..........................................................................................................................................................................................

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

PACKAGE/ORDERING INFORMATION

MINIMUM

RELATIVE NO MINIMUM SPECIFIED

PRODUCT (LSB) CODE (dB) RANGE LEAD DESIGNATOR NUMBER MEDIA, QTY

ADS8517IB ± 1.5 16 87 -40 ° C to +85 ° C

ADS8517I ± 3 15 85 -40 ° C to +85 ° C

ACCURACY MISSING SINAD TEMPERATURE PACKAGE- PACKAGE ORDERING TRANSPORT

SO-28 DW

TSSOP-28

TSSOP-28

(2)

SO-28 DW

(2)

(1)

ADS8517IBDW Tube, 20

ADS8517IBDWR Tape and Reel, 1000

PW

PW

ADS8517IBPW Tube, 50

ADS8517IBPWR Tape and Reel, 2000

ADS8517IDW Tube, 20

ADS8517IDWR Tape and Reel, 1000

ADS8517W Tube, 50

ADS8517IPWR Tape and Reel, 2000

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(2) TSSOP-28 (PW) package available Q2, 2009.

ABSOLUTE MAXIMUM RATINGS

(1) (2)

Over operating free-air temperature range (unless otherwise noted).

PARAMETER UNIT

R1

IN

Analog inputs R2

IN

REF +V

ANA

DGND, AGND2 ± 0.3 V
V

Ground voltage differences

ANA

V

to V

DIG

ANA

V

DIG

Digital inputs -0.3 V to +V
Maximum junction temperature +165 ° C
Storage temperature range – 65 ° C to +150 ° C
Internal power dissipation 700 mW
Lead temperature (soldering, 1.6 mm from case, 10 seconds) +260 ° C

(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute

maximum conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal.

± 25 V
± 25 V

+ 0.3 V to AGND2 – 0.3 V

6 V

0.3 V
6 V

+ 0.3 V

DIG

ELECTRICAL CHARACTERISTICS

At TA= -40 ° C to +85 ° C, fS= 200 kHz, V

PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT

Resolution 16 16 Bits

ANALOG INPUT

Voltage ranges See Table 1 0 5 0 5 V

Impedance See Table 1
Capacitance 45 45 pF

(1) Shaded cells indicate different specifications for high-grade version of the device.

2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated

= V

DIG

= 5 V, using internal reference (see Figure 39 ), unless otherwise noted.

ANA

ADS8517I ADS8517IB

– 10 10 – 10 10

0 4 0 4

Product Folder Link(s): ADS8517

(1)

ADS8517

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.......................................................................................................................................................................................... SLAS527 – SEPTEMBER 2008

ELECTRICAL CHARACTERISTICS (continued)

At TA= -40 ° C to +85 ° C, fS= 200 kHz, V

PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT

THROUGHPUT SPEED

Conversion time 2.5 2.5 µ s
Complete cycle Acquire and convert 5 5 µ s
Throughput rate 200 200 kHz

DC ACCURACY

INL Integral linearity error – 3 3 – 1.5 1.5 LSB
DNL Differential linearity error – 2 3 – 1 1.5 LSB

No missing codes 15 16 Bits
Transition noise
Gain error ± 0.2 ± 0.1 %

Full-scale error

Full-scale error drift

BPZ Bipolar zero error ± 10 V range – 5 ± 1 5 – 2 ± 1 2 mV

Bipolar zero error drift ± 10 V range ± 0.6 ± 0.6 ppm/ ° C

UPZ Unipolar zero error 0 V to 5 V, 0 V to 4 V ranges – 3 ± 0.1 3 – 2 ± 0.1 2 mV

Unipolar zero error drift 0 V to 5 V, 0 V to 4 V ranges ± 0.15 ± 0.15 ppm/ ° C
Recovery time to rated accuracy

from power down
Power-supply sensitivity

(V

= V

DIG

AC ACCURACY

SFDR Spurious-free dynamic range fIN= 10 kHz, ± 10 V 92 100 96 101 dB
THD Total harmonic distortion fIN= 10 kHz, ± 10 V – 97 – 92 – 98 – 95 dB

SINAD Signal-to-(noise+distortion) dB

SNR Signal-to-noise ratio fIN= 10 kHz, ± 10 V 85 88 88 89 dB

SNR usable bandwidth
SNR full-power bandwidth ( – 3 dB) fIN= 10 kHz, ± 10 V 600 600 kHz

SAMPLING DYNAMICS

Aperture delay 40 40 ns
Aperture jitter 20 20 ps
Transient response FS step 5 5 µ s
Overvoltage recovery

(2) LSB means Least Significant Bit. One LSB for the ± 10 V input range is 305 µ V.
(3) Typical rms noise at worst-case transitions.
(4) Full-scale error is the worst case of – Full Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by

the transition voltage (not divided by the full-scale range) and includes the effect of offset error.

(5) This is the time delay after the ADS8517 is brought out of Power-Down mode until all internal settling occurs and the analog input is

acquired to rated accuracy. A Convert command after this delay will yield accurate results.
(6) All specifications in dB are referred to a full-scale input.
(7) Usable bandwidth defined as full-scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60 dB.
(8) Recovers to specified performance after 2 x FS input overvoltage.

(3)

(4)

(5)

= VS)

ANA

(7)

(8)

= V

DIG

Internal reference – 0.75 0.75 – 0.75 0.75 %
External 2.5-V reference – 0.75 0.75 – 0.75 0.75 %
Internal reference ± 9 ± 9 ppm/ ° C
External 2.5-V reference ± 1 ± 1 ppm/ ° C

2.2- µ F capacitor to CAP 1 1 ms
+4.75 V < V

+4.5 V < V

fIN= 10 kHz, ± 10 V 85 88 87 88.5
– 60 dB Input 29 29

fIN= 10 kHz, ± 10 V 130 130 kHz

= 5 V, using internal reference (see Figure 39 ), unless otherwise noted.

ANA

ADS8517I ADS8517IB

0.9 0.8 LSB

< +5.25 V – 8 +8 – 6 +6

ANA

< +5.5 V – 20 +20 – 12 +12

ANA

750 750 ns

(1)

(2)

LSB

(6)

Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 3

Product Folder Link(s): ADS8517

ADS8517

SLAS527 – SEPTEMBER 2008 ..........................................................................................................................................................................................

ELECTRICAL CHARACTERISTICS (continued)

At TA= -40 ° C to +85 ° C, fS= 200 kHz, V

PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT

REFERENCE

Internal reference voltage No load 2.48 2.5 2.52 2.48 2.5 2.52 V
Internal reference source current

(must use external buffer)
Internal reference drift 8 8 ppm/ ° C
External reference voltage range

for specified linearity
External reference current drain External 2.5-V reference 100 100 µ A

DIGITAL INPUTS

V

Low-level input voltage

IL

V

High-level input voltage

IH

I

Low-level input current VIL= 0 V ± 10 ± 10 µ A

IL

I

High-level input current VIH= 5 V ± 10 ± 10 µ A

IH

DIGITAL OUTPUTS

Data format - Parallel 16-bits in 2-bytes, Serial
Data coding - Binary twos complement or straight binary

V

Low-level output voltage 0.45 0.45 V

OL

V

High-level output voltage V

OH

Leakage current ± 5 ± 5 µ A
Output capacitance High-Z state 15 15 pF

DIGITAL TIMING

Bus access time RL= 3.3 k Ω , CL= 50 pF 83 83 ns
Bus relinquish time RL= 3.3 k Ω , CL= 10 pF 83 83 ns

POWER SUPPLIES

V

Interface voltage 1.65 1.8 5.5 1.65 1.8 5.5 V

DIG

V

ADC core voltage 4.5 5 5.5 4.5 5 5.5 V

ANA

I

Interface current V

DIG

I

ADC core current V

ANA

Power dissipation

TEMPERATURE RANGE

Specified performance – 40 +85 – 40 +85 ° C
Derated performance – 55 +125 – 55 +125 ° C
Storage temperature – 65 +150 – 65 +150 ° C

θ

Thermal impedance ° C/W

JA

(9) TTL-compatible at 5V supply.

(9)

(9)

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= V

DIG

= 5 V, using internal reference (see Figure 39 ), unless otherwise noted.

ANA

ADS8517I ADS8517IB

(1)

1 1 µ A

2.3 2.5 2.7 2.3 2.5 2.7 V

V

= 1.65 V to 5.5 V – 0.3 0.6 – 0.3 0.6 V

DIG

V

= 1.65 V to 5.5 V 0.5 x V

DIG

I

= 1.6mA,

SINK

V

= 1.65V to 5.5V

DIG

I

= 500 µ A,

SOURCE

V

= 1.65V to 5.5V

DIG

DIG

– 0.45 V

DIG

V

+ 0.3 0.5 x V

DIG

DIG

– 0.45 V

DIG

V

DIG

+ 0.3 V

High-Z state,
V

= 0 V to V

OUT

= 5 V 0.3 0.3 mA

DIG

= 5 V 9 9 mA

ANA

V

= V

ANA

fS= 200 kHz

DIG

= 5 V,

DIG

47 60 47 60 mW

REFD high with BUF on 42 42 mW
PWRD and REFD high 50 50 µ W

TSSOP 62 62
SO 46 46

Table 1. Analog Input Range Connections (see Figure 38 and Figure 39 )

ANALOG INPUT

RANGE CONNECT R1

± 10 V V
0 V to 5 V AGND V
0 V to 4 V V

4 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated

VIA 200 Ω TO CONNECT R2

IN

IN

IN

Product Folder Link(s): ADS8517

VIA 100 Ω TO IMPEDANCE

IN

CAP 45.7 k Ω

IN

V

IN

20.0 k Ω

21.4 k Ω

V

DIG

V

ANA

BUSY

CS

R/C

BYTE

TAG

SDATA

DATACLK

D0

D1

D2

R1

IN

AGND1

CAP

REF

AGND2

D7

D6

D5

D4

D3

DGND

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

ADS8517

R2

IN

SB/BTC

EXT/INT

REFD

PWRD

ADS8517

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.......................................................................................................................................................................................... SLAS527 – SEPTEMBER 2008

PIN CONFIGURATION

DW, PW PACKAGES

SO-28, TSSOP-28

(TOP VIEW)

(1)

(1) TSSOP-28 (PW) package available Q2, 2009.

Pin Assignments

PIN

NAME NO. I/O DESCRIPTION

R1

IN

1 Analog Input.

AGND1 2 Analog sense ground. Used internally as ground reference point. Minimal current flow

R2

IN

3 Analog Input.

CAP 4 Reference buffer output. 2.2- µ F tantalum capacitor to ground.
REF 5

AGND2 6 Analog ground

SB/ BTC 7 I high, data are output in a straight binary format. If low, data are output in a binary twos

EXT/ INT 8 I

D7 9 O
D6 10 O Data bit 6 if BYTE is high. Data bit 14 if BYTE is low. High-Z when CS is high and/or R/ C is low.

D5 11 O Data bit 5 if BYTE is high. Data bit 13 if BYTE is low. High-Z when CS is high and/or R/ C is low.
D4 12 O Data bit 4 if BYTE is high. Data bit 12 if BYTE is low. High-Z when CS is high and/or R/ C is low.
D3 13 O Data bit 3 if BYTE is high. Data bit 11 if BYTE is low. High-Z when CS is high and/or R/ C is low.

DGND 14 Digital ground

D2 15 O Data bit 2 if BYTE is high. Data bit 10 if BYTE is low. High-Z when CS is high and/or R/ C is low.
D1 16 O Data bit 1 if BYTE is high. Data bit 9 if BYTE is low. High-Z when CS is high and/or R/ C is low.

Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 5

DIGITAL

Reference input/output. Outputs internal 2.5-V reference. Can also be driven by external system
reference. In both cases, bypass to ground with a 2.2- µ F tantalum capacitor.

Output mode select. Selects straight binary or binary twos complement for output data format. If
complement format.

External/internal data select. Selects external/internal data clock for transmitting data. If high,
data is output synchronized to the clock input on DATACLK. If low, a convert command initiates
the transmission of the data from the previous conversion, along with 16-clock pulses output on
DATACLK.

Data bit 7 if BYTE is high. Data bit 15 (MSB) if BYTE is low. High-Z when CS is high and/or R/ C
is low. Leave unconnected when using serial output.

Product Folder Link(s): ADS8517

ADS8517

SLAS527 – SEPTEMBER 2008 ..........................................................................................................................................................................................

Pin Assignments (continued)

D0 17 O

DATACLK 18 I/O synchronized to this clock. If EXT/ INT is low, DATACLK transmits 16 pulses after each

SDATA 19 O TAG as long as CS is low and R/ C is high. If EXT/ INT is low, data are valid on both the rising

TAG 20 I

BYTE 21 I

R/ C 22 I into the hold state and starts a conversion. With EXT/ INT is low, the transmission of the data

CS 23 I conversion. If EXT/ INT is low, this same falling edge will start the transmission of serial data

BUSY 24 O

PWRD 25 I

REFD 26 I

V

ANA

V

DIG

27 ADC core supply. Nominally +5 V. Decouple with 0.1- µ F ceramic and 10- µ F tantalum capacitors.
28 I/O supply. Nominally +1.8 V.

Data bit 0 (LSB) if BYTE is high. Data bit 8 if BYTE is low. High-Z when CS is high and/or R/ C is
low.

Data clock. Either an input or an output, depending on the EXT/ INT level. Output data are
conversion, and then remains low between conversions.

Serial data output. Data are synchronized to DATACLK, with the format determined by the level
of SB/ BTC. In the external clock mode, after 16 bits of data, the ADC outputs the level input on

and falling edges of DATACLK, and between conversions SDATA stays at the level of the TAG
input when the conversion was started.

Tag input for use in the external clock mode. If EXT is high, digital data input from TAG is output
on DATA with a delay that depends on the external clock mode.

Byte select. Selects the eight most significant bits (low) or eight least significant bits (high) on
parallel output pins.

Read/convert input. With CS low, a falling edge on R/ C puts the internal sample-and-hold circuit
results from the previous conversion is initiated.

Chip select. Internally ORed with R/ C. If R/ C is low, a falling edge on CS initiates a new
results from the previous conversion.

Busy output. At the start of a conversion, BUSY goes low and stays low until the conversion is
completed and the digital outputs have been updated.

Power-down input. If high, conversions are inhibited and power consumption is significantly
reduced. Results from the previous conversion are maintained in the output shift register.

Reference disable. REFD high shuts down the internal reference. The external reference is
required for conversions.

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Product Folder Link(s): ADS8517

10.0

9.5

9.0

8.5

8.0

Temperature( C)°

P

ower

-SupplyCurrent(mA)

-50 -25 0 25 50 75 100 125

2.520

2.515

2.510

2.505

2.500

2.495

2.490

2.485

2.480

Temperature( C)°

InternalReferenceV

oltage(V)

-50 -25 0 125100755025

10.0

9.5

9.0

8.5

8.0

SamplingFrequency(kHz)

Power

-SupplyCurrent(mA)

50 100 150 200

2

1

0

-1

-2

Temperature( C)°

Offset(mV)

-50 -25 1251007550250

Bipolar 10VRange±

0.10

0.05

0

Temperature(°C)

PositiveFull-ScaleError(%)

-40 -50 1251007550250

Bipolar10VRange

0

-0.05

-0.10

Temperature( C)°

NegativeFull-ScaleError(%)

-50 -45 1251007550250

Bipolar10VRange

ADS8517

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.......................................................................................................................................................................................... SLAS527 – SEPTEMBER 2008

TYPICAL CHARACTERISTICS

At fS= 200 kHz, V

POWER-SUPPLY CURRENT INTERNAL REFERENCE VOLTAGE

vs FREE-AIR TEMPERATURE vs FREE-AIR TEMPERATURE

POWER-SUPPLY CURRENT BIPOLAR OFFSET ERROR
vs SAMPLING FREQUENCY vs FREE-AIR TEMPERATURE

= V

DIG

= 5 V, and using internal reference (see Figure 39 ), unless otherwise specified.

ANA

Figure 1. Figure 2.

Figure 3. Figure 4.

BIPOLAR POSITIVE FULL-SCALE ERROR BIPOLAR NEGATIVE FULL-SCALE ERROR

vs FREE-AIR TEMPERATURE vs FREE-AIR TEMPERATURE

Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 7

Figure 5. Figure 6.

Product Folder Link(s): ADS8517

0.2

0.1

0

-0.1

-0.2

Temperature( C)°

Offset(mV)

-50 -25 1251007550250

Unipolar4VRange

0.2

0.1

0

-0.1

-0.2

Temperature( C)°

Offset(mV)

-50 -25 1251007550250

Unipolar5VRange

0.10

0.05

0

-0.05

-0.10

Temperature( C)°

Offset(mV)

-50 -25 1251007550250

Unipolar4VRange

0.10

0.05

0

-0.05

-0.10

Temperature( C)°

Offset(mV)

-50 -25 1251007550250

Unipolar5VRange

110

105

100

95

90

85

80

-80

-85

-90

-95

-100

-105

-110

Temperature( C)°

SFDR,SINAD,andSNR(dB)

THD(dB)

-50 -25 1251007550250

SINAD

SNR

SFDR

THD

f =10kHz,0dB

IN

89.5

89.0

88.5

88.0

87.5

Temperature( C)°

SINAD(dB)

-50 -25 1251007550250

f =100kHz

S

f =150kHz

S

f =10kHz,0dB

IN

f =200kHz

S

f =50kHz

S

ADS8517

SLAS527 – SEPTEMBER 2008 ..........................................................................................................................................................................................

At fS= 200 kHz, V

TYPICAL CHARACTERISTICS (continued)

= V

DIG

UNIPOLAR OFFSET ERROR UNIPOLAR OFFSET ERROR

vs FREE-AIR TEMPERATURE vs FREE-AIR TEMPERATURE

UNIPOLAR FULL-SCALE ERROR UNIPOLAR FULL-SCALE ERROR

vs FREE-AIR TEMPERATURE vs FREE-AIR TEMPERATURE

= 5 V, and using internal reference (see Figure 39 ), unless otherwise specified.

ANA

Figure 7. Figure 8.

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8 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated

Figure 9. Figure 10.

AC PARAMETERS SIGNAL-TO-(NOISE+DISTORTION)

vs FREE-AIR TEMPERATURE vs FREE-AIR TEMPERATURE

Figure 11. Figure 12.

Product Folder Link(s): ADS8517

100

90

80

70

60

50

40

30

20

10

InputSignalFrequency(kHz)

SINAD(dB)

0 2 4 8 106 12 14 16 18 20

-60dB

-20dB

0dB

100

90

80

InputSamplingFrequency(kHz)

SNR(dB)

1 10010

100

90

80

InputSamplingFrequency(kHz)

SINAD(dB)

1 10010

110

100

90

80

70

InputSamplingFrequency(kHz)

SFDR(dB)

1 10010

-70

-80

-90

-100

-110

-120

InputSamplingFrequency(kHz)

THD(dB)

1 10010

110

105

100

95

90

85

80

-80

-85

-90

-95

-100

-105

-110

ESR( )W

SFDR,SINAD,andSNR(dB)

THD(dB)

0 1 4 5 6 7 8 9 10

THD

SNR

SFDR

SINAD

f =10kHz,0dB

IN

32

ADS8517

www.ti.com

.......................................................................................................................................................................................... SLAS527 – SEPTEMBER 2008

At fS= 200 kHz, V

vs INPUT FREQUENCY AND INPUT AMPLITUDE vs INPUT FREQUENCY

TYPICAL CHARACTERISTICS (continued)

= V

DIG

SIGNAL-TO-(NOISE+DISTORTION) SIGNAL-TO-NOISE RATIO

SIGNAL-TO-(NOISE+DISTORTION) SPURIOUS-FREE DYNAMIC RANGE

= 5 V, and using internal reference (see Figure 39 ), unless otherwise specified.

ANA

Figure 13. Figure 14.

vs INPUT FREQUENCY vs INPUT FREQUENCY

TOTAL HARMONIC DISTORTION AC PARAMETERS

vs INPUT FREQUENCY vs CAP PIN CAPACITOR ESR

Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 9

Figure 15. Figure 16.

Figure 17. Figure 18.

Product Folder Link(s): ADS8517

110

105

100

95

90

85

80

75

70

-70

-75

-80

-85

-90

-95

-100

-105

-110

Power-SupplyVoltage(V)

SFDR,SINAD,andSNR(dB)

THD(dB)

4.00 4.25 4.50 4.75 5.00 5.25 5.50

THD

SNR

SFDR

SINAD

f =10kHz,0dB

IN

-20

-30

-40

-50

-60

-70

-80

Power-SupplyRippleFrequency(Hz)

OutputRejection(dB)

10 1M100 1k 10k 100k

2.40

2.35

2.30

2.25

2.20

Temperature( C)°

ConversionTime( s)m

-50 -25 1251007550250

2.0

1.5

1.0

0.5

0

-0.5

-1.0

-1.5

-2.0

Power-SupplyVoltage(V)

INL/DNLMaxandMin(LSB)

4.00 4.25 4.50 4.75 5.00 5.25 5.50

INLMax

INLMin

DNLMin

DNLMax

3

2

1

0

-1

-2

-3

Code

INL(LSB)

0 8192 16384 24576 32768 40960 49152 57344 65535

AllCodesINL

3

2

1

0

-1

-2

-3

Code

DNL(LSB)

0 8192 16384 24576 32768 40960 49152 57344 65535

AllCodesDNL

ADS8517

SLAS527 – SEPTEMBER 2008 ..........................................................................................................................................................................................

At fS= 200 kHz, V

TYPICAL CHARACTERISTICS (continued)

= V

DIG

vs POWER-SUPPLY VOLTAGE vs POWER-SUPPLY RIPPLE FREQUENCY

vs FREE-AIR TEMPERATURE vs POWER-SUPPLY VOLTAGE

= 5 V, and using internal reference (see Figure 39 ), unless otherwise specified.

ANA

AC PARAMETERS OUTPUT REJECTION

Figure 19. Figure 20.

INTEGRAL LINEARITY ERROR AND

CONVERSION TIME DIFFERENTIAL LINEARITY ERROR

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Figure 21. Figure 22.

INTEGRAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR

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Figure 23. Figure 24.

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0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

Frequency(kHz)

Amplitude(dB)

0 25 50 10075

4096PointFFT

f =1kHz,0dB

IN

Frequency(kHz)

0 25 50 10075

4096PointFFT

f =10kHz,0dB

IN

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

Amplitude(dB)

Frequency(kHz)

0 25 50 10075

4096PointFFT

f =20kHz,0dB

IN

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

Amplitude(dB)

ADS8517

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.......................................................................................................................................................................................... SLAS527 – SEPTEMBER 2008

At fS= 200 kHz, V

TYPICAL CHARACTERISTICS (continued)

= V

DIG

= 5 V, and using internal reference (see Figure 39 ), unless otherwise specified.

ANA

FFT FFT

Figure 25. Figure 26.

FFT

Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 11

Figure 27.

Product Folder Link(s): ADS8517

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

ADS8517

+5 V

+

+

ConvertPulse

40nsmin

0.1 mF 10 mF

+

NOTE:(1)NC=notconnected.

B11B12B13B1 4B15

(MSB)

Pin21

LOW

B3B4B5B6B7Pin21

HIGH

NC

(1)

B8B9B10

B0

(LSB)

B1B2

BUSY

R/C

BYTE

±10 V

2.2 Fm

+5V

2.2 Fm

+1.8V

0.1 Fm

ADS8517

SLAS527 – SEPTEMBER 2008 ..........................................................................................................................................................................................

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BASIC OPERATION

PARALLEL OUTPUT

Figure 28 shows a basic circuit for operating the ADS8517 with a ± 10-V input range and parallel output. Taking

R/ C (pin 22) low for a minimum of 40 ns (5 µ s max) initiates a conversion. BUSY (pin 24) goes low and stays low
until the conversion completes and the output register updates. If BYTE (pin 21) is low, the eight most significant
bits (MSBs) will be valid when BUSY rises; if BYTE is high, the eight least significant bits (LSBs) will be valid
when BUSY rises. Data are output in binary twos complement (BTC) format. BUSY going high can be used to
latch the data. After the first byte has been read, BYTE can be toggled, allowing the remaining byte to be read.
All convert commands are ignored while BUSY is low.

The ADS8517 begins tracking the input signal at the end of the conversion. Allowing 5 µ s between convert
commands assures accurate acquisition of a new signal.

Figure 28. Basic ± 10-V Operation, Both Parallel and Serial Output

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Product Folder Link(s): ADS8517