Texas Instruments ADS8402 EVM, ADS8402, ADS8412 EVM User Manual

ADS8402/ADS8412EVM

User’s Guide

December 2003 Data Acquistion

SLAU126

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Copyright  2003, Texas Instruments Incorporated

EVM IMPORTANT NOTICE

Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EV ALUATION

PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided
may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective
considerations, including product safety measures typically found in the end product incorporating the goods.
As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic
compatibility and therefore may not meet the technical requirements of the directive.

Should this evaluation kit not meet the specifications indicated in the EVM User’s Guide, the kit may be returned
within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE
WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER W ARRANTIES, EXPRESSED,
IMPLIED, OR S TA TUTOR Y, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY
PARTICULAR PURPOSE.

The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user
indemnifies TI from all claims arising from the handling or use of the goods. Please be aware that the products
received may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). Due to the open construction
of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic
discharge.

EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE
TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.

TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not
exclusive.

TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein.

Please read the EVM User’s Guide and, specifically, the EVM Warnings and Restrictions notice in the EVM
User’s Guide prior to handling the product. This notice contains important safety information about temperatures
and voltages. For further safety concerns, please contact the TI application engineer.

Persons handling the product must have electronics training and observe good laboratory practice standards.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any

machine, process, or combination in which such TI products or services might be or are used.

Mailing Address:

Texas Instruments
Post Office Box 655303
Dallas, Texas 75265

Copyright  2003, Texas Instruments Incorporated

EVM WARNINGS AND RESTRICTIONS

It is important to operate this EVM within the input voltage range of ±6 V and the output voltage
range of 0 V and 5.5 V.

Exceeding the specified input range may cause unexpected operation and/or irreversible
damage to the EVM. If there are questions concerning the input range, please contact a TI
field representative prior to connecting the input power.

Applying loads outside of the specified output range may result in unintended operation and/or
possible permanent damage to the EVM. Please consult the EVM User ’s Guide prior to
connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.

During normal operation, some circuit components may have case temperatures greater than
60°C. The EVM is designed to operate properly with certain components above 60°C as long
as the input and output ranges are maintained. These components include but are not limited
to linear regulators, switching transistors, pass transistors, and current sense resistors. These
types of devices can be identified using the EVM schematic located in the EVM User’s Guide.
When placing measurement probes near these devices during operation, please be aware
that these devices may be very warm to the touch.

Mailing Address:

Texas Instruments
Post Office Box 655303
Dallas, Texas 75265

Copyright  2003, Texas Instruments Incorporated

About This Manual

Related Documentation From Texas Instruments

Preface

Read This First

This users guide describes the characteristics, operation, and use of the
ADS8402/ADS8412 16-bit, high speed, parallel interface analog-to-digital
converter evaluation board. A complete circuit description as well as a
schematic diagram and bill of materials are included.

How to Use This Manual

This document contains the following chapters:

- Chapter 1 – EVM Overview

- Chapter 2 – Analog Interface

- Chapter 3 – Digital Interface

- Chapter 4 – Power Supply Requirements

- Chapter 5 – Using the EVM

- Chapter 6 - ADS8402/ADS8412 BOM, Layout, and Schematic

Related Documentation From Texas Instruments

To obtain a copy of any of the following TI documents, call the Texas
Instruments Literature Response Center at (800) 477 - 8924 or the Product
Information Center (PIC) at (972) 644- 5580. When ordering, identify this
booklet by its title and literature number. Updated documents can also be
obtained through our website at www.ti.com

Data Sheets: Literature Number:

ADS8402 SLAS154
ADS8412 SLAS384
REF3040 SBVS032
SN74AHC138 SCLS258
SN74AHC245 SCLS230
SN74AHC1G04 SCLS318
THS4503 SLOS352

iii

Contents

FCC Warning

This equipment is intended for use in a laboratory test environment only. It gen­erates, uses, and can radiate radio frequency energy and has not been tested
for compliance with the limits of computing devices pursuant to subpart J of
part 15 of FCC rules, which are designed to provide reasonable protection
against radio frequency interference. Operation of this equipment in other en­vironments may cause interference with radio communications, in which case
the user at his own expense will be required to take whatever measures may
be required to correct this interference.

iv

Contents

Contents

1 EVM Overview 1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Features 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Introduction 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Analog Interface 2-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Signal Conditioning 2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Reference 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Digital Interface 3-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Power Supply Requirements 4-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Using the EVM 5-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 As a Reference Board 5-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 As a Prototype Board 5-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 As a Software Test Platform 5-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 ADS8402/ADS8412EVM BOM, Layout, and Schematic 6-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1 ADS8402/ADS8412EVM Bill of Materials 6-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2 ADS8402/ADS8412EVM Layout 6-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3 ADS8402/ADS8412EVM Schematic 6-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

v

Contents

Figures

1-1 Input Buffer Circuit 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-1 Top Layer—Layer 1 5-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-2 Ground Plane—Layer 2 5-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-3 Power Plane—Layer 3 5-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-4 Bottom Layer—Layer 4 5-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Tables

1-1 Analog Input Connector 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-2 Solder Short Jumper Setting 1-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-1 Pinout for Parallel Control Connector P2 2-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-2 Jumper Settings for Decoder Outputs 2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-3 Data Bus Connector P3 2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-4 Pinout for Converter Control Connector J3 2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-1 Power Supply Test Points 3-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-2 Power Connector, J1, Pinout 3-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-1 ADS8402/ADS8412EVM Bill Of Materials 5-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vi

Chapter 1

EVM Overview

This chapter contains the features of the ADS8402/ADS8412.

Topic Page

1.1 Features 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Introduction 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

EVM Overview

1-1

Features

1.1 Features

1.2 Introduction

- Full-featured evaluation board for the high-speed ADS8402 (1.25 MSPS)

and the ADS8412 (2 MSPS) high speed, 16-bit, single channel, parallel
interface SAR-type analog-to-digital converters.

- Onboard signal conditioning

- Onboard reference

- Input and output digital buffer

- Onboard decoding for stacking multiple EVMs

The ADS8402EVM and ADS8412EVM is a modular or stand alone EVM. It has
the bare minimum circuitry to showcase the device under test and plug into
prototype systems. The onboard decoding circuitry enables the user flexibility
to map the A/D to different addresses in processor memory. The power, analog
and digital control lines are on standard 0.1-in. header/socket connectors, at
the edges of the PWB, making it easy to wire into prototype systems for
evaluation. The EVM has been designed for direct evaluation of the
analog-to-digital converter performance and operating characteristics. This
EVM is compatible with the 5 -6K interface board (SLAU104) from Texas
Instruments and additional third party boards.

1-2

Chapter 2

Analog Interface

The ADS8402/ADS8412EVM analog-to-digital converter has a unipolar
differential input. A unipolar differential input is a differential signal (inverting
and noninverting input is 180 degrees out of phase) that is level shifted such
that the signals levels are always equal to or above zero volts. The
peak-to-peak amplitude on each input pin can be as large as the reference
voltage. See the respective product data sheet for more information.

Topic Page

2.1 Signal Conditioning 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Reference 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog Interface

2-1

Signal Conditioning

2.1 Signal Conditioning

The ADS8402/ADS8412EVM comes installed with the unity gain buffer (U2)
wired for single-ended in to differential out configuration. The common-mode
voltage is derived from a REF3040 reference IC and is adjustable using a
potentiometer (R9). The common-mode voltage pin of the THS4503 is set to
2 V on the evaluation module. A single-ended input signal can be applied at
pin connector P1 or via SMA connectors J2 (noninverting input). The buffer
circuit can be reconfigured for a unipolar differential input by installing resistor
R6 and R8 and removing R1. The inverting leg of the differential signal should
be applied to either connector P1 pin 1 or SMA connector J4 (inverting input).
See Table 2-1 for the pinout of the analog connector, P1. See Chapter 6 for
the EVM schematic.

Table 2-1.Analog Input Connector

Description Signal Name Connector.Pin# Signal Name Description

Inverting input (-) P1.1 P1.2 + Noninverting input

Reserved N/A P1.3 P1.4 N/A Reserved
Reserved N/A P1.5 P1.6 N/A Reserved

Reserved N/A P1.7 P1.8 N/A Reserved
Pin tied to ground AGND P1.9 P.10 N/A Reserved
Pin tied to ground AGND P1.11 P1.12 N/A Reserved

Reserved N/A P1.13 P1.14 N/A Reserved
Pin tied to ground AGND P1.15 P1.16 N/A Reserved
Pin tied to ground AGND P1.17 P1.18 N/A Reserved

Reserved N/A P1.19 P1.20 REF+ External reference input

It is recommended the analog input to any SAR-type converter be buffered.
The amplifier circuit in Figure 2-1 is the buffer circuit used on the
ADS8402/ADS8412EVM. This circuit consists of the THS4503, a high-speed
fully differential amplifier configured as a single-ended in to differential out,
unity gain buffer. The circuit shown in Figure 2-1 was optimized to achieve the
ac (i.e., SNR, THD, SFDR, etc.) specifications listed in the ADS8402 and
ADS8412 data sheets. The 60-pF and 6800-pF capacitors in the signal path
are polypropylene type, manufactured by the WIMA Corporation.
Polypropylene capacitors cause the least distortion of the input signal.

2-2

Figure 2-1.Input Buffer Circuit

Reference

THS4503

+V

Reference

60 pF

1 kΩ

CC

0.1 µF
1 µF

1 kΩ

V

I

+2.048 V

+

V

-

1 kΩ

-V

2.2 Reference

The EVM allows users to select from three reference sources. The
ADS8402/ADS8412EVM provides an onboard 4.096-V reference, U3. The
EVM also has the provision for users to supply a reference voltage via
connecter P1 pin 20. The user reference voltage and onboard reference
voltages can be filtered by installing amplifier U1. Both the ADS8402 and
ADS8412 analog-to-digital converters have integrated onboard reference
buffers; therefore, it is not necessary to buffer the voltage externally. The
reference buffer circuit on the EVM is not populated with an amplifier. The EVM
comes installed with an on-chip internal reference tied directly to the reference
pin of the converter. See Chapter 6 for the schematic.

Table 2-2.Solder Short Jumper Setting

-

OCM

+

CC

1 µF

0.1 µF

1 kΩ

60 pF

25 Ω

25 Ω

(+) IN

6800 pF

(-) IN

Reference

Designator

SJP1 Not used on the EVM
SJP2 On-chip internal reference applied to reference pin Installed
SJP3

SJP4

SJP5

†

Factory set condition

Apply reference voltage from external source Not Installed Installed
Apply voltage to amplifier, U2, common-mode voltage pin Installed
Buffer onboard reference, REF3040 Installed Not installed
Buffer user reference voltage applied at P1 pin 20. Not Installed Installed
Select REF3040 for reference voltage Installed Not installed
Select buffered reference voltage Not Installed Installed

Description

Analog Interface

Jumper Setting

1-2 2-3

†

†

N/A

2-3

2-4

The ADS8402/ADS8412 EVM is designed for easy interfacing to multiple
platforms. Samtec part numbers SSW-110-22-F-D-VS-K and
TSM-110-01-T-DV-P provide a convenient dual row header/socket
combination at P2 and P3. Consult Samtec at www.samtec.com or
1-800-SAMTEC-9 for a variety of mating connector options.

Table 3-1.Pinout for Parallel Control Connector P2

Connector.Pin Signal Description

P2.1 DC_CS Daughter card board select pin
P2.3
P2.5
P2.7 A0 Address line from processor

P2.9 A1 Address line from processor
P2.11 A2 Address line from processor
P2.13
P2.15
P2.17
P2.19 INTc Set jumper W3 to select BUSY or inverted signal

Note: All even numbered pins of P2 are tied to DGND.

Chapter 3

Digital Interface

to be applied to this pin.

The read (RD), conversion start (CONVST), and reset (RESET) signals to the
converter can be assigned to two different addresses in memory via jumper
settings. This allows for the stacking of up to two ADS8402EVMs and/or
ADS8412EVMs into processor memory. See Table 3-2 for jumper settings.
Note, the evaluation module does not allow the chip select (CS) line of the
converter to be assigned to different memory locations. It is therefore
suggested the CS line be grounded or wired to an appropriate signal of the
processor.

Digital Interface

3-1

Table 3-2.Jumper Settings for Decoder Outputs

Reference Designator Description

Set A[2..0] = 0x1 to generate RD pulse Installed

W2

Set A[2..0] = 0x2 to generate RD pulse Not installed Installed
Set A[2..0] = 0x3 to generate CONVST pulse Installed

W5

W4

†

Factory set condition

Set A[2..0] = 0x4 to generate CONVST pulse Not installed Installed
Set A[2..0] = 0x5 to generate RESET pulse Installed
Set A[2..0] = 0x6 to generate RESET pulse Not installed Installed

The data bus is available at connector P3, see Table 3-3 for pin out
information.

Table 3-3.Data Bus Connector P3

Connector.Pin Signal Description

P3.1 D0 Buffered Data Bit 0 (LSB)
P3.3 D1 Buffered Data Bit 1
P3.5 D2 Buffered Data Bit 2
P3.7 D3 Buffered Data Bit 3

P3.9 D4 Buffered Data Bit 4
P3.11 D5 Buffered Data Bit 5
P3.13 D6 Buffered Data Bit 6
P3.15 D7 Buffered Data Bit 7
P3.17 D8 Buffered Data Bit 8
P3.19 D9 Buffered Data Bit 9
P3.21 D10 Buffered Data Bit 10
P3.23 D11 Buffered Data Bit 11
P3.25 D12 Buffered Data Bit 12
P3.27 D13 Buffered Data Bit 13
P3.29 D14 Buffered Data Bit 14
P3.31 D15 Buffered Data Bit 15

Note: All even numbered pins of P3 are tied to DGND.

Jumper Settings

1-2 2-3

†

Not installed

†

Not installed

†

Not installed

This evaluation module provides direct access to all the analog-to-digital
converter control signals via connector J3, see Table 3-4.

Table 3-4.Pinout for Converter Control Connector J3

Connector.Pin Signal Description

J3.1 CS Chip select pin. Active low
J3.3 RD Read pin. Active low
J3.5 CONVST Convert start pin. Active low
J3.7 BYTE Byte mode pin. Used for 8-bit buses.
J3.9 RESET Reset pin. Active low.

J3.11 BUSY Converter status output. High when a conversion is in progress.

Note: All even numbered pins of J3 are tied to DGND.

3-2

Chapter 4

Power Supply Requirements

The EVM accepts four power supplies.

- A dual ±Vs dc supply for the dual supply op-amps. Recommend ±7 Vdc

supply.

- A single +5-Vdc supply for the analog section of the board (A/D +

Reference).

- A single +5-V or +3.3-Vdc supply for the digital section of the board (A/D

+ address decoder + buffers).

There are two ways to provide these voltages.

1) Wire in the voltages at test points on the EVM. See Table 4-1.

Table 4-1.Power Supply Test Points

Test Point Signal Description

TP14 +BVDD Apply +3.3 V or +5 V. See ADC data sheet for full range.
TP11 +AVCC Apply +5 Vdc.
TP12 +VA Apply +7 Vdc. Positive supply for amplifier.
TP13 -VA Apply –7 Vdc. Negative supply for amplifier.

2) Use the power connector J1 and derive the voltages elsewhere. The
pinout for this connector is sho wn in Table 4-2. If using this connector, set
the W1 jumper to connect +3.3VD or +5VD from connector to +BVDD.
Short between pins 1-2 to select +5VD or short between pins 2-3 to select
+3.3VD as the source for the digital buffer voltage supply (+BVDD).

Table 4-2.Power Connector, J1, Pinout

Signal Power Connector - J1 Signal

+VA(+7V) 1 2 –VA (–7V)

+5VA 3 4 N/C

DGND 5 6 AGND

N/C 7 8 N/C

+3.3VD 9 10 +5VD

Power Supply Requirements

4-1

4-2

Chapter 5

Using the EVM

The ADS8402/ADS8412EVM serves three functions:

1) As a reference design

2) As a prototype board

3) As a software test platform

Topic Page

5.1 As a Reference Board 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 As a Prototype Board 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 As a Software Test Platform 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Using the EVM

5-1

As a Reference Board

5.1 As a Reference Board

As a reference design, the ADS8402/ADS8412EVM contains the essential
circuitry to showcase the analog-to-digital converter. This essential circuitry
includes the input amplifier, reference circuit, and buffers. The EVM analog
input circuit is optimized for 100-kHz sine wave. Therefore, users may need
to adjust the resistor and capacitor values of the A/D input circuit. In ac-type
applications where signal distortion is a concern, polypropylene capacitors
should be used in the signal path.

5.2 As a Prototype Board

As a prototype board, the buffer circuit consists of resistor pads for configuring
the input as either single-ended or differential input. The input circuit can be
modified to accommodate user prototype needs, whether it be evaluating
another differential amplifier or limiting noise for best performance. The
analog, power, and digital connectors can be made to plug into a standard

0.1 in. breadboard or cables made up to interface directly to an FPGA or
processor.

5.3 As a Software Test Platform

As a software test platform, connectors P1, P2, and P3, plug into the parallel
interface connectors of the 5-6K interface card. The 5-6K interface card sits
on the C5000 and C6000 digital signal processor starter kit (DSK). The
ADS8402/ADS8412EVM is then mapped into the processor’s memory space.
This card also provides an area for signal conditioning. This area can be used
to install application circuit(s) for digitization by the ADS8402/ADS8412
analog-to-digital converter. See the 5-6K interface card user’s guide
(SLAU104) for more information.

The ADS8402/ADS8412EVM provides a simple platform for interfacing to the
converter. The EVM provides standard 0.1-in. headers and sockets to wire into
prototype boards. The user only needs to provide three address lines (A2, A1,
A0) and address valid line (DC_CS) to connector P2. To choose which address
combinations generates RD, CONVST, and RESET, set jumpers as shown in
Table 4-2. The recall chip select (CS) signal is not memory-mapped or tied to
P2; therefore, it must be controlled via a general purpose pin or shorted to
ground at J 3 pin 1. If address decoding is not required, the EVM provides direct
access to converter data bus via P3 and control via J3.

5-2

Chapter 6

ADS8402/ADS8412EVM BOM, Layout, and

Schematic

This chapter contains the ADS8402/ADS8412EVM bill of materials, the
layouts, and the schematics.

Topic Page

6.1 ADS8402/ADS8412EVM Bill of Materials 6-2. . . . . . . . . . . . . . . . . . . . . . . . .

6.2 ADS8402/ADS8412EVM Layout 6-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3 ADS8402/ADS8412EVM Schematic 6-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ADS8402/ADS8412EVM BOM, Layout, and Schematic

6-1

ADS9393EVM Bill of Materials

6.1 ADS9393EVM Bill of Materials

Table 6-1 contains a complete bill of materials for the
ADS8402/ADS8412EVM. The schematic diagram is also provided for
reference. Contact the Product Information Center or e-mail

[e-mail] for questions regarding this EVM.

Table 6-1.ADS8402/ADS8412EVM Bill Of Materials

Item

QTY Value Designator Footprint Mfg Mfg’s Part Number Description

No.

1 2 0 Ω R15, R21 805 Panasonic - ECG

2 2 24.9 Ω R12, R13 805 Panasonic - ECG

3 3 100 Ω R5, R14, R25 805 Panasonic - ECG

4 1 910 Ω R4 805 Panasonic - ECG

5 3 1 kΩ R1, R7, R10 805 Panasonic - ECG

6 5 10 kΩ R16 - R20 603 Panasonic - ECG

7 1 10 kΩ R24 805 Panasonic - ECG

8 6 NI R6, R8, R11,

R2, R3, R22

9 1 49.9 Ω R23 805 Panasonic - ECG

10 4 1 nF C3, C5, C11,

C23

11 2 68 pF C34, C35 TH WIMA FKP2 68/100/1 68-pF polypropylene

12 1 6800 pF C17 TH WIMA FKP2 6800/100/1 6800-pF polypropylene

13 10 0.01 µF C13, C21, C41,

C44, C46, C48,
C53, C56, C65,
C50

14 4 0.01 µF C10, C18, C20,

C66

15 2 0.01 µF C4, C26 1206 Kemet or

16 15 0.1 µF C8, C25, C40,

C42, C43, C47,
C51, C52, C54,
C55, C57, C58,
C62, C63, C64

17 7 0.1 µF C7, C9, C15,

C22, C32, C36,
C45

18 6 1 µF C16, C31, C33,

C37, C59, C60

19 2 1 µF C2, C28 1206 Kemet or

20 4 10 µF C1, C6, C12,

C19

21 1 10 µF C49 3528 Kemet or

805 Not Installed Not Installed

1206 Kemet or

603 Kemet or

805 Kemet or

603 Kemet or

805 Kemet or

805 Kemet or

1206 Panasonic - ECG

or Alternate

or Alternate

or Alternate

or Alternate

or Alternate

or Alternate

or Alternate

or Alternate

Alternate

Alternate

Alternate

Alternate

Alternate

Alternate

Alternate

Alternate

or Alternate

Alternate

ERJ-6GEY0R00V RES 0 Ω 1/8 W 5% 0805

SMD

ERJ-6ENF24R9V RES 24.9 Ω 1/10 W 1%

0805 SMD

ERJ-6ENF1000V RES 100 Ω 1/10 W 1%

0805 SMD

ERJ-6GEYJ911V RES 910 Ω 1/8 W 5%

0805 SMD

ERJ-6ENF1001V RES 1 kΩ 1/10 W 1%

0805 SMD

ERJ-3EKF1002V RES 10 kΩ 1/16 W 1%

0603 SMD

ERJ-6ENF1002V RES 10 kΩ 1/10 W 1%

0805 SMD

ERJ-6ENF49R9V RES 49.9 Ω 1/10 W 1%

0805 SMD

C1206C102J5GACTU Capacitor 1000 pF 50-V

ceramic NPO 1206

capacitor

capacitor

C0603C103J5RACTU Capacitor 10000 pF 50-V

ceramic X7R 0603

C0805C103K5RACTU Capacitor 10000 pF 50-V

ceramic X7R 0805

C1206C103J5RACTU Capacitor 10000 pF 50-V

ceramic X7R 1206

C0603C104K3RACTU Capacitor 0.1 µF 25-V

ceramic X7R 0603

C0805C104J5RACTU Capacitor 0.10 µF 50-V

ceramic X7R 0805

C0805C105K4RACTU Capacitor 1 µF 16-V

ceramic X7R 0805

C1206C105K3RACTU Capacitor 1 µF 25-V

ceramic X7R 1206

ECJ-3YB1C106M Capacitor 10 µF 16-V

ceramic X5R 1206

T491B106K016AS Capacitor TANT 10 µF

16 V 10% SMT

6-2

ADS9393EVM Bill of Materials

Item

QTY Value Designator Footprint Mfg Mfg’s Part Number Description

No.

22 4 10 µF C14, C24, C27,

23 1 22 µF C30 805 TDK Corporation C2012X5R0J226M Capacitor CER 22 µF

24 3 NI C38, C39, C61 805
25 2 1 Ω RP1, RP3 CTS_742 CTS Corporation 742C163102JTR RES array 1 Ω 16TERM

26 1 100 Ω RP2 CTS_742 CTS Corporation 742C163101JTR RES array 100 Ω 16TRM

27 1 10 kΩ R9 BOURNS_3

28 4 L1, L2, L3 1206 MURATA ERIE BLM31PG601SN1L Chip ferrite beads- 600 Ω

29 2 U1, U3 3-SOT-23 Texas

30 1 U2 8-SOP(D) Texas

31† 1 U4 socket_48QFPTexas

32 1 OPA627AU U8 8-SOP(D) Not installed Not installed Amplifier
33 1 NI U9 8-SOP(D) Footprint for 8-pin SOIC

34 1 U10 5-SOT

35 1 U11 16-TSSOP

36 3 U5, U6, U7 20-TSSOP

37 1 5X2X.1 J1 5X2X.1_SM

38 1 6X2X.1 J3 6X2X.1_SM

39 2 SMA_PCB

40 2 10X2X.1 P1, P2 10X2X.1_S

41 1 16X2X.1_S

42 1 SJP2 SJP3 SJP2 Not installed Not installed Pad 2 position jumper
43 3 SJP3 SJP2, SJP4,

44 1 SW-PB S1 EVQ-PJ Panasonic EVQ-PJU04K Switch
45 5 3POS_JU

46 14 TP_.025 TP1 - TP14 test_point2 Keystone

_MT

MT_plug_&

_pg_

_socket

MPER

C29

J2, J4 SMA_JACK AMPHENOL 901-144-4 MaCom #5002-5003-10

P3 16X2X.1_S

SJP5

W1 - W5 3pos_jump Samtec TSW-103-07-L-S 3 position jumper 0.1”

6032 Panasonic -

2X4W

(DBV)

(PW)

(PW)

T_socket

T_plug_&_s

_pg__

ocket

MT_plug_&_

_pg__
socket

MT_plug_&_

_pg__
socket

SJP3 Not installed Not installed Pad 3 postion jumper

ECG or Alternate

Bourns 3214W-1-103E TRIMPOT 10 kΩ 4 mm

Instruments

Instruments

Instruments

Texas
Instruments

Texas
Instruments

Texas
Instruments

Samtec TSM-105-01-T-D-V-P 0.025” SMT plug - top

Samtec

Samtec

Samtec

Electronics

ECS-T1EC106R Capacitor 10 µF 25-V

tantalum TE SMD

6.3 V X5R 20% 0805

8RES SMD

8RES SMD

top ADJ SMD

at 100 MHz

REF3040AIDBZT REF3040 50 ppm/°C,

50 µA in SOT23-3
CMOS voltage reference

THS4503ID High-speed

fully-differential amplifiers

ADS8402IPFBT† ADS8402 16-bit

1.25 MSPS

reference that operates
from +5V.

SN74AHC1G04DBVR Single inverter gate

SN74AHC138PWR 3-line to 8-line decoder /

demultiplexer

SN74AHC245PWR Octal bus transceiver, tri

state

side of PWB

SSW-106-22-S-D-VS 0.025” SMT socket -

bottom side of PWB

TSM-106-01-T-D-V-P 0.025” SMT plug - top

side of PWB

/ Amphenol #901-144

SSW-110-22-S-D-VS 0.025” SMT socket -

bottom side of PWB

TSM-110-01-T-D-V-P 0.025” SMT plug - top

side of PWB

SSW-116-22-S-D-VS 0.025” SMT socket –

bottom side of PWB

TSM-116-01-T-D-V-P 0.025” SMT plug – top

side of PWB

spacing

5000K–ND Test point-single 0.025”

pin

Note: On ADS8412EVM, the ADS8412IPFBT is installed instead of ADS8402IPFBT.

ADS8402/ADS8412EVM BOM, Layout, and Schematic

6-3

ADS8402/ADS8412EVM Layout

6.2 ADS8402/ADS8412EVM Layout

Figure 6-1.Top Layer—Layer 1

Figure 1.

6-4

Figure 6-2.Ground Plane—Layer 2

ADS8402/ADS8412EVM Layout

ADS8402/ADS8412EVM BOM, Layout, and Schematic

6-5

ADS8402/ADS8412EVM Layout

Figure 6-3.Power Plane—Layer 3

6-6

Figure 6-4.Bottom Layer—Layer 4

ADS8402/ADS8412EVM Layout

ADS8402/ADS8412EVM BOM, Layout, and Schematic

6-7

ADS8402/ADS8412EVM Schematic

6.3 ADS8402/ADS8412EVM Schematic

The following pages contain the schematic for the ADS8402/ADS8412EVM.

6-8

D

6

Revision History

REV ECN Number Approved

54321

C

2

4

6

8

10

12

14

16

18

20

22

24

26

28

2

4

6

8

10

12

14

16

18

20

22

24

26

1

3

5

7

9

11

13

15

17

19

21

23

17

B_DB8

19

B_DB9

25

21

23

25

27

B_DB10

B_DB11

B_DB12

B_DB13

P3

1

3

5

7

9

11

13

15

B_DB0

B_DB1

B_DB2

B_DB3

B_DB4

B_DB5

B_DB6

B_DB7

B

30

32

28

30

32

27

29

31

ADC Data Bus

29

31

B_DB14

B_DB15

A

A

REV:

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TITLE:

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DATE: 22-Oct-2003

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BlockDiagram.sch

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FILE: SIZE:

B_DB[15...0]

BUSY

B_RD
B_CS

+AVCC

B_DB[15...0]

DB[15...0]

B_RESET

B_BYTE

B_CONVST

+VA

-VA

+BVDD

INTc
A2
A1
A0
DC_CS

B_BUSY
RESET
BYTE
CONVST
RD
CS

CSRDCONVST

123456789

J3

BYTE

RESET

10

B_BUSY

11

12

DC_CS

A0A1A2

1 2

3 4

5 6

7 8

ADC Control

P2

INTc

9 10

11 12

13 14

15 16

17 18

19 20

Parallel Control

DB[15...0]

BUSY

B_RESET
B_BYTE
B_CONVST
B_RD
B_CS

-IN

+IN

Analog-to-Digital Converter

EXT_REF

DB[15..0]

Power & Digital Buffer

TP13

TP12

J2

J4

P1

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15 16

17 18

19 20

Analog Input

TP11

J1

TP14

+BVDD

W1

TP10

+5VD

AGND

1 2

3 4

5 6

7 8

9 10

+VA -VA

DGND

+3.3VD

+5VA

TP9

1 2 3 4 56

D

C

B

A

D

BUSY

B_CS

B_RD

B_BYTE

B_CONVST

B_RESET

6

Revision History

B_CS

B_RD

B_CONVST

B_BYTE

B_RESET

REV ECN Number Approved

+5VCC

C53

C51

54321

C54

+5VCC

0.01uF

0.1uF

0.1uF

C50

.01uF

+VBD

C21

0.01uF

C43

0.1uF

C

+VBD

C8

0.1uF

DB[15...0]

DB[15...0]

C13

0.01uF

+VBD

C55

0.1uF

C62

BUSY

DB0

DB1

DB2

DB3

DB4

DB5

DB6

0.1uF

33

36

34

C65

35

0.01uF

+VBD

BUSY

BDGND

+VBD

37

RESET

38

BYTE

39

CONVST

40

RD

41

CS

42

+VA

43

AGND

44

AGND

45

+VA

46

REFM

47

REFM

48

REFIN1REFOUT2NC3+VA4AGND5+IN6-IN7AGND8+VA9+VA10AGND11AGND

U4

DB7

ADS8402/ADS8412

C56

0.01uF

25

DB726DB627DB528DB429DB330DB231DB132DB0

BDGND

+VBD

24

DB8

23

DB9
DB10
DB11
DB12
DB13
DB14
DB15
AGND
AGND
+VA

12

C46

0.01uF

DB8

22

DB9

21

DB10

20

DB11

19

DB12

18

DB13

17

DB14

16

DB15

15
14
13

+5VCC

B

C52

0.1uF

C44

0.01uF

A

A

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Analog-to-Digital Converter

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23

C40

0.1uF

+5VCC

+5VCC

C41

0.01uF

C47

0.1uF

0

R15

2

31

C49

10uF

+

C48

0.01uF

+5VCC

C42

0.1uF

SJP2

2

3 1

C17

6800pF

SJP5

C38

C39

C36

0.1uF

C59

1uF

-VCC

R14

100

C32

6

U8NI

8

3

2

0.1uF

R2

5

1

C60

1uF

7 4

+VCC

NI

0

R21

C61

NI

C15

R13

0.1uF

NI

25

R12

NI

25

C7

0.1uF

C37

+VCC

1uF

910

R11

NI

100

R3

2

3 1

SJP4

C18

+5VCC

1

2

NC

+VIN

U9

3

GND

IN1OUT

U3

REF3040

2

0.01uF

EXT_REF

C45

0.1uF

3

4

EN

GND

NC5VREF

NI

6NC7NC8

C30

22uF

R23

50

NI

68pF

C35

1k

R10

R4

R5

5

U2

36

+VCC

7

NC

+

812

TP4

U1

VOUT-

3

GND

IN1OUT

4

THS4503

-VCC

VOUT+

-

VOCM

C33

1uF

REF3040

2

C31

1uF

-VCC

12

SJP3

1k

C34

R7

R1

R8

NI

R22

R6

NI

68pF

1k

NI

1 2 3 4 5 6

+5VCC

R9

+5VCC

+IN

D

C

B

C16

1uF

10k

-IN

A

D

C

B

A

A

REV:

33

SHEET: OF:

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Revision History

B_DB[17...0]

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DATE: 22-Oct-2003

B_DB[17...0]

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Power & Digital Buffer

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C5

1nF

54321

C4

0.01uF

TP3

+VCC

L2

BLM21AJ601SN1L

+VA

TP2

C28

1uF

10uF

C29

+

C6

10uF

C3

1nF

C58

0.1uF

B_DB0

B_DB1

B_DB2

B_DB3

B_DB7

B_DB4

B_DB6

B_DB5

B1B2B3B4B5B6B7

12

11

1 16

2 15

3 14

4 13

5

6

DB5

DB4

DB3

DB2

DB1

DB0

10

7

DB6

9

8

DB7

B8

GND

SN74AHC245PWR

1K

BLM21AJ601SN1L

-VCC

+VBD

+VBD

VCC

/OE

U7

DIRA1A2A3A4A5A6A7A8

RP3

C26

0.01uF

TP1

C2

1uF

C27

10uF

+

L1

C1

10uF

DB[17...0]

-VA

DB[17...0]

+VBD

C57

0.1uF

VCC

/OE

DIRA1A2A3A4A5A6A7A8

U6

+VBD

RP1

B_DB13

B_DB12

B_DB11

B_DB10

B_DB9

B_DB8

B1B2B3B4B5B6B7

12

11

1 16

2 15

3 14

4 13

5

6

DB13

DB12

DB11

DB10

DB9

DB8

B_DB15

B_DB14

B8

GND

SN74AHC245PWR

9

10

1K

8

7

DB15

DB14

+VBD

A0A2A1

DC_CS

R24

10k

DC_CS

+VBD

A0A1A2

6

3

5

U11

A1B2C

G1

G2A4G2B

+VBD

VCC

16

Y015Y114Y213Y312Y411Y510Y69Y7

C63

0.1uF

GND

8

7

Engineer:

FILE: SIZE:

SN74AHC138PWR

TP6

+5VCC

W2

1

3

2

C11

1nF

CSRDCONVST

BYTE

RESET

C23

1nF

C10

0.01uF

C9

0.1uF

TP5

TP8

+VBD

C20

0.01uF

C22

0.1uF

TP7

+VBD

R18

10k

R19

10k

R20

10k

R16

10k

R17

10k

W5

1

3

2

INTc

W4

RESET#

S1

C66

R25

0.01uF

100

W3

BYTE

RESET

BUSY

B8

GND

C64

0.1uF

SN74AHC245PWR

+VBD

U10

53

SN74AHC1G04DBV

C14

10uF

+

L3

BLM21AJ601SN1L

C24

10uF

+

L4

+VBD

C25

0.1uF

CSRDCONVST

B1B2B3B4B5B6B7

VCC

/OE

DIRA1A2A3A4A5A6A7A8

U5

BLM21AJ601SN1L

+AVCC

9

12

10

1 16

B_CS

B_CS

2 15

3 14

B_CONVST

B_RD

B_RD

B_CONVST

4 13

5

B_BYTE

B_RESET

B_BYTE

11

6

8

7

B_RESET

100

B_BUSY

B

C12

10uF

C19

10uF

RP2

+BVDD

D

C

2 4

1 2 3 4 56

A