Texas Instruments ADS8364, 65MEVM User Manual

User's Guide

SLAU189 – September 2006

ADS8364/65MEVM

This user's guide describes the characteristics, operation, and use of the
ADS8364/65MEVM 16-bit, parallel analog-to-digital converter evaluation module
(EVM). A complete circuit description, a schematic diagram, and bill of materials is
included.

Contents

1 EVM Overview ...................................................................................... 1

2 Introduction .......................................................................................... 2

3 Analog Interface .................................................................................... 2

4 Digital Interface ..................................................................................... 4

5 Power Supplies ..................................................................................... 6

6 EVM Operation ...................................................................................... 6

7 EVM Bill of Materials, Assembly Drawing, and Schematic .................................... 7

8 Related Documentation From Texas Instruments ............................................ 10

List of Figures

1 Channel A0 Input Circuit ........................................................................... 3

2 Channel A1 Input Circuit ........................................................................... 4

3 ADS8364/654MEVM Assembly Drawing ........................................................ 9

1 EVM Overview

1.1 Features

List of Tables

1 Typical Analog Input Buffer Circuit Values ...................................................... 3

2 Header/Socket Combinations at J5 .............................................................. 5

3 J1 Pinout and Functions ........................................................................... 6

4 JP1 Pinout ........................................................................................... 6

5 ADS8364/65MEVM Jumpers ...................................................................... 7

6 ADS8364/65MEVM Bill of Materials ............................................................. 7

• Full-featured evaluation board for the ADS8364 and ADS8365 250-kHz, 16-bit, 6-channel,
simultaneous-sampling, analog-to-digital converter

• Analog inputs can be configured as single-ended or differential

• Modular design allows direct connection to various DSP platforms through the 5-6K and HPA-MCU

Interface Boards

• Built-in reference

• High-speed parallel interface

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Introduction

2 Introduction

The ADS8364 and ADS8365 are high-speed, low-power, 6-channel, 16-bit A/D converters that operate
from independent +5-V Avdd and Dvdd supplies. Internal buffer circuits powered from 3.3-V to 5.5-V BVdd
supplies allow for mixed logic level operation without additional level translation.

The six input channels contain fully differential sample-and-hold circuits which are divided into three pairs
(A, B, and C). Each channel pair has a hold signal (HOLDA, HOLDB, and HOLDC) which, when strobed
together, provides simultaneous sampling on all six analog inputs. The devices accept analog input
voltages in the range of –V
circuit is used in the analog front-end circuitry (see Figure 1 ).

Conversion time for the ADS8364 and ADS8365 is 3.2 µ s when a 5-MHz external clock is used. The
corresponding acquisition time is 800 ns. To achieve maximum output rate (250 kHz per channel, effective

1.5-MSPS throughput max), the read function can be performed during the start of the next conversion.

3 Analog Interface

The analog input to the EVM is divided in two parts. Connector J4 provides access to input channels A0
and A1 through two different amplifier circuit configurations. The input buffer configuration of channel A0
presents a typical front-end circuit for the A/D converter. Its function is to provide level and impedance
adaptation of the input signal. The input to channel A1 is a bipolar configuration using the INA159 to
accommodate ± 10-V input signals. Connector J3 provides access to the remaining analog input channels
through simple R/C filters.

3.1 Analog Input – Channel A0

The analog input to the ADS8364/65MEVM board for channel A0 is composed of the dual OPA2132
operational amplifier and its associated circuitry as shown in Figure 1 . The OPA2132 is powered from the
± 12-V analog supply, and arranged as an inverting amplifier with a gain of 1. The internal +2.5-V
reference voltage of the ADS8364 or ADS8365 is applied to the noninverting input of the OPA2132 to
provide input bias.

to +V

REF

. The parts also accept bipolar input ranges when a level shift

REF

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Analog Interface

NOTE: Components marked NI are NOT INSTALLED.

This configuration allows single-ended signals of ± 2.5 V (+5 Vpp) to be applied to either input of channel
A0 (J2 pin 1 or 3 referenced to pin 2). The input also can be applied to connector J4 (not shown) pins 2 or
4, referenced to analog ground.

3.2 Bipolar Input to Channel A0

By changing components and setting the appropriate jumper, it is possible to configure the input buffer to
accept bipolar input voltages. Table 1 is related to the schematic presented in Figure 1 and represents just
a few of the possible input configurations.

Input Voltage R3 R2 R1 R4 W2

Refer to Figure 1 Default open 5k Ω 5k Ω 5 k Ω 1–2

0 – +5

0 – 2.5 5 k Ω 5 k Ω open 5 k Ω 2–3

– 2.5 – +2.5 20 k Ω 4 k Ω 20 k Ω 4 k Ω 2–3

– 5 – +5 20 k Ω 4 k Ω 10 k Ω 2 k Ω 2–3

– 10 – +10 20 k Ω 4 k Ω 5 k Ω 1 k Ω 2–3

Figure 1. Channel A0 Input Circuit

Table 1. Typical Analog Input Buffer Circuit Values

R28 R25 R24 R29 W1

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Digital Interface

The output from the buffer stage in each case applies 0-5 V to the CHA0(+) input when the applied signal
is connected to J2 pin 1 or J4 pin 2. The applied signal is directed to the CHA0(-) input when connected
via J2 pin 3 or J4 pin 4.

When operating the ADS836x with single-ended signals, it is important to keep the unused ADC input
biased to +2.5 V. This is easily accomplished on the EVM by changing the components associated with
either the inverting or noninverting input only, leaving the default component values shown in Table 1 on
the unused input. For example, to achieve a bipolar input range of ± 10 V on CHA0(+), use the component
values shown for R1–R4 and move the shunt on W2 position 2-3. Components R24, R25, R28, and R29
and the shunt on W1 should remain in the default conditions shown in Table 1 .

3.3 Analog Input – Channel A1

The analog input to the ADS8364/65MEVM board for channel A1 is composed of the INA159 difference
amplifier and the associated circuitry as shown in Figure 2 . The INA159 is powered from the +5-V analog
supply, and arranged as a noninverting amplifier with a gain of 0.2. The internal +2.5-V reference voltage
of the ADS836x is applied to both REF1 and REF2 pins of the INA159 to provide a direct ± 10-V interface
with built-in level translation to the noninverting input of channel A1.

Figure 2. Channel A1 Input Circuit

3.4 Analog Inputs –Channels B0/B1 and C0/C1

The analog inputs to the remaining ADS836x input channels are routed to connector J3 and configured
with simple R/C filters only. This configuration allows the EVM user to apply any customized input circuit to
the data converter. Connector J3 is composed of a male/female pass-through combination of pin header
and socket with industry standard 0.1-inch centers.

When the ADS8364/65MEVM is used in combination with the 5-6K Interface Board or HPA-MCU Interface
Board, the DAP Signal Conditioning Board (SLAU105 ) can be used to drive the remaining input channels.

4 Digital Interface

The ADS8364/65MEVM is designed for easy interfacing to multiple control platforms. Jumper options are
provided on the EVM to allow control over the state of Chip Select pin ( CS) as well as the operating mode
pins (A0–A2), the Reset pin ( RST), and the Conversion Start strobes (HOLD A, HOLDB, and HOLDC).

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4.1 Parallel Control

Digital Interface

Jumpers W4 and W6 control the signals applied to A0, A1, A2, and CS. In the factory default mode, W6 is
closed by means of a shunt jumper. The Ax and CS pins are controlled by the signals applied to J5 (top or
bottom side). When used with either the 5-6K or HPA-MCU Interface Boards, these control signals are
associated with the host processors address bus.

By removing the shunt jumper located at W6, the A0, A1, and A2 pins are controlled by shunt jumpers
placed on W4. The CS pin is routed to J5.1, which requires the application of an active-low Chip Select
signal. A simple shunt jumper placed across J5 pins 1-2 can be used to force the CS pin to ground if
desired.

Samtec part numbers SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient 10-pin,
dual-row, header/socket combination at J5 (Table 2 ). This header/socket provides access to the digital
control pins of the EVM. Consult Samtec at www.samtec.com or 1-800-SAMTEC-9 for a variety of mating
connector options.

Table 2. Header/Socket Combinations at J5

Pin Number Signal Description

J5.1 DC_CSa Daughter Card Chip Select – active-low signal used to access the EVM
J5.3 DC_AWE Write Strobe – signal not used on the ADS8364/65M EVM
J5.5 DC_ARE Read Strobe – active-low signal used to access parallel data
J5.7 EVM_A0 EVM Address line 0 – used with U3 to control A0
J5.9 EVM_A1 EVM Address line 1 – used with U3 to control A1
J5.11 EVM_A2 EVM Address line 2 – used with U3 to control A2
J5.13 EVM_A3 EVM Address line 3 – used with U3 and U6 to control CS
J5.15 EVM_A4 EVM Address line 4 – not used
J5.17 DC_TOUT Timer Input – optional CLK input used with W8
J5.19 DC_INTa Interrupt Output to Host Processor – connects to the ADC EOC pin

4.2 Parallel Data

The ADS8364/65MEVM uses Samtec part numbers SSW-116-22-F-D-VS-K and TSM-116-01-T-DV-P to
provide a convenient 16-pin, dual-row header/socket combination at J6. This header/socket combination
provides access to the parallel data pins of the ADS7864. Data line D0 is connected to J6 pin 1. Data
lines 1–15 are located on pins 3–31, respectively. Even pin numbers 2–32 are connected to digital ground.

4.3 GPIO/Control Options

Samtec part numbers SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a 10-pin, dual-row,
header/socket combination at J1 to facilitate general-purpose input/output (GPIO) control options to the
ADS836x device installed on the EVM. Table 3 describes the functions and pinout of J1.

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