SBAS139E – SEPTEMBER 2000 – REVISED SEPTEMBER 2006
DESCRIPTION
The ADS8344 is an 8-channel, 16-bit, sampling
Analog-to-Digital (A/D) converter with a synchronous serial
interface. Typical power dissipation is 10mW at a 100kHz
throughput rate and a +5V supply. The reference voltage
(V
) can be varied between 500mV and VCC, providing a
REF
corresponding input voltage range of 0V to V
device includes a shutdown mode that reduces power dissipation to under 15µW. The ADS8344 is tested down to 2.7V
operation.
Low power, high speed, and an on-board multiplexer make
the ADS8344 ideal for battery-operated systems such as
personal digital assistants, portable multi-channel data loggers, and measurement equipment. The serial interface also
provides low-cost isolation for remote data acquisition. The
ADS8344 is available in a QSOP-20 or SSOP-20 package
and is ensured over the –40°C to +85°C temperature range.
REF
. The
CH0
CH1
CH2
CH3
COM
ADS8341
ADS8343
4-Channel
Multiplexer
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
V
REF
ADS8344
ADS8345
8-Channel
Multiplexer
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
to GND ........................................................................ –0.3V to +6V
CC
Analog Inputs to GND ............................................ –0.3V to +V
Digital Inputs to GND ........................................................... –0.3V to +6V
Power Dissipation .......................................................................... 250mW
Maximum Junction Temperature................................................... +150°C
Operating Temperature Range ........................................ –40°C to +85°C
Storage Temperature Range ......................................... –65°C to +150°C
Lead Temperature (soldering, 10s)............................................... +300°C
NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
(1)
+ 0.3V
CC
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments
recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ADS8344E8±0.05–40°C to +85°CDBQQSOP-20DBQADS8344ERails, 56
ADS8344N"""DBSSOP-20DBADS8344NRails, 68
ADS8344EB6±0.024–40°C to +85°CDBQQSOP-20DBQADS8344EBRails, 56
ADS8344NB"""DBSSOP-20DBADS8344NBRails, 68
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI web site at
www.ti.com.
ACCURACY GAIN ERROR TEMPERATUREPACKAGEDRAWINGORDERINGTRANSPORT
10SHDNShutdown. When LOW, the device enters a very
11V
12+V
13GNDGround
14GNDGround
15D
16BUSYBusy Output. Busy goes LOW when the D
17D
18CSChip Select Input. Active LOW. Data will not be clocked
19DCLKExternal Clock Input. The clock speed determines the
20+V
Ground reference for analog inputs. Sets zero code
voltage in single–ended mode. Connect this pin to ground
or ground reference point.
low-power shutdown mode.
Voltage Reference Input. See Electrical Characteristics
REF
Table for ranges.
Power Supply, 2.7V to 5V
CC
Serial Data Output. Data is shifted on the falling edge of
OUT
DCLK. This output is high impedance when CS is HIGH.
are being read and also when the device is converting.
The Output is high impedance when CS is HIGH.
Serial Data Input. If CS is LOW, data is latched on rising
No Missing Codes1415Bits
Integral Linearity Error86LSB
Offset Error±2±1mV
Offset Error Match1.24✻✻LSB
Gain Error±0.05±0.024%
Gain Error Match1.04✻✻ LSB
Noise20✻µVrms
Power-Supply Rejection+4.75V < V
No Missing Codes1415Bits
Integral Linearity Error128LSB
Offset Error±10.5mV
Offset Error Match1.24✻✻ LSB
Gain Error±0.05±0.024% of FSR
Gain Error Match14✻✻ LSB
Noise20✻µVrms
Power-Supply Rejection+2.7 < V
NOTES: (1) LSB means Least Significant Bit. With V
(PD1 = PD0 = 0) active or SHDN = GND.
= +2.7V, f
REF
= 100kHz, and f
SAMPLE
CLK
= 24 • f
= 2.4MHz, unless otherwise noted.
SAMPLE
ADS8344E, NADS8344EB, NB
REF
+VCC + 0.2
✻✻V
✻✻V
Negative Input–0.2+0.2✻✻V
< +3.3V3✻LSB
CC
DD
2.4✻MHz
When used with Internal Clock0.0242.0✻✻MHz
Data Transfer Only02.4✻✻MHz
VIN = 2.5Vp-p at 1kHz–90✻dB
= 2.5Vp-p at 1kHz86✻dB
IN
= 2.5Vp-p at 1kHz92✻dB
IN
= 2.5Vp-p at 10kHz100✻dB
IN
CC
f
= 12.5kHz2.5✻µA
SAMPLE
DCLK Static0.0013✻✻ µA
| I
| ≤ +5µA+V
IH
| I
| ≤ +5µA–0.3+0.8✻✻V
IL
IOH = –250µA+V
IOL = 250µA0.4✻V
• 0.75.5✻✻V
CC
• 0.8✻V
CC
✻✻V
Specified Performance2.73.6✻✻V
f
= 100kHz220✻µA
SAMPLE
Power-Down Mode
(3)
, CS = +V
equal to +2.5V, one LSB is 38µV. (2) First nine harmonics of the test frequency. (3) Auto power-down mode
REF
CC
3✻µA
(1)
4
ADS8344
SBAS139E
TYPICAL CHARACTERISTICS: +5V
CHANGE IN SIGNAL-TO-(NOISE+DISTORTION)
vs TEMPERATURE
–40–250205075100
Temperature (°C)
Delta from +25°C (dB)
0.2
0.0
–0.2
–0.4
–0.6
–0.8
0.4
fIN = 9.985kHz, –0.2dB
At TA = +25°C, +VCC = +5V, V
= +5V, f
REF
= 100kHz, and f
SAMPLE
DCLK
= 24 • f
SAMPLE
= 2.4MHz, unless otherwise noted.
FREQUENCY SPECTRUM
(4096 Point FFT; f
0
–20
–40
–60
–80
–100
Amplitude (dB)
–120
–140
–160
0 1020304050
SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-
100
90
(NOISE+DISTORTION) vs INPUT FREQUENCY
= 1.001kHz, –0.2dB)
IN
Frequency (kHz)
SNR
FREQUENCY SPECTRUM
(4096 Point FFT; f
0
–20
–40
–60
–80
–100
Amplitude (dB)
–120
–140
–160
0 1020304050
SPURIOUS-FREE DYNAMIC RANGE AND TOTAL
100
HARMONIC DISTORTION vs INPUT FREQUENCY
90
= 9.985kHz, –0.2dB)
IN
Frequency (kHz)
SFDR
–100
–90
80
70
SNR and SINAD (dB)
60
15.0
14.5
14.0
13.5
13.0
12.5
12.0
Effective Number of Bits
11.5
11.0
SINAD
101100
Frequency (kHz)
EFFECTIVE NUMBER OF BITS
vs INPUT FREQUENCY
101100
Frequency (kHz)
80
SFDR (dB)
70
NOTE: (1) First Nine Harmonics
of the Input Frequency
60
(1)
THD
101100
Frequency (kHz)
–80
THD (dB)
–70
–60
ADS8344
SBAS139E
5
TYPICAL CHARACTERISTICS: +5V (Cont.)
At TA = +25°C, +VCC = +5V, V
= +5V, f
REF
= 100kHz, and f
SAMPLE
DCLK
= 24 • f
= 2.4MHz, unless otherwise noted.
SAMPLE
2
1
0
–1
ILE (LSB)
–2
–3
–4
0000
3.0
2.5
2.0
INTEGRAL LINEARITY ERROR vs CODE
H
4000
8000
H
H
Output Code
WORST CASE CHANNEL-TO-CHANNEL
OFFSET MATCH vs TEMPERATURE
C000
DIFFERENTIAL LINEARITY ERROR vs CODE
3
2
1
0
DLE (LSB)
–1
–2
–3
FFFF
H
H
0000
H
4000
H
8000
H
C000
FFFF
H
H
Output Code
WORST CASE CHANNEL-TO-CHANNEL
2.0
GAIN MATCH vs TEMPERATURE
1.5
1.0
Offset Match (LSB)
1.5
1.0
–50–250255075100
Temperature (°C)
3
CHANGE IN OFFSET vs TEMPERATURE
2
1
0
–1
Delta from 25°C (LSB)
–2
–3
–50–250255075100
Temperature (°C)
Gain Match (LSB)
0.5
0.0
–50–250255075100
Temperature (°C)
1.0
CHANGE IN GAIN vs TEMPERATURE
0.5
0.0
Delta from 25°C (LSB)
–0.5
–50–250255075100
Temperature (°C)
6
ADS8344
SBAS139E
TYPICAL CHARACTERISTICS: +5V (Cont.)
At TA = +25°C, +VCC = +5V, V
= +5V, f
REF
= 100kHz, and f
SAMPLE
DCLK
= 24 • f
= 2.4MHz, unless otherwise noted.
SAMPLE
1.8
1.7
1.6
1.5
Supply Current (mA)
1.4
1.3
–50–250255075100
SUPPLY CURRENT vs TEMPERATURE
Temperature (°C)
POWER DOWN SUPPLY CURRENT
3.0
2.5
2.0
Supply Current (µA)
1.5
1.0
–50–250255075100
vs TEMPERATURE
Temperature (°C)
ADS8344
SBAS139E
7
TYPICAL CHARACTERISTICS: +2.7V
At TA = +25°C, +VCC = +2.7V, V
= +2.7V, f
REF
= 100kHz, and f
SAMPLE
DCLK
= 24 • f
SAMPLE
= 2.4MHz, unless otherwise noted.
FREQUENCY SPECTRUM
(4096 Point FFT; f
0
–20
–40
–60
–80
–100
Amplitude (dB)
–120
–140
–160
0 1020304050
SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-
100
90
80
(NOISE+DISTORTION) vs INPUT FREQUENCY
= 1.001kHz, –0.2dB)
IN
Frequency (kHz)
SNR
FREQUENCY SPECTRUM
(4096 Point FFT; f
0
–20
–40
–60
–80
–100
Amplitude (dB)
–120
–140
–160
0 1020304050
SPURIOUS-FREE DYNAMIC RANGE AND TOTAL
100
HARMONIC DISTORTION vs INPUT FREQUENCY
90
80
THD
(1)
= 9.985kHz, –0.2dB)
IN
Frequency (kHz)
SFDR
–100
–90
–80
70
SNR and SINAD (dB)
60
50
15
14
13
12
11
10
Effective Number of Bits
9
8
SINAD
101100
Frequency (kHz)
EFFECTIVE NUMBER OF BITS
vs INPUT FREQUENCY
101100
Frequency (kHz)
70
SFDR (dB)
60
NOTE: (1) First Nine Harmonics
of the Input Frequency
50
CHANGE IN SIGNAL-TO-(NOISE+DISTORTION)
2.0
fIN = 9.985kHz, –0.2dB
1.5
1.0
0.5
0.0
–0.5
–1.0
Delta from +25°C (dB)
–1.5
–2.0
–40–250205075100
101100
Frequency (kHz)
vs TEMPERATURE
Temperature (°C)
–70
–60
–50
THD (dB)
8
ADS8344
SBAS139E
TYPICAL CHARACTERISTICS: +2.7V (Cont.)
WORST CASE CHANNEL-TO-CHANNEL
GAIN MATCH vs TEMPERATURE
1.2
1.0
0.8
0.6
0.4
Gain Match (LSBS)
Temperature (°C)
–50–250255075100
0.3
0.2
0.1
0.0
–0.1
–0.2
–50–250255075100
CHANGE IN GAIN vs TEMPERATURE
Temperature (°C)
Delta from 25°C (LSB)
At TA = +25°C, +VCC = +2.7V, V
= +2.7V, f
REF
= 100kHz, and f
SAMPLE
DCLK
= 24 • f
= 2.4MHz, unless otherwise noted.
SAMPLE
3
2
1
0
ILE (LSB)
–1
–2
–3
0000
1.2
1.0
0.8
INTEGRAL LINEARITY ERROR vs CODE
H
4000
H
8000
H
Output Code
WORST CASE CHANNEL-TO-CHANNEL
OFFSET MATCH vs TEMPERATURE
C000
DIFFERENTIAL LINEARITY ERROR vs CODE
3
2
1
0
DLE (LSB)
–1
–2
–3
FFFF
H
H
0000
H
4000
8000
H
H
C000
FFFF
H
H
Output Code
0.6
0.4
Offset Match (LSBS)
0.2
0
–50–250255075100
Temperature (°C)
3
CHANGE IN OFFSET vs TEMPERATURE
2
1
0
Delta from 25°C (LSB)
–1
–50–250255075100
Temperature (°C)
ADS8344
SBAS139E
9
TYPICAL CHARACTERISTICS: +2.7V (Cont.)
At TA = +25°C, +VCC = +2.7V, V
= +2.7V, f
REF
= 100kHz, and f
SAMPLE
DCLK
= 24 • f
= 2.4MHz, unless otherwise noted.
SAMPLE
1.25
SUPPLY CURRENT vs TEMPERATURE
1.20
1.15
1.10
Supply Current (mA)
1.05
1.00
–50–250255075100
Temperature (°C)
3.0
2.5
2.0
1.6
1.5
1.4
1.3
1.2
Supply Current (mA)
1.1
1.0
2.53.03.54.04.55.0
POWER DOWN SUPPLY CURRENT
vs TEMPERATURE
f
SAMPLE
SUPPLY CURRENT vs +V
= 100kHz, V
REF
= +V
+V
SS
SS
(V)
SS
Supply Current (µA)
1.5
1.0
–50–250255075100
Temperature (°C)
10
ADS8344
SBAS139E
THEORY OF OPERATION
The ADS8344 is a classic Successive Approximation
Register (SAR) A/D converter. The architecture is based on
capacitive redistribution that inherently includes a sampleand-hold function. The converter is fabricated on a 0.6µs
CMOS process.
The basic operation of the ADS8344 is shown in Figure 1.
The device requires an external reference and an external
clock. It operates from a single supply of 2.7V to 5.25V. The
external reference can be any voltage between 500mV and
. The value of the reference voltage directly sets the
+V
CC
input range of the converter. The average reference input
current depends on the conversion rate of the ADS8344.
The analog input to the converter is differential and is
provided via an 8-channel multiplexer. The input can be
provided in reference to a voltage on the COM pin (which
is generally ground) or differentially by using four of the
eight input channels (CH0 - CH7). The particular configuration is selectable via the digital interface.
TABLE I. Single-Ended Channel Selection (SGL/DIF HIGH).
ANALOG INPUT
See Figure 2 for a block diagram of the input multiplexer on
the ADS8344. The differential input of the converter is
derived from one of the eight inputs in reference to the COM
pin, or four of the eight inputs. Table I and Table II show the
relationship between the A2, A1, A0, and SGL/DIF control
bits and the configuration of the analog multiplexer. The
control bits are provided serially via the DIN pin (see the
Digital Interface section of this data sheet for more details).
When the converter enters the hold mode, the voltage
difference between the +IN and –IN inputs is captured on
the internal capacitor array (see Figure 2). The voltage on
the –IN input is limited between –0.2V and 1.25V, allowing
the input to reject small signals that are common to both the
+IN and –IN input. The +IN input has a range of –0.2V to
+ 0.2V.
+V
CC
The input current on the analog inputs depends on the conversion rate of the device. During the sample period, the source
must charge the internal sampling capacitor (typically 25pF).
After the capacitor has been fully charged, there is no further
input current. The rate of charge transfer from the analog
source to the converter is a function of conversion rate.
TABLE II. Differential Channel Control (SGL/DIF LOW).
Single-ended
or differential
analog inputs
FIGURE 1. Basic Operation of the ADS8344.
+2.7V to +5V
ADS8344
1
CH0
2
CH1
3
CH2
4
CH3
5
CH4
6
CH5
7
CH6
8
CH7
9
COM
10
SHDN
+V
DCLK
CS
D
BUSY
D
OUT
GND
GND
+V
V
REF
20
CC
19
18
17
IN
16
15
14
13
12
CC
11
0.1µF
Serial/Conversion Clock
Chip Select
Serial Data In
Serial Data Out
+
1µF to 10µF
External
V
REF
1µF to 10µF1µF
ADS8344
SBAS139E
11
A2-A0
(1)
(shown 00o
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
NOTE: (1) See Truth T ables, Table I
and Table II for address coding.
)
B
SGL/DIF
(shown HIGH)
+IN
Converter
–IN
FIGURE 2. Simplified Diagram of the Analog Input.
REFERENCE INPUT
The external reference sets the analog input range. The
ADS8344 will operate with a reference in the range of
100mV to +VCC. Keep in mind that the analog input is the
difference between the +IN input and the –IN input, as
shown in Figure 2. For example, in the single-ended mode,
a 1.25V reference with the COM pin grounded, the selected
input channel (CH0 - CH7) will properly digitize a signal in
the range of 0V to 1.25V. If the COM pin is connected to
0.5V, the input range on the selected channel is 0.5V to
1.75V.
There are several critical items concerning the reference
input and its wide-voltage range. As the reference voltage is
reduced, the analog voltage weight of each digital output
code is also reduced. This is often referred to as the LSB
(Least Significant Bit) size and is equal to the reference
voltage divided by 65536. Any offset or gain error inherent
in the A/D converter will appear to increase, in terms of LSB
size, as the reference voltage is reduced. For example, if the
offset of a given converter is 2LSBs with a 2.5V reference,
then it will typically be 10LSBs with a 0.5V reference. In
each case, the actual offset of the device is the same,
76.3µV.
Likewise, the noise or uncertainty of the digitized output
will increase with lower LSB size. With a reference voltage
of 500mV, the LSB size is 7.6µV. This level is below the
internal noise of the device. As a result, the digital output
code will not be stable and will vary around a mean value by
a number of LSBs. The distribution of output codes will be
gaussian and the noise can be reduced by simply averaging
consecutive conversion results or applying a digital filter.
With a lower reference voltage, care should be taken to
provide a clean layout including adequate bypassing, a clean
(low-noise, low-ripple) power supply, a low-noise reference,
and a low-noise input signal. Because the LSB size is lower,
the converter will also be more sensitive to nearby digital
signals and electromagnetic interference.
The voltage into the V
input is not buffered and directly
REF
drives the Capacitor Digital-to-Analog Converter (CDAC)
portion of the ADS8344. Typically, the input current is
13µA with a 2.5V reference. This value will vary by
microamps depending on the result of the conversion. The
reference current diminishes directly with both conversion
rate and reference voltage. As the current from the reference
is drawn on each bit decision, clocking the converter more
quickly during a given conversion period will not reduce
overall current drain from the reference.
DIGITAL INTERFACE
The ADS8344 has a four-wire serial interface compatible
with several microprocessor families (note that the digital
inputs are over-voltage tolerant up to +5.5V, regardless of
+VCC). Figure 3 shows the typical operation of the ADS8344
digital interface.
Most microprocessors communicate using 8-bit transfers;
the ADS8344 can complete a conversion with three such
transfers, for a total of 24 clock cycles on the DCLK input,
provided the timing is as shown in Figure 3.
CS
t
DCLK
D
BUSY
D
OUT
1
A2S
IN
(START)
A1 A0
ACQ
81
AcquireIdleConversion
SGL/
PD1 PD0
DIF
14131211109 8 7654321 0Zero Filled...
15
(MSB)
818
(START)
(LSB)
181
AcquireIdleConversion
SGL/
A2SA1A0
DIF
PD1 PD0
15
(MSB)
14
FIGURE 3. Conversion Timing, 24-Clocks per Conversion, 8-Bit Bus Interface. No DCLK Delay Required with Dedicated
Serial Port.
12
ADS8344
SBAS139E
The first eight clock cycles are used to provide the control
byte via the D
pin. When the converter has enough
IN
information about the following conversion to set the input
multiplexer appropriately, it enters the acquisition (sample)
mode. After four more clock cycles, the control byte is
complete and the converter enters the conversion mode. At
this point, the input sample-and-hold goes into the Hold
mode. The next sixteen clock cycles accomplish the actual
A/D conversion.
Control Byte
See Figure 3 for placement and order of the control bits
within the control byte. Tables III and IV give detailed
information about these bits. The first bit, the “S” bit, must
always be HIGH and indicates the start of the control byte.
The ADS8344 will ignore inputs on the DIN pin until the
START bit is detected. The next three bits (A2-A0) select
the active input channel or channels of the input multiplexer
(see Tables I and II and Figure 2).
BIT 7BIT 0
(MSB)BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1(LSB)
SA2A1A0—SGL/DIF PD1PD0
TABLE III. Order of the Control Bits in the Control Byte.
BITNAMEDESCRIPTION
7SStart Bit. Control byte starts with first HIGH bit on
6 - 4A2 - A0Channel Select Bits. Along with the SGL/DIF bit,
2SGL/DIFSingle-Ended/Differential Select Bit. Along with bits
1 - 0 PD1 - PD0 Power-Down Mode Select Bits. See Table V for
D
.
IN
these bits control the setting of the multiplexer input,
see Tables I and II.
A2 - A0, this bit controls the setting of the multiplexer
input, see Tables I and II.
details.
TABLE IV. Descriptions of the Control Bits within the
Control Byte.
The SGL/DIF-bit controls the multiplexer input mode: either in single-ended mode, where the selected input channel
is referenced to the COM pin, or in differential mode, where
the two selected inputs provide a differential input.
See Tables I and II and Figure 2 for more information. The
last two bits (PD1 - PD0) select the power-down mode and
Clock mode, as shown in Table V. If both PD1 and PD0 are
HIGH, the device is always powered up. If both PD1 and
PD0 are LOW, the device enters a power-down mode
between conversions. When a new conversion is initiated,
the device will resume normal operation instantly—no delay
is needed to allow the device to power up and the very first
conversion will be valid.
PD1PD0DESCRIPTION
00Power-down between conversions. When each
10Selects Internal Clock Mode.
01Reserved for Future Use.
1 1No power-down between conversions, device al-
conversion is finished, the converter enters a
low-power mode. At the start of the next conversion, the device instantly powers up to full power.
There is no need for additional delays to assure full
operation and the very first conversion is valid.
ways powered. Selects external clock mode.
TABLE V. Power-Down Selection.
Clock Modes
The ADS8344 can be used with an external serial clock or an
internal clock to perform the successive-approximation conversion. In both clock modes, the external clock shifts data in
and out of the device. Internal clock mode is selected when
PD1 is HIGH and PD0 is LOW.
If the user decides to switch from one clock mode to the other,
an extra conversion cycle will be required before the
ADS8344 can switch to the new mode. The extra cycle is
required because the PD0 and PD1 control bits need to be
written to the ADS8344 prior to the change in clock modes.
When power is first applied to the ADS8344, the user must
set the desired clock mode. It can be set by writing PD1
= 1 and PD0 = 0 for internal clock mode or PD1 = 1 and PD0
= 1 for external clock mode. After enabling the required
clock mode, only then should the ADS8344 be set to powerdown between conversions (i.e., PD1 = PD0 = 0). The
ADS8344 maintains the clock mode it was in prior to
entering the power-down modes.
External Clock Mode
In external clock mode, the external clock not only shifts data
in and out of the ADS8344, it also controls the A/D conversion
steps. BUSY will go HIGH for one clock period after the last
bit of the control byte is shifted in. Successive-approximation
bit decisions are made and appear at D
on each of the next
OUT
16 DCLK falling edges (see Figure 3). Figure 4 shows the
BUSY timing in external clock mode.
CS
t
CSS
DCLK
t
DS
D
IN
t
BDV
BUSY
t
DV
D
OUT
FIGURE 4. Detailed Timing Diagram.
ADS8344
SBAS139E
t
t
CH
CL
t
BD
t
DH
PD0
t
BD
t
D0
15
14
t
CSH
t
BTR
t
TR
13
Since one clock cycle of the serial clock is consumed with
BUSY going HIGH (while the MSB decision is being
made), 16 additional clocks must be given to clock out all 16
bits of data; thus, one conversion takes a minimum of 25
clock cycles to fully read the data. Since most microprocessors communicate in 8-bit transfers, this means that an
additional transfer must be made to capture the LSB.
There are two ways of handling this requirement. One is
where the beginning of the next control byte appears at the
same time the LSB is being clocked out of the ADS8344
(see Figure 3). This method allows for maximum throughput
and 24 clock cycles per conversion.
The other method is shown in Figure 5, which uses 32 clock
cycles per conversion; the last seven clock cycles simply
shift out zeros on the D
line. BUSY and D
OUT
go into a
OUT
high-impedance state when CS goes HIGH; after the next
CS falling edge, BUSY will go LOW.
Internal Clock Mode
In internal clock mode, the ADS8344 generates its own
conversion clock internally. This relieves the microprocessor from having to generate the SAR conversion clock and
allows the conversion result to be read back at the processor’s
convenience, at any clock rate from 0MHz to 2.0MHz.
BUSY goes LOW at the start of a conversion and then
returns HIGH when the conversion is complete. During the
conversion, BUSY will remain LOW for a maximum of 8µs.
Also, during the conversion, DCLK should remain LOW to
achieve the best noise performance. The conversion result is
stored in an internal register; the data may be clocked out of
this register any time after the conversion is complete.
If CS is LOW when BUSY goes LOW following a conversion, the next falling edge of the external serial clock will
write out the MSB on the D
line. The remaining bits
OUT
(D14-D0) will be clocked out on each successive clock cycle
following the MSB. If CS is HIGH when BUSY goes LOW
then the D
line will remain in tri-state until CS goes
OUT
LOW, as shown in Figure 6. CS does not need to remain
LOW once a conversion has started. Note that BUSY is not
tri-stated when CS goes HIGH in internal clock mode.
Data can be shifted in and out of the ADS8344 at clock rates
exceeding 2.4MHz, provided that the minimum acquisition
time t
, is kept above 1.7µs.
ACQ
Digital Timing
Figure 4 and Tables VI and VII provide detailed timing for
the digital interface of the ADS8344.
SYMBOLDESCRIPTIONMINTYPMAXUNITS
t
ACQ
t
t
t
t
t
t
CSS
t
CSH
t
t
t
t
BDV
t
BTR
DS
DH
DO
DV
TR
CH
CL
BD
Acquisition Time1.5µs
DIN Valid Prior to DCLK Rising100ns
DIN Hold After DCLK HIGH10ns
DCLK Falling to D
CS Falling to D
CS Rising to D
CS Falling to First DCLK Rising100ns
CS Rising to DCLK Ignored0ns
DCLK HIGH200ns
DCLK LOW200ns
DCLK Falling to BUSY Rising200ns
CS Falling to BUSY Enabled200ns
CS Rising to BUSY Disabled200ns
Valid200ns
OUT
Enabled200ns
OUT
Disabled200ns
OUT
TABLE VI. Timing Specifications (+VCC = +2.7V to 3.6V,
TA = –40°C to +85°C, C
LOAD
= 50pF).
CS
t
D
CLK
BUSY
D
D
OUT
1
A1 A0
IN
A2S
(START)
ACQ
81
AcquireIdleConversion
SGL/
PD1 PD0
DIF
15
14131211109 8 7654321 0
(MSB)
FIGURE 5. External Clock Mode, 32 Clocks Per Conversion.
CS
t
D
CLK
BUSY
D
OUT
1
D
IN
(START)
A1 A0
A2S
ACQ
8
AcquireIdleConversion
SGL/
PD1 PD0
DIF
9 1011121314151617181920212223242526272829303132
14131211109 8 7654321 0Zero Filled...
15
(MSB)
FIGURE 6. Internal Clock Mode Timing.
818
(LSB)
18
Idle
Zero Filled...
(LSB)
14
ADS8344
SBAS139E
SYMBOLDESCRIPTIONMINTYPMAXUNITS
t
t
t
t
t
ACQ
t
DS
t
DH
t
DO
t
DV
t
TR
CSS
CSH
t
CH
t
CL
t
BD
BDV
BTR
Acquisition Time1.7µs
DIN Valid Prior to DCLK Rising50ns
DIN Hold After DCLK HIGH10ns
DCLK Falling to D
CS Falling to D
CS Rising to D
CS Falling to First DCLK Rising50ns
CS Rising to DCLK Ignored0ns
DCLK HIGH150ns
DCLK LOW150ns
DCLK Falling to BUSY Rising100ns
CS Falling to BUSY Enabled70ns
CS Rising to BUSY Disabled70ns
Valid100ns
OUT
Enabled70ns
OUT
Disabled70ns
OUT
TABLE VII. Timing Specifications (+VCC = +4.75V to
+5.25V, TA = –40°C to +85°C, C
LOAD
= 50pF).
Data Format
The ADS8344 output data is in straight binary format, as
shown in Figure 7. This figure shows the ideal output code
for the given input voltage and does not include the effects
of offset, gain, or noise.
FS = Full-Scale Voltage = V
1LSB = V
REF
11...111
11...110
11...101
Output Code
00...010
00...001
00...000
0V
NOTE: (1) Voltage at converter input, after multiplexer: +IN – (–IN). (See Figure 2.)
1LSB
Input Voltage
/65,536
(1)
(V)
REF
FS – 1LSB
FIGURE 7. Ideal Input Voltages and Output Codes.
POWER DISSIPATION
There are three power modes for the ADS8344: full-power
(PD1 - PD0 = 11B), auto power-down (PD1 - PD0 = 00B),
and shutdown (SHDN LOW). The effects of these modes
varies depending on how the ADS8344 is being operated.
For example, at full conversion rate and 24-clocks per
conversion, there is very little difference between
full-power mode and auto power-down; a shutdown will not
lower power dissipation.
When operating at full-speed and 24-clocks per conversion
(see Figure 3), the ADS8344 spends most of its time
acquiring or converting. There is little time for auto
power-down, assuming that this mode is active. Thus, the
difference between full-power mode and auto power-down
is negligible. If the conversion rate is decreased by simply
slowing the frequency of the DCLK input, the two modes
remain approximately equal. However, if the DCLK frequency is kept at the maximum rate during a conversion, but
conversions are simply done less often, then the difference
between the two modes is dramatic. In the latter case, the
converter spends an increasing percentage of its time in
power-down mode (assuming the auto power-down mode is
active).
If DCLK is active and CS is LOW while the ADS8344 is in
auto power-down mode, the device will continue to dissipate
some power in the digital logic. The power can be reduced
to a minimum by keeping CS HIGH.
Operating the ADS8344 in auto power-down mode will
result in the lowest power dissipation, and there is no
conversion time “penalty” on power-up. The very first
conversion will be valid. SHDN can be used to force an
immediate power-down.
NOISE
The noise floor of the ADS8344 itself is extremely low, as
shown in Figures 8 thru 11, and is much lower than competing A/D converters. The ADS8344 was tested at both 5V
and 2.7V, and in both the internal and external clock modes.
A low-level DC input was applied to the analog-input pins
and the converter was put through 5,000 conversions. The
digital output of the A/D converter will vary in output code
due to the internal noise of the ADS8344. This is true for all
16-bit SAR-type A/D converters. Using a histogram to plot
the output codes, the distribution should appear bell-shaped
with the peak of the bell curve representing the nominal code
for the input value. The ±1σ, ±2σ, and ±3σ distributions will
represent the 68.3%, 95.5%, and 99.7%, respectively, of all
codes. The transition noise can be calculated by dividing the
number of codes measured by 6 and this will yield the ±3σ
distribution, or 99.7%, of all codes. Statistically, up to 3
codes could fall outside the distribution when executing
1,000 conversions. The ADS8344, with < 3 output codes for
the ±3σ distribution, will yield a < ±0.5LSB transition noise
at 5V operation. Remember, to achieve this low-noise performance, the peak-to-peak noise of the input signal and
reference must be < 50µV.
4561
24200197
7FFE7FFD800180007FFF
Code
FIGURE 8. Histogram of 5,000 Conversions of a DC Input at the
FIGURE 11. Histogram of 5,000 Conversions of a DC Input at the
Code Center, 2.7V operation internal clock mode.
AVERAGING
The noise of the A/D converter can be compensated by
averaging the digital codes. By averaging conversion results,
transition noise will be reduced by a factor of 1/√n, where n
is the number of averages. For example, averaging 4 conver-
sion results will reduce the transition noise by 1/2 to
±0.25LSBs. Averaging should only be used for input signals
with frequencies near DC.
For AC signals, a digital filter can be used to low-pass filter
and decimate the output codes. This works in a similar
manner to averaging: for every decimation by 2, the
signal-to-noise ratio will improve 3dB.
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS8344 circuitry. This is particularly true if the reference voltage is LOW and/or the conversion rate is HIGH.
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the
output of the analog comparator. Thus, during any single
conversion for an n-bit SAR converter, there are n “windows” in which large external transient voltages can easily
affect the conversion result. Such glitches might originate
from switching power supplies, nearby digital logic, and
high-power devices. The degree of error in the digital output
depends on the reference voltage, layout, and the exact
timing of the external event. The error can change if the
external event changes in time with respect to the DCLK
input.
With this in mind, power to the ADS8344 should be clean
and well bypassed. A 0.1µF ceramic bypass capacitor should
be placed as close to the device as possible. In addition, a
1µF to 10µF capacitor and a 5Ω or 10Ω series resistor may
be used to low-pass filter a noisy supply.
The reference should be similarly bypassed with a 0.1µF
capacitor. Again, a series resistor and large capacitor can be
used to low-pass filter the reference voltage. If the reference
voltage originates from an op amp, make sure that it can
drive the bypass capacitor without oscillation (the series
resistor can help in this case). The ADS8344 draws very
little current from the reference on average, but it does place
larger demands on the reference circuitry over short periods
of time (on each rising edge of DCLK during a conversion).
The ADS8344 architecture offers no inherent rejection of
noise or voltage variation in regards to the reference input.
This is of particular concern when the reference input is tied
to the power supply. Any noise and ripple from the supply
will appear directly in the digital results. While
high-frequency noise can be filtered out as discussed in the
previous paragraph, voltage variation due to line frequency
(50Hz or 60Hz) can be difficult to remove.
The GND pin should be connected to a clean ground point.
In many cases, this will be the “analog” ground. Avoid
connections that are too near the grounding point of a
microcontroller or digital signal processor. If needed, run a
ground trace directly from the converter to the power-supply
entry point. The ideal layout will include an analog ground
plane dedicated to the converter and associated analog
circuitry.
16
ADS8344
SBAS139E
Revision History
DATEREVISIONPAGESECTIONDESCRIPTION
2Package/Ordering InfoAdded quantity to last column.
9/06E
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
4Electrical CharacteristicsFixed typo. Changed +2.7V Gain Error minimum value (for EB, NB grade)
from ±0.0024 to ±0.024.
ADS8344
SBAS139E
17
PACKAGE OPTION ADDENDUM
www.ti.com
26-Mar-2007
PACKAGING INFORMATION
Orderable DeviceStatus
ADS8344EACTIVESSOP/
ADS8344E/2K5ACTIVESSOP/
ADS8344E/2K5G4ACTIVESSOP/
ADS8344EBACTIVESSOP/
ADS8344EB/2K5ACTIVESSOP/
ADS8344EB/2K5G4ACTIVESSOP/
ADS8344EBG4ACTIVESSOP/
ADS8344EG4ACTIVESSOP/
(1)
Package
Type
QSOP
QSOP
QSOP
QSOP
QSOP
QSOP
QSOP
QSOP
Package
Drawing
Pins Package
Qty
Eco Plan
DBQ2056Green (RoHS &
no Sb/Br)
DBQ202500 Green (RoHS&
no Sb/Br)
DBQ202500 Green (RoHS&
no Sb/Br)
DBQ2056Green (RoHS &
no Sb/Br)
DBQ202500 Green (RoHS&
no Sb/Br)
DBQ202500 Green (RoHS&
no Sb/Br)
DBQ2056Green (RoHS &
no Sb/Br)
DBQ2056Green (RoHS &
no Sb/Br)
ADS8344NACTIVESSOPDB2068Green (RoHS &
no Sb/Br)
ADS8344N/1KACTIVESSOPDB201000 Green (RoHS &
no Sb/Br)
ADS8344N/1KG4ACTIVESSOPDB201000 Green (RoHS &
no Sb/Br)
ADS8344NBACTIVESSOPDB2068Green (RoHS &
no Sb/Br)
ADS8344NB/1KACTIVESSOPDB201000 Green (RoHS &
no Sb/Br)
ADS8344NB/1KG4ACTIVESSOPDB201000 Green (RoHS &
no Sb/Br)
ADS8344NBG4ACTIVESSOPDB2068Green (RoHS &
no Sb/Br)
ADS8344NG4ACTIVESSOPDB2068Green (RoHS &
no Sb/Br)
(1)
The marketingstatus valuesare definedas follows:
ACTIVE: Productdevice recommendedfor newdesigns.
LIFEBUY: TIhas announcedthat thedevice willbe discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a newdesign.
PREVIEW: Devicehas beenannounced butis notin production. Samples may or may not be available.
OBSOLETE: TIhas discontinuedthe productionof thedevice.
(2)
Lead/Ball Finish MSL PeakTemp
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
(3)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
TBD: ThePb-Free/Green conversionplan hasnot beendefined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at hightemperatures, TIPb-Free productsare suitablefor use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) asdefined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Bror Sbdo notexceed 0.1%by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information maynot beavailable forrelease.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customeron anannual basis.
26-Mar-2007
Addendum-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,65
28
1
2,00 MAX
0,38
0,22
15
14
A
0,05 MIN
0,15
M
5,60
5,00
Seating Plane
8,20
7,40
0,10
0,25
0,09
0°–ā8°
Gage Plane
0,25
0,95
0,55
PINS **
DIM
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
14
6,50
6,50
5,905,90
2016
7,50
6,90
24
8,50
28
10,50
9,907,90
30
10,50
9,90
38
12,90
12,30
4040065 /E 12/01
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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