TEXAS INSTRUMENTS ADS8343 Technical data

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ADS8343

343

SBAS183C – JANUARY 2001 – REVISED APRIL 2003

16-Bit, 4-Channel Serial Output Sampling

ANALOG-TO-DIGITAL CONVERTER

FEATURES

● BIPOLAR INPUT RANGE

● PIN-FOR-PIN COMPATIBLE WITH THE

ADS7841 AND ADS8341

● SINGLE SUPPLY: 2.7V to 5V

● 4-CHANNEL SINGLE-ENDED OR

2-CHANNEL DIFFERENTIAL INPUT

● UP TO 100kHz CONVERSION RATE

● 86dB SINAD

● SERIAL INTERFACE

● SSOP-16 PACKAGE

APPLICATIONS

● DATA ACQUISITION

● TEST AND MEASUREMENT

● INDUSTRIAL PROCESS CONTROL

● PERSONAL DIGITAL ASSISTANTS

● BATTERY-POWERED SYSTEMS

DESCRIPTION

The ADS8343 is a 4-channel, 16-bit sampling Analog-toDigital (A/D) converter with a synchronous serial interface. Typical power dissipation is 8mW at a 100kHz throughput rate and a +5V supply. The reference voltage (V varied between 500mV and V input voltage range of ±V

/2, providing a corresponding

. The device includes a shut-

REF

down mode which reduces power dissipation to under 15µW. The ADS8343 is ensured down to 2.7V operation.

Low power, high speed, and an onboard multiplexer make the ADS8343 ideal for battery-operated systems such as personal digital assistants, portable multi-channel data loggers, and measurement equipment. The serial interface also provides low-cost isolation for remote data acquisition. The ADS8343 is available in an SSOP-16 package and is ensured over the –40°C to +85°C temperature range.

REF

) can be

CH0 CH1 CH2 CH3

COM

REF

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Four

Channel

Multiplexer

CDAC

SAR

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Comparator

DCLK

Serial

Interface

and

Control

SHDN DIN DOUT BUSY

PACKAGE/ORDERING INFORMATION

MAXIMUM NO

INTEGRAL MISSING SPECIFIED

PRODUCT ERROR (LSB) ERROR (LSB) PACKAGE-LEAD DESIGNATOR

LINEARITY CODES PACKAGE TEMPERATURE ORDERING TRANSPORT

ADS8343E 8 14 SSOP-16 DBQ –40°C to +85°C ADS8343E Rails, 100

(1)

RANGE NUMBER MEDIA, QUANTITY

""""""ADS8343E/2K5 Tape and Reel, 2500

ADS8343EB 6 15 SSOP-16 DBQ –40°C to +85°C ADS8343EB Rails, 100

""""""ADS8343EB/2K5 Tape and Reel, 2500

NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

to GND ........................................................................ –0.3V to +6V

Analog Inputs to GND ............................................ –0.3V to +V

Digital Inputs to GND ........................................................... –0.3V to +6V

Power Dissipation .......................................................................... 250mW

Maximum Junction Temperature................................................... +150°C

Operating Temperature Range ........................................ –40°C to +85°C

Storage Temperature Range ......................................... –65°C to +150°C

Lead Temperature (soldering, 10s) ............................................... +300°C

NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability.

(1)

+ 0.3V

ELECTROSTATIC DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PIN CONFIGURATIONS

Top View SSOP

CH0 CH1 CH2 CH3

COM

SHDN

REF

2 3 4 5 6 7 8

ADS8343

DCLK

DIN

BUSY

DOUT

GND

PIN DESCRIPTIONS

PIN NAME DESCRIPTION

1+V 2 CH0 Analog Input Channel 0 3 CH1 Analog Input Channel 1 4 CH2 Analog Input Channel 2 5 CH3 Analog Input Channel 3 6 COM Common reference for analog inputs. This pin is typically connected to V 7 8V

9+V 10 GND Ground 11 GND Ground 12 DOUT Serial Data Output. Data is shifted on the falling edge of DCLK. This output is high impedance when 13 BUSY Busy Output. This output is high impedance when 14 DIN Serial Data Input. If CS is LOW, data is latched on rising edge of DCLK. 15 16 DCLK External Clock Input. This clock runs the SAR conversion process and synchronizes serial data I/O. Maximum input clock frequency

SHDN

REF

Power Supply, 2.7V to 5V

. Shutdown. When LOW, the device enters a very low power shutdown mode. Voltage Reference Input. See Electrical Characteristic Table for ranges. Power Supply, 2.7V to 5V

is HIGH.

Chip Select Input. Controls conversion timing and enables the serial input/output register.

equals 2.4MHz to achieve 100kHz sampling rate.

REF

is HIGH.

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ADS8343

SBAS183C

ELECTRICAL CHARACTERISTICS: +5V

At TA = –40°C to +85°C, +VCC = +5V, V

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS RESOLUTION 16 ✻ Bits

ANALOG INPUT

Full-Scale Input Span Positive Input-Negative Input –V Absolute Input Range Positive Input –0.2 +V

Capacitance 25 ✻ pF Leakage Current ±1 ✻ µA

SYSTEM PERFORMANCE

No Missing Codes 14 15 Bits Integral Linearity Error ±8 ±6LSB Bipolar Error ±2 ±1mV Bipolar Error Match 2.3 8.0 ✻✻LSB Gain Error ±0.05 ±0.024 % Gain Error Match 1.0 4.0 ✻✻ LSB Noise 20 ✻ µVrms Power-Supply Rejection +4.75V < V

SAMPLING DYNAMICS

Conversion Time 16 ✻ Clk Cycles Acquisition Time 4.5 ✻ Clk Cycles Throughput Rate 100 ✻ kHz Multiplexer Settling Time 500 ✻ ns Aperture Delay 30 ✻ ns Aperture Jitter 100 ✻ ps Internal Clock Frequency External Clock Frequency 0.024 2.4 ✻✻MHz

DYNAMIC CHARACTERISTICS

Total Harmonic Distortion

(2)

Signal-to-(Noise + Distortion) V Spurious-Free Dynamic Range V Channel-to-Channel Isolation V

REFERENCE INPUT

Range 0.5 +VCC/2 ✻✻V Resistance DCLK Static 5 ✻ GΩ Input Current 40 100 ✻✻ µA

DIGITAL INPUT/OUTPUT

Logic Family CMOS ✻ Logic Levels

Data Format Binary Two’s Complement ✻

POWER-SUPPLY REQUIREMENTS

Quiescent Current 1.5 2.0 ✻ mA

Power Dissipation 7.5 10 ✻ mW

TEMPERATURE RANGE

Specified Performance –40 +85 ✻✻°C

= +2.5V, f

REF

= 100kHz, and f

SAMPLE

CLK

= 24 • f

= 2.4MHz, unless otherwise noted.

SAMPLE

ADS8343E ADS8343EB

REF

Negative Input –0.2 +V

< 5.25V 3 ✻ LSB

SHDN

= V

2.4 ✻ MHz

REF

+ 0.2 ✻✻V

✻✻V

Data Transfer Only 0 2.4 ✻✻MHz

VIN = 5Vp-p at 10kHz –95 ✻ dB

= 5Vp-p at 10kHz 86 ✻ dB

= 5Vp-p at 10kHz 97 ✻ dB

= 5Vp-p at 50kHz 100 ✻ dB

= 12.5kHz 2.5 ✻ µA

SAMPLE

DCLK Static 0.001 3 ✻✻ µA

| IIH | ≤ +5µA 3.0 5.5 ✻✻V | IIL | ≤ +5µA –0.3 +0.8 ✻✻V

IOH = –250µA 3.5 ✻ V

IOL = 250µA 0.4 ✻ V

Specified Performance 4.75 5.25 ✻✻V

= 10kHz 150 ✻ µA

SAMPLE

Power-Down Mode

(3, 4)

, CS = +V

3 ✻ µA

(1)

✻ Same specifications as ADS8343E. NOTES: (1) LSB means Least Significant Bit. With V

(PD1 = PD0 = 0) active or

= GND. (4) Power-down after conversion mode with external clock gated ‘HIGH’.

SHDN

ADS8343

SBAS183C

equal to +2.5V, one LSB is 76µV. (2) First nine harmonics of the test frequency. (3) Auto power-down mode

REF

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ELECTRICAL CHARACTERISTICS: +2.7V

At TA = –40°C to +85°C, +VCC = +2.7V, V

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS RESOLUTION 16 ✻ BITS

ANALOG INPUT

Full-Scale Input Span Positive Input-Negative Input –V Absolute Input Range Positive Input –0.2 +V

Capacitance 25 ✻ pF Leakage Current ±1 ✻ µA

SYSTEM PERFORMANCE

No Missing Codes 14 15 Bits Integral Linearity Error ±12 ±8LSB Bipolar Error ±1 ±0.5 mV Bipolar Error Match 1.2 4.0 ✻✻ LSB Gain Error ±0.05 ±0.0024 % of FSR Gain Error Match 1.0 4.0 ✻✻ LSB Noise 20 ✻ µVrms Power-Supply Rejection +2.7 < V

SAMPLING DYNAMICS

DYNAMIC CHARACTERISTICS

Total Harmonic Distortion

(2)

Signal-to-(Noise + Distortion) V Spurious-Free Dynamic Range V Channel-to-Channel Isolation V

REFERENCE INPUT

Range 0.5 +VCC/2 ✻✻V Resistance DCLK Static 5 ✻ GΩ Input Current 13 40 ✻✻ µA

DIGITAL INPUT/OUTPUT

Logic Family CMOS ✻ Logic Levels

Data Format Binary Two’s Complement ✻

POWER-SUPPLY REQUIREMENTS

Quiescent Current 1.2 1.85 ✻✻ mA

Power Dissipation 3.2 5 ✻ mW

TEMPERATURE RANGE

Specified Performance –40 +85 ✻✻°C

✻ Same specifications as ADS8343E.

NOTES: (1) LSB means Least Significant Bit. With V (PD1 = PD0 = 0) active or

= GND. (4) Power-down after conversion mode with external clock gated ‘HIGH’.

SHDN

= +1.25V, f

REF

= 100kHz, and f

SAMPLE

CLK

= 24 • f

= 2.4MHz, unless otherwise noted.

SAMPLE

ADS8343E ADS8343EB

REF

Negative Input –0.2 +V

< +3.3V 3 ✻ LSB

SHDN

= V

2.4 ✻ MHz

REF

+ 0.2 ✻✻V

✻✻V

When Used with Internal Clock 0.024 2.0 ✻✻MHz

Data Transfer Only 0 2.4 ✻✻MHz

VIN = 2.5Vp-p at 1kHz –94 ✻ dB

= 2.5Vp-p at 1kHz 81 ✻ dB

= 2.5Vp-p at 1kHz 98 ✻ dB

= 2.5Vp-p at 10kHz 100 ✻ dB

= 12.5kHz 2.5 ✻ µA

SAMPLE

DCLK Static 0.001 3 ✻✻ µA

| I

| ≤ +5µA+V

| I

| ≤ +5µA –0.3 +0.8 ✻✻V

IOH = –250µA+V

IOL = 250µA 0.4 ✻ V

• 0.7 5.5 ✻✻V

• 0.8 ✻ V

Specified Performance 2.7 3.6 ✻✻V

= 10kHz 105 µA

SAMPLE

Power-Down Mode

(3, 4)

, CS = +V

equal to +1.25V, one LSB is 38µV. (2) First nine harmonics of the test frequency. (3) Auto power-down mode

REF

3 ✻ µA

(1)

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ADS8343

SBAS183C

TYPICAL CHARACTERISTICS: +5V

–20

–40

–60

–80

–100

–120

–140

FREQUENCY SPECTRUM

(4096 Point FFT; f

= 9.985kHz, –0.2dB)

0502010 4030

Frequency (kHz)

Amplitude (dB)

SPURIOUS-FREE DYNAMIC RANGE AND

TOTAL HARMONIC DISTORTION

vs INPUT FREQUENCY

101 100

Frequency (kHz)

SFDR (dB)

110

100

THD (dB)

–110

–100

–90

–80

–70

–60

SFDR

THD

(1)

NOTE: (1) First nine harmonics of the input frequency.

Temperature (°C)

0.1

–0.1

–0.2

–0.3

CHANGE IN SIGNAL-TO-(NOISE + DISTORTION)

vs TEMPERATURE

25 100–50 –25 0 50 75

Delta from 25°C (dB)

fIN = 4.956kHz, –0.2dB

At TA = +25°C, +VCC = +5V, V

–20

–40

–60

–80

Amplitude (dB)

–100

–120

–140

100

(4096 Point FFT; f

0502010 4030

SIGNAL-TO-(NOISE + DISTORTION)

= +2.5V, f

REF

FREQUENCY SPECTRUM

SIGNAL-TO-NOISE RATIO AND

vs INPUT FREQUENCY

= 1.001kHz, –0.2dB)

Frequency (kHz)

= 100kHz, and f

SAMPLE

CLK

= 24 • f

SAMPLE

= 2.4MHz, unless otherwise noted.

SNR and SINAD (dB)

15.0

14.5

14.0

13.5

13.0

12.5

12.0

Effective Number of Bits

11.5

11.0

ADS8343

SBAS183C

SNR

101 100

Frequency (kHz)

EFFECTIVE NUMBER OF BITS

vs INPUT FREQUENCY

101 100

Frequency (kHz)

SINAD

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TYPICAL CHARACTERISTICS: +5V (Cont.)

At TA = +25°C, +VCC = +5V, V

= +2.5V, f

REF

= 100kHz, and f

SAMPLE

CLK

= 24 • f

= 2.4MHz, unless otherwise noted.

SAMPLE

ILE (LSBs)

–1

–2

–3

–4

8000

1.6

1.5

1.4

INTEGRAL LINEARITY ERROR vs CODE

C000

0000

Output Code

SUPPLY CURRENT vs TEMPERATURE

4000

DIFFERENTIAL LINEARITY ERROR vs CODE

DLE (LSBs)

–1

–2

–3

7FFF

8000

C000

0000

4000

7FFF

Output Code

CHANGE IN BPZ vs TEMPERATURE

–1

–2

1.3

Supply Current (mA)

1.2 –50 –25 0 25 50 75 100

Temperature (°C)

CHANGE IN GAIN vs TEMPERATURE

1.0

0.5

Delta from 25°C (LSBs)

–0.5

–50 –25 0 25 50 75 100

Temperature (°C)

Delta from 25°C (LSBs)

–3

–4

–50 –25 0 25 50 75 100

Temperature (°C)

WORST-CASE CHANNEL-TO-CHANNEL

BPZ MATCH vs TEMPERATURE

4.5

4.0

3.5

BPZ Match (LSBs)

3.0 –50 –25 0 25 50 75 100

Temperature (°C)

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ADS8343

SBAS183C

TYPICAL CHARACTERISTICS: +5V (Cont.)

–20

–40

–60

–80

–100

–120

–140

FREQUENCY SPECTRUM

(4096 Point FFT; f

= 9.985kHz, –0.2dB)

0502010 4030

Frequency (kHz)

Amplitude (dB)

SPURIOUS-FREE DYNAMIC RANGE AND

TOTAL HARMONIC DISTORTION

vs INPUT FREQUENCY

101 100

Frequency (kHz)

SFDR (dB)

100

500

THD (dB)

–100

–90

–80

–70

–60

–50

SFDR

THD

(1)

NOTE: (1) First nine harmonics of the input frequency.

At TA = +25°C, +VCC = +5V, V

WORST CASE CHANNEL-TO-CHANNEL

GAIN MATCH vs TEMPERATURE

0.4

= +2.5V, f

REF

= 100kHz, and f

SAMPLE

CLK

= 24 • f

= 2.4MHz, unless otherwise noted.

SAMPLE

100

COMMON-MODE REJECTION vs FREQUENCY

0.3

0.2

0.1

Gain Match (LSBs)

–0.1

–50 –25 0 25 50 75 100

Temperature (°C)

TYPICAL CHARACTERISTICS: +2.7V

At TA = +25°C, +VCC = +2.7V, V

(4096 Point FFT; f

–20

–40

= +1.25V, f

REF

FREQUENCY SPECTRUM

SAMPLE

= 1.001kHz, –0.2dB)

= 100kHz, and f

CLK

= 24 • f

SAMPLE

CMRR (dB)

VCM = 2Vp-p Sinewave Centered Around V

= 2.4MHz, unless otherwise noted.

REF

1 10 1000.1

Frequency (kHz)

–60

–80

Amplitude (dB)

–100

–120

–140

0502010 4030

SNR and SINAD (dB)

ADS8343

SBAS183C

Frequency (kHz)

SIGNAL-TO-NOISE RATIO AND

SIGNAL-TO-(NOISE + DISTORTION)

vs INPUT FREQUENCY

SNR

SINAD

Frequency (kHz)

101 100

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TYPICAL CHARACTERISTICS: +2.7V (Cont.)

At TA = +25°C, +VCC = +2.7V, V

= +1.25V, f

REF

= 100kHz, and f

SAMPLE

CLK

= 24 • f

= 2.4MHz, unless otherwise noted.

SAMPLE

14.0

13.5

13.0

12.5

12.0

11.5

11.0

10.5

Effective Number of Bits

10.0

9.5

9.0

INTEGRAL LINEARITY ERROR vs CODE

ILE (LSBs)

–1

–2

EFFECTIVE NUMBER OF BITS

vs INPUT FREQUENCY

101 100

Frequency (kHz)

0.4

0.2

–0.2

–0.4

Delta from 25°C (dB)

–0.6

–0.8

DLE (LSBs)

–1

–2

CHANGE IN SIGNAL-TO-(NOISE + DISTORTION)

vs TEMPERATURE

fIN = 4.956kHz, –0.2dB

25 100–50 –25 0 50 75

Temperature (°C)

DIFFERENTIAL LINEARITY ERROR vs CODE

–3

8000

C000

0000

4000

Output Code

SUPPLY CURRENT vs TEMPERATURE

1.2

1.1

1.0

Supply Current (mA)

0.9 –50 –25 0 25 50 75 100

Temperature (°C)

7FFF

–3

8000

C000

0000

4000

7FFF

Output Code

CHANGE IN BPZ vs TEMPERATURE

1.0

0.5

–0.5

Delta from 25°C (LSBs)

–1.0

–50 –25 0 25 50 75 100

Temperature (°C)

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ADS8343

SBAS183C

TYPICAL CHARACTERISTICS: +2.7V (Cont.)

WORST-CASE CHANNEL-TO-CHANNEL

BPZ MATCH vs TEMPERATURE

–50 –25 0 25 50 75 100

Temperature (°C)

BPZ Match (LSBs)

1.5

1.0

0.5

+VSS (V)

1.4

1.3

1.2

1.1

1.0

SUPPLY CURRENT vs +V

3.5 5.02.5 3.0 4.0 4.5

Supply Current (mA)

SAMPLE

= 100kHz

At TA = +25°C, +VCC = +2.7V, V

= +1.25V, f

REF

= 100kHz, and f

SAMPLE

CLK

= 24 • f

= 2.4MHz, unless otherwise noted.

SAMPLE

0.5

CHANGE IN GAIN vs TEMPERATURE

–0.5

Delta from 25°C (LSBs)

–1.0

–50 –25 0 25 50 75 100

Temperature (°C)

WORST-CASE CHANNEL-TO-CHANNEL

GAIN MATCH vs TEMPERATURE

0.16

0.15

0.14

COMMON-MODE REJECTION vs FREQUENCY

Gain Match (LSBs)

0.13

0.12 –50 –25 0 25 50 75 100

POWER-DOWN SUPPLY CURRENT

140

External Clock Disabled

120

100

Supply Current (mA)

–50 –25 0 25 50 75 100

Temperature (°C)

vs TEMPERATURE

Temperature (°C)

CMRR (dB)

VCM = 1Vp-p Sinewave Centered Around V

REF

1 10 1000.1

Frequency (kHz)

ADS8343

SBAS183C

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TYPICAL CHARACTERISTICS: +2.7V (Cont.)

At TA = +25°C, +VCC = +2.7V, V

= +1.25V, f

REF

= 100kHz, and f

SAMPLE

1.4

1.2

CLK

= 24 • f

= 2.4MHz, unless otherwise noted.

SAMPLE

SUPPLY CURRENT vs SAMPLING FREQUENCY

= 2.4MHz

CLK

1.0

0.8

0.6

0.4

Supply Current (mA)

0.2

Power-Down After Conversion Mode. External Clock Gated HIGH After Conversion.

10 20 30 40 50 60 70 80 90 100

Sampling Frequency (kHz)

THEORY OF OPERATION

The ADS8343 is a classic Successive Approximation Register (SAR) A/D converter. The architecture is based on capacitive redistribution which inherently includes a sample-and-hold function. The converter is fabricated on a 0.6µm CMOS process.

The basic operation of the ADS8343 is shown in Figure 1. The device requires an external reference and an external clock. It operates from a single supply of 2.7V to 5.25V. The external reference can be any voltage between 500mV and +V

/2. The value of the reference voltage directly sets the

input range of the converter. The average reference input current depends on the conversion rate of the ADS8343.

VSS = 5.0V

VSS = 2.7V

The analog input to the converter is differential and is provided via a 4-channel multiplexer. The input can be provided in reference to a voltage on the COM pin (which is generally V

) or differentially by using two of the four input

REF

channels (CH0-CH3). The particular configuration is selectable via the digital interface.

ANALOG INPUT

The analog input is bipolar and fully differential. There are two general methods of driving the analog input of the ADS8343: single-ended or differential, as shown in Figure 2.

1µF

to 10µF

Single-ended

or differential

analog inputs.

REF

+2.7V to +5V

0.1µF

1µF

ADS8343

CH0

CH1

CH2

CH3

COM

SHDN

REF

DCLK

DIN

BUSY

DOUT

GND GND

16 15 14 13 12 11 10

FIGURE 1. Basic Operation of the ADS8343.

Serial/Conversion Clock

Chip Select Serial Data In

Serial Data Out

(1)

±V

REF

Common-Mode

Voltage

(typically V

Common-Mode

NOTE: (1) Relative to common-mode voltage.

Voltage

REF

)

Single-Ended Input

(1)

REF

(1)

REF

Differential Input

CHX

ADS8343

COM

CHX+

ADS8343

CHX–

FIGURE 2. Methods of Driving the ADS8343—Single-Ended

or Differential.

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ADS8343

SBAS183C

When the input is single-ended, the COM input is held at a fixed voltage. The CHX input swings around the same voltage and the peak-to-peak amplitude is 2 • V value of V

determines the range over which the common

REF

. The

voltage may vary, as shown in Figure 3.

4.9

Common Voltage Range (V)

0.1

–1

0.5 1.0 1.5 2.0 2.5

Single-Ended Input

REF

(V)

FIGURE 3. Single-Ended Input—Common Voltage Range vs V

= 5V

2.8

2.1

REF

When the input is differential, the amplitude of the input is the difference between the CHX and COM input. A voltage or signal is common to both of these inputs. The peak-to-peak amplitude of each input is V

about this common voltage.

REF

However, since the inputs are 180° out-of-phase, the peakto-peak amplitude of the difference voltage is 2 • V value of V

also determines the range of the voltage that

REF

. The

may be common to both inputs, as shown in Figure 4.

5.2

= 5V

4.2

In each case, care should be taken to ensure that the output impedance of the sources driving the CHX and COM inputs are matched. If this is not observed, the two inputs could have different settling times. This may result in offset error, gain error, and linearity error which change with both temperature and input voltage. If the impedance cannot be matched, the errors can be lessened by giving the ADS8343 additional acquisition time.

The input current on the analog inputs depends on a number of factors: sample rate, input voltage, and source impedance. Essentially, the current into the ADS8343 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current.

Care must be taken regarding the absolute analog input voltage. Outside of these ranges, the converter’s linearity may not meet specifications. Please refer to the electrical characteristics table for min/max ratings.

REFERENCE INPUT

The external reference sets the analog input range. The ADS8343 will operate with a reference in the range of 500mV to +V ence between the CHX input and the COM input, as shown

in Figure 5. For example, in the single-ended mode, with V (CH0-CH3) will properly digitize a signal in the range of 0V to

2.50V relative to GND. If the COM pin is connected to 2.0V, the input range on the selected channel is 0.75V to 3.25V.

/2. Keep in mind that the analog input is the differ-

and COM pin set to 1.25V, the selected input channel

REF

A2-A0

(Shown 001

CH0

CH1 CH2 CH3

)

+IN

–IN

Converter

Common Voltage Range (V)

0.2

0.0 1.0 1.5 2.0 2.5

Differential Input

0.8

(V)

REF

FIGURE 4. Differential Input—Common Voltage Range vs V

ADS8343

SBAS183C

REF.

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COM

SGL/DIF

(Shown HIGH)

FIGURE 5. Simplified Diagram of the Analog Input.

There are several critical items concerning the reference input and its wide voltage range. As the reference voltage is reduced, the analog voltage weight of each digital output code is also reduced. This is often referred to as the LSB (Least Significant Bit) size and is equal to the reference voltage divided by 65,536. Any offset or gain error inherent in the A/D converter will appear to increase, in terms of LSB

size, as the reference voltage is reduced. For example, if the offset of a given converter is 2LSBs with a 2.5V reference, then it will typically be 10LSBs with a 0.5V reference. In each case, the actual offset of the device is the same, 76µV.

The noise or uncertainty of the digitized output will increase with lower LSB size. With a reference voltage of 500mV, the LSB size is 7.6µV. This level is below the internal noise of the device. As a result, the digital output code will not be stable and vary around a mean value by a number of LSBs. The distribution of output codes will be gaussian and the noise can be reduced by simply averaging consecutive conversion results or applying a digital filter.

With a lower reference voltage, care should be taken to provide a clean layout including adequate bypassing, a clean (low-noise, low-ripple) power supply, a low-noise reference, and a low-noise input signal. Because the LSB size is lower, the converter will also be more sensitive to nearby digital signals and electromagnetic interference.

The voltage into the V

input is not buffered and directly

REF

drives the Capacitor Digital-to-Analog Converter (CDAC) portion of the ADS8343. Typically, the input current is 13µA with a 2.5V reference. This value will vary by microamps depending on the result of the conversion. The reference current diminishes directly with both conversion rate and reference voltage. As the current from the reference is drawn on each bit decision, clocking the converter more quickly during a given conversion period will not reduce overall current drain from the reference.

converter enters the conversion mode. At this point, the input sample-and-hold goes into the hold mode. The next 16 clock cycles accomplish the actual A/D conversion.

Control Byte

Also shown in Figure 6 is the placement and order of the control bits within the control byte. Tables I and II give detailed information about these bits. The first bit, the ‘S’ bit, must always be HIGH and indicates the start of the control byte. The ADS8343 will ignore inputs on the DIN pin until the start bit is detected. The next three bits (A2-A0) select the active input channel or channels of the input multiplexer, as shown in Tables III and IV and Figure 5.

Bit 7 Bit 0

(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB)

S A2A1A0—

SGL/DIF

TABLE I. Order of the Control Bits in the Control Byte.

BIT NAME DESCRIPTION

7 S Start Bit. Control byte starts with first HIGH bit on

6-4 A2-A0 Channel Select Bits. Along with the

SGL/DIF

1-0 PD1-PD0 Power-Down Mode Select Bits. See Table V for

DIN.

these bits control the setting of the multiplexer input. Single-Ended/Differential Select Bit. Along with bits

A2-A0, this bit controls the setting of the multiplexer input.

details.

PD1 PD0

bit,

SGL/DIF

DIGITAL INTERFACE

Figure 6 shows the typical operation of the ADS8343’s digital interface. This diagram assumes that the source of the digital signals is a microcontroller or digital signal processor with a basic serial interface (note that the digital inputs are overvoltage tolerant up to 5.5V, regardless of +V munication between the processor and the converter consists of eight clock cycles. One complete conversion can be accomplished with three serial communications, for a total of 24 clock cycles on the DCLK input.

The first eight cycles are used to provide the control byte via the DIN pin. When the converter has enough information about the following conversion to set the input multiplexer appropriately, it enters the acquisition (sample) mode. After three more clock cycles, the control byte is complete and the

ACQ

AcquireIdle Conversion

SGL/

PD1 PD0

DIF

DIN

BUSY

(START)

1DCLK

A2S

A1 A0

). Each com-

TABLE II. Descriptions of the Control Bits within the Control Byte.

A2 A1 A0 CH0 CH1 CH2 CH3 COM

001+IN –IN 101 +IN –IN 010 +IN –IN 110 +IN–IN

TABLE III. Single-Ended Channel Selection (SGL/DIF HIGH).

A2 A1 A0 CH0 CH1 CH2 CH3 COM

001+IN–IN 101–IN +IN 010 +IN–IN 110 –IN +IN

TABLE IV. Differential Channel Control (SGL/DIF LOW).

81 8

181

AcquireIdle Conversion

SGL/

A2SA1A0

(START)

DIF

PD1 PD0

DOUT

14131211109 8 7654321 0 Zero Filled...

(MSB)

(LSB)

(MSB)

FIGURE 6. Conversion Timing, 24-Clocks per Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated serial port.

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ADS8343

SBAS183C

The SGL/DIF

bit controls the multiplexer input mode: either single-ended (HIGH) or differential (LOW). In single-ended mode, the selected input channel is referenced to the COM pin. In differential mode, the two selected inputs provide a differential input. See Tables III and IV and Figure 5 for more information. The last two bits (PD1-PD0) select the powerdown mode as shown in Table V. If both inputs are HIGH, the device is always powered up. If both inputs are LOW, the device enters a power-down mode between conversions. When a new conversion is initiated, the device will resume normal operation instantly—no delay is needed to allow the device to power up and the very first conversion will be valid.

PD1 PD0 DESCRIPTION

0 0 Power-down between conversions. When each

1 0 Selects internal clock mode. 0 1 Reserved for future use. 1 1 No power-down between conversions, device al-

conversion is finished, the converter enters a lowpower mode. At the start of the next conversion, the device instantly powers up to full power. There is no need for additional delays to assure full operation and the very first conversion is valid.

ways powered. Selects external clock mode.

TABLE V. Power-Down Selection.

Clock Modes

The ADS8343 can be used with an external serial clock or an internal clock to perform the successive-approximation conversion. In both clock modes, the external clock shifts data in and out of the device. Internal clock mode is selected when PD1 is HIGH and PD0 is LOW.

If the user decides to switch from one clock mode to the other, an extra conversion cycle will be required before the

ADS8343 can switch to the new mode. The extra cycle is required because the PD0 and PD1 control bits need to be written to the ADS8343 prior to the change in clock modes.

When power is first applied to the ADS8343, the user must set the desired clock mode. It can be set by writing PD1 = 1 and PD0 = 0 for internal clock mode or PD1 = 1 and PD0 = 1 for external clock mode. After enabling the required clock mode, only then should the ADS8343 be set to power-down between conversions (i.e., PD1 = PD0 = 0). The ADS8343 maintains the clock mode it was in prior to entering the power-down modes.

External Clock Mode

In external clock mode, the external clock not only shifts data in and out of the ADS8343, it also controls the A/D conversion steps. BUSY will go HIGH for one clock period after the last bit of the control byte is shifted in. Successive-approximation bit decisions are made and appear at DOUT on each of the next 16 DCLK falling edges, see Figure 6. Figure 7 shows the BUSY timing in external clock mode.

Since one clock cycle of the serial clock is consumed with BUSY going HIGH (while the MSB decision is being made), 16 additional clocks must be given to clock out all 16 bits of data; thus, one conversion takes a minimum of 25 clock cycles to fully read the data. Since most microprocessors communicate in 8-bit transfers, this means that an additional transfer must be made to capture the LSB.

There are two ways of handling this requirement. One is presented in Figure 6, where the beginning of the next control byte appears at the same time the LSB is being clocked out of the ADS8343. This method allows for maximum throughput and 24 clock cycles per conversion.

DCLK

DIN

BUSY

CSS

BDV

FIGURE 7. Detailed Timing Diagram.

ADS8343

SBAS183C

PD0

15DOUT

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CSH

BTR

The other method is shown in Figure 8, which uses 32 clock cycles per conversion; the last seven clock cycles simply shift out zeros on the DOUT line. BUSY and DOUT go into a high-impedance state when CS

falling edge, BUSY will go LOW.

goes HIGH; after the next

Internal Clock Mode

In internal clock mode, the ADS8343 generates its own conversion clock internally. This relieves the microprocessor from having to generate the SAR conversion clock and allows the conversion result to be read back at the processor’s convenience, at any clock rate from 0MHz to 2.0MHz. BUSY goes LOW at the start of conversion and then returns HIGH when the conversion is complete. During the conversion, BUSY will remain LOW for a maximum of 8µs. Also, during the conversion, DCLK should remain LOW to achieve the best noise performance. The conversion result is stored in an internal register; the data may be clocked out of this register any time after the conversion is complete.

is LOW when BUSY goes LOW following a conversion, the next falling edge of the external serial clock will write out the MSB on the DOUT line. The remaining bits (D14-D0) will be clocked out on each successive clock cycle following the MSB. If line will remain in tri-state until Figure 9. sion has started. Note that BUSY is not tri-stated when

is HIGH when BUSY goes LOW then the DOUT

goes LOW, as shown in

does not need to remain LOW once a conver-

goes HIGH in internal clock mode. Data can be shifted in and out of the ADS8343 at clock rates

exceeding 2.4MHz, provided that the minimum acquisition time t

, is kept above 1.7µs.

ACQ

Digital Timing

Figure 4 and Tables VI and VII provide detailed timing for the digital interface of the ADS8343.

SYMBOL DESCRIPTION MIN TYP MAX UNITS

t t

ACQ

TR CSS CSH

BD BDV

BTR

Acquisition Time 1.5 µs

DIN Valid Prior to DCLK Rising 100 ns

DIN Hold After DCLK HIGH 10 ns

DCLK Falling to DOUT Valid 200 ns

Falling to DOUT Enabled 200 ns

Rising to DOUT Disabled 200 ns

Falling to First DCLK Rising 100 ns

Rising to DCLK Ignored 0 ns

DCLK HIGH 200 ns

DCLK LOW 200 ns

DCLK Falling to BUSY Rising 200 ns

Falling to BUSY Enabled 200 ns

Rising to BUSY Disabled 200 ns

TABLE VI. Timing Specifications (+VCC = +2.7V to 3.6V,

= –40°C to +85°C, C

LOAD

= 50pF).

SYMBOL DESCRIPTION MIN TYP MAX UNITS

t t

ACQ

TR CSS CSH

BD BDV

BTR

Acquisition Time 1.7 µs

DIN Valid Prior to DCLK Rising 50 ns

DIN Hold After DCLK HIGH 10 ns

DCLK Falling to DOUT Valid 100 ns

Falling to DOUT Enabled 70 ns Rising to DOUT Disabled 70 ns

Falling to First DCLK Rising 50 ns

Rising to DCLK Ignored 0 ns

DCLK HIGH 150 ns

DCLK LOW 150 ns

DCLK Falling to BUSY Rising 100 ns

Falling to BUSY Enabled 70 ns

Rising to BUSY Disabled 70 ns

TABLE VII. Timing Specifications (+VCC = +4.75V to +5.25V,

= –40°C to +85°C, C

LOAD

= 50pF).

DCLK

DIN

BUSY

DOUT

(START)

A1 A0

A2S

ACQ

AcquireIdle Conversion

SGL/

PD1 PD0

DIF

14131211109 8 7654321 0

(MSB)

FIGURE 8. External Clock Mode 32 Clocks Per Conversion.

DCLK

DIN

BUSY

DOUT

(START)

A1 A0

A2S

ACQ

AcquireIdle Conversion

SGL/

PD1 PD0

DIF

9 1011121314151617181920212223242526272829303132

14131211109 8 7654321 0 Zero Filled...

(MSB)

FIGURE 9. Internal Clock Mode Timing.

81 8

(LSB)

Idle

Zero Filled...

(LSB)

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ADS8343

SBAS183C

DATA FORMAT

10k 100k1k 1M

SAMPLE

(Hz)

Supply Current (µA)

100

1000

CLK

= 2.4MHz

CLK

= 24 • f

SAMPLE

TA = 25°C +V

= +2.7V

REF

= +2.5V

PD1 = PD0 = 0

10k 100k1k 1M

SAMPLE

(Hz)

Supply Current (µA)

0.00

0.09

CS LOW

(GND)

CS HIGH (+V

)

= 25°C

= +2.7V

REF

= +2.5V

CLK

= 24 • f

SAMPLE

PD1 = PD0 = 0

The output data from the ADS8343 is in Binary Two’s Complement format, as shown in Table VIII. This table represents the ideal output code for the given input voltage and does not include the effects of offset, gain, or noise.

DESCRIPTION ANALOG VALUE

Full-Scale Range 2 • V Least Significant 2 • V

Bit (LSB) BINARY CODE HEX CODE +Full-Scale +V

Midscale 0V 0000 0000 0000 0000 0000 Midscale – 1LSB 0V – 1LSB 1111 1111 1111 1111 FFFF –Full-Scale –V

REF

/65536

REF

– 1LSB 0111 1111 1111 1111 7FFF

REF

DIGITAL OUTPUT

BINARY TWO’S COMPLEMENT

1000 0000 0000 0000 8000

TABLE VIII. Ideal Input Voltages and Output Codes.

POWER DISSIPATION

There are three power modes for the ADS8343: full-power (PD1 = PD0 = 1 shutdown ( depending on how the ADS8343 is being operated. For example, at full conversion rate and 24-clocks per conversion, there is very little difference between full-power mode and auto power-down, a shutdown ( lower power dissipation.

When operating at full-speed and 24 clocks per conversion (see Figure 6), the ADS8343 spends most of its time acquiring or converting. There is little time for auto power-down, assuming that this mode is active. Thus, the difference between full-power mode and auto power-down is negligible. If the conversion rate is decreased by simply slowing the frequency of the DCLK input, the two modes remain approximately equal. However, if the DCLK frequency is kept at the maximum rate during a conversion, but conversion are simply done less often, then the difference between the two modes is dramatic. Figure 10 shows the difference between reducing the DCLK frequency (“scaling” DCLK to match the conversion rate) or maintaining DCLK at the highest frequency and reducing the number of conversion per second. In the later case, the converter spends an increasing percentage of its time in power-down mode (assuming the auto power-down mode is active).

), auto power-down (PD1 = PD0 = 0B), and

SHDN

LOW). The affects of these modes varies

SHDN

LOW) will not

If DCLK is active and CS is LOW while the ADS8343 is in auto power-down mode, the device will continue to dissipate some power in the digital logic. The power can be reduced to a minimum by keeping

HIGH. The differences in

supply current for these two cases are shown in Figure 11. Operating the ADS8343 in auto power-down mode will result

in the lowest power dissipation, and there is no conversion time “penalty” on power-up. The very first conversion will be valid.

SHDN

can be used to force an immediate power-down.

FIGURE 10. Supply Current versus Directly Scaling the Fre-

quency of DCLK with Sample Rate or Keeping DCLK at the Maximum Possible Frequency.

FIGURE 11. Supply Current vs State of CS.

ADS8343

SBAS183C

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NOISE

The noise floor of the ADS8343 itself is extremely low, as can be seen from Figures 12 and 13, and is much lower than competing A/D converters. The ADS8343 was tested at both 5V and 2.7V and in both the internal and external clock modes. A low-level DC input was applied to the analog input pins and the converter was put through 5000 conversions. The digital output of the A/D converter will vary in output code due to the internal noise of the ADS8343. This is true for all 16-bit, SAR-type, A/D converters. Using a histogram to plot the output codes, the distribution should appear bell-shaped with the peak of the bell curve representing the nominal code for the input value. The ±1σ, ±2σ, and ±3σ distributions will represent the 68.3%, 95.5%, and 99.7%, respectively, of all codes. The transition noise can be calculated by dividing the number of codes measured by 6 and this will yield the ±3σ distribution or 99.7% of all codes. Statistically, up to 3 codes could fall outside the distribution when executing 1000 conversions. The ADS8343, with < 3 output codes for the ±3σ distribution, will yield a < ±0.5LSB transition noise at 5V operation. Remember, to achieve this low noise performance, the peak-to-peak noise of the input signal and reference must be < 50µV.

3295

774

FFFEHFFFFH0000H0001H0002

Code

FIGURE 12. Histogram of 5000 Conversions of a DC Input at the

Code Transition, 5V Operation External Clock Mode.

2387

694

411

38 38

FFFE

FFFD

FFFC

FFFFH0000H0001H0002H0003H0004

Code

FIGURE 13. Histogram of 5000 Conversions of a DC Input at the

Code Center, 2.7V Operation Internal Clock Mode.

705

131

905

512

AVERAGING

The noise of the A/D converter can be compensated by averaging the digital codes. By averaging conversion results, transition noise will be reduced by a factor of 1/

√n

, where n is the number of averages. For example, averaging 4 conversion results will reduce the transition noise by 1/2 to ±0.25LSBs. Averaging should only be used for input signals with frequencies near DC.

For AC signals, a digital filter can be used to low-pass filter and decimate the output codes. This works in a similar manner to averaging; for every decimation by 2, the signalto-noise ratio will improve 3dB.

LAYOUT

For optimum performance, care should be taken with the physical layout of the ADS8343 circuitry. This is particularly true if the reference voltage is low and/or the conversion rate is high.

The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the output of the analog comparator. Thus, during any single conversion for an nbit SAR converter, there are n “windows” in which large external transient voltages can easily affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, and high-power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. The error can change if the external event changes in time with respect to the DCLK input.

With this in mind, power to the ADS8343 should be clean and well bypassed. A 0.1µF ceramic bypass capacitor should be placed as close to the device as possible. In addition, a 1µF to 10µF capacitor and a 5Ω or 10Ω series resistor may be used to low-pass filter a noisy supply.

The reference should be similarly bypassed with a 1µF capacitor. Again, a series resistor and large capacitor can be used to low-pass filter the reference voltage. If the reference voltage originates from an op amp, make sure that it can drive the bypass capacitor without oscillation (the series resistor can help in this case). The ADS8343 draws very little current from the reference on average, but it does place larger demands on the reference circuitry over short periods of time (on each rising edge of DCLK during a conversion).

The ADS8343 architecture offers no inherent rejection of noise or voltage variation in regards to the reference input. This is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply will appear directly in the digital results. While high-frequency noise can be filtered out as discussed in the previous paragraph, voltage variation due to line frequency (50Hz or 60Hz) can be difficult to remove.

The GND pin should be connected to a clean ground point. In many cases, this will be the “analog” ground. Avoid connections which are too near the grounding point of a microcontroller or digital signal processor. If needed, run a ground trace directly from the converter to the power-supply entry point. The ideal layout will include an analog ground plane dedicated to the converter and associated analog circuitry.

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ADS8343

SBAS183C

PACKAGE DRAWING

DBQ (R-PDSO-G**) PLASTIC SMALL-OUTLINE

Gage Plane

0.008 (0,20) NOM

0.010 (0,25)

0.016 (0,40)

0.035 (0,89)

2420

Seating Plane

(8,74)

(8,56)

0.3370.337

(8,56)

(8,74)

0.344 0.344

4073301/E 10/00

0.150 (3,81)

0.157 (3,99)

0.012 (0,30)

0.008 (0,20)

24 PINS SHOWN

DIM

PINS **

A MIN

A MAX

0.004 (0,10)

0.010 (0,25)

0.069 (1,75) MAX

0.244 (6,20)

0.228 (5,80)

0.197

(5,00)

(4,78)

0.188

0.004 (0,10)

0.005 (0,13)

0.025 (0,64)

0°–8°

(10,01)

(9,80)

0.386

0.394

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MO-137

ADS8343

SBAS183C

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PACKAGE OPTION ADDENDUM

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18-Jul-2006

PACKAGING INFORMATION

Orderable Device Status

ADS8343E ACTIVE SSOP/

ADS8343E/2K5 ACTIVE SSOP/

ADS8343E/2K5G4 ACTIVE SSOP/

ADS8343EB ACTIVE SSOP/

ADS8343EB/2K5 ACTIVE SSOP/

ADS8343EB/2K5G4 ACTIVE SSOP/

ADS8343EBG4 ACTIVE SSOP/

ADS8343EG4 ACTIVE SSOP/

(1)

The marketingstatus valuesare definedas follows:

(1)

Package

Type

QSOP

Package Drawing

Pins Package

Qty

Eco Plan

DBQ 16 100 Green (RoHS &

no Sb/Br)

DBQ 16 2500 Green (RoHS&

no Sb/Br)

DBQ 16 2500 Green (RoHS&

no Sb/Br)

DBQ 16 100 Green (RoHS &

no Sb/Br)

DBQ 16 2500 Green (RoHS&

no Sb/Br)

DBQ 16 2500 Green (RoHS&

no Sb/Br)

DBQ 16 100 Green (RoHS &

no Sb/Br)

DBQ 16 100 Green (RoHS &

no Sb/Br)

ACTIVE: Productdevice recommendedfor newdesigns. LIFEBUY: TIhas announcedthat thedevice willbe discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a newdesign.

PREVIEW: Devicehas beenannounced butis notin production. Samples may or may not be available. OBSOLETE: TIhas discontinuedthe productionof thedevice.

(2)

Lead/Ball Finish MSL PeakTemp

CU NIPDAU Level-2-260C-1 YEAR

(3)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent forthe latestavailability informationand additionalproduct content details.

TBD: ThePb-Free/Green conversionplan hasnot beendefined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at hightemperatures, TIPb-Free productsare suitablefor use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) asdefined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Bror Sbdo notexceed 0.1%by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customeron anannual basis.

Addendum-Page 1

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TEXAS INSTRUMENTS ADS8343 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

DESCRIPTION

PACKAGE/ORDERING INFORMATION

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATIONS

PIN DESCRIPTIONS

ELECTRICAL CHARACTERISTICS: +5V

ELECTRICAL CHARACTERISTICS: +2.7V

TYPICAL CHARACTERISTICS: +5V

TYPICAL CHARACTERISTICS: +2.7V

THEORY OF OPERATION

ANALOG INPUT

REFERENCE INPUT

Control Byte

DIGITAL INTERFACE

Clock Modes

External Clock Mode

Internal Clock Mode

Digital Timing

DATA FORMAT

POWER DISSIPATION

NOISE

AVERAGING

LAYOUT

PACKAGE DRAWING

DBQ (R-PDSO-G**) PLASTIC SMALL-OUTLINE