TEXAS INSTRUMENTS ADS831 Technical data

ADS831

8-Bit, 80MHz Sampling

ANALOG-TO-DIGITAL CONVERTER

FEATURES

● HIGH SNR: 49dB

● INTERNAL OR EXTERNAL REFERENCE

OPTION

● SINGLE-ENDED OR

DIFFERENTIAL ANALOG INPUT

● PROGRAMMABLE INPUT RANGE:

1Vp-p/2Vp-p

● LOW POWER: 275mW

● LOW DNL: 0.35LSB

● SINGLE +5V SUPPLY OPERATION

● SSOP-20 PACKAGE

APPLICATIONS

● MEDICAL IMAGING

● VIDEO DIGITIZING

● COMPUTER SCANNERS

● COMMUNICATIONS

● DISK-DRIVE CONTROL

ADS831

TM

¤

SBAS087A – MAY 2001

DESCRIPTION

The ADS831 is a pipeline, CMOS Analog-to-Digital (A/D) con­verter that operates from a single +5V power supply. This con­verter provides excellent performance with a single-ended input
and can be operated with a differential input
for added spurious performance. This high performance converter
includes an 8-bit quantizer, high bandwidth
track/hold, and a high accuracy internal reference. It also allows for
the user to disable the internal reference and utilize external
references. This external reference option provides excellent gain
and offset matching when used in multi-channel applications or in
applications where DC full scale range adjustment is required.

The ADS831 employs digital error correction techniques to pro­vide excellent differential linearity for demanding imaging appli­cations. Its low distortion and high SNR give the extra margin
needed for medical imaging, communications, video, and test
instrumentation.

The ADS831 is specified at a maximum sampling frequency of
80MHz and a single-ended input range of 1.5V to 3.5V. The
ADS831 is available in an SSOP-20 package and is pin-for-pin
compatible with the 8-bit, 60MHz ADS830.

+V

S

CLK VDRV

IN

(Opt)

INV

IN

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

ADS831

T/H

8-Bit
Pipelined
A/D Core

Optional External

Reference

www.ti.com

Timing

Circuitry

Int/Ext

Error

Correction

Logic

Internal

Reference

3-State

Outputs

D0

•

•

•

D7

Copyright © 1998, Texas Instruments Incorporated

ABSOLUTE MAXIMUM RATINGS

+VS.......................................................................................................+6V

Analog Input ............................................................. –0.3V to (+V

Logic Input ............................................................... –0.3V to (+V

Case Temperature ......................................................................... +100°C

Junction Temperature .................................................................... +150°C

Storage Temperature..................................................................... +150°C

S
S

+ 0.3V)
+ 0.3V)

This integrated circuit can be damaged by ESD. Texas Instruments
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and

ELECTROSTATIC
DISCHARGE SENSITIVITY

installation procedures can cause damage.

DEMO BOARD ORDERING INFORMATION

PRODUCT DEMO BOARD

ADS831 DEM-ADS831E

ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION

PACKAGE SPECIFIED
DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT

PRODUCT PACKAGE NUMBER

ADS831E SSOP-20 (QSOP) 349 –40°C to +85°C ADS831E ADS831E Rails

" " " " " ADS831E/1K Tape and Reel

NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces
of “ADS831E/1K” will get a single 1000-piece Tape and Reel.

(1)

RANGE MARKING NUMBER MEDIA

ELECTRICAL CHARACTERISTICS

At TA = full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 80MHz, and external reference, unless otherwise noted.

ADS831E

PARAMETER CONDITIONS MIN TYP MAX UNITS
RESOLUTION 8 Guaranteed Bits

SPECIFIED TEMPERATURE RANGE Ambient Air –40 to +85 °C
ANALOG INPUT

Standard Single-Ended Input Range 2Vp-p 1.5 3.5 V
Optional Single-Ended Input Range 1Vp-p 2 3 V
Common-Mode Voltage 2.5 V
Optional Differential Input Range 2Vp-p 2 3 V
Analog Input Bias Current 1 µA
Input Impedance 1.25 || 5 MΩ || pF
Track-Mode Input Bandwidth –3dBFS 300 MHz

CONVERSION CHARACTERISTICS

Sample Rate 10k 80M Samples/s
Data Latency 4 Clk Cyc

DYNAMIC CHARACTERISTICS

Differential Linearity Error (largest code error)

f = 1MHz ±0.25 ±1.0 LSB

f = 10MHz ±0.35 LSB
No Missing Codes Guaranteed
Integral Nonlinearity Error, f = 1MHz ±0.5 ±2.0 LSBs
Spurious Free Dynamic Range

f = 1MHz (–1dB input) 67 dBFS

f = 10MHz (–1dB input) 50 65 dBFS
Two-Tone Intermodulation Distortion

f = 9.5MHz and 9.9MHz (–7dB each tone) –57 dBc
Signal-to-Noise Ratio (SNR) Referred to Full Scale

f = 1MHz 49 dB

f = 10MHz 46 49 dB
Signal-to-(Noise + Distortion) (SINAD) Referred to Full Scale

f = 1MHz 48.5 dB

f = 10MHz 44 48.5 dB
Effective Number of Bits
Output Noise Input Tied to Common-Mode 0.2 LSBs rms
Aperture Delay Time 3ns
Aperture Jitter 1.2 ps rms
Overvoltage Recovery Time 2ns
Full-Scale Step Acquisition Time 2.5 ns

(1)

(3)

(4)

, f = 1MHz 7.8 Bits

(2)

2

ADS831

SBAS087A

ELECTRICAL CHARACTERISTICS (Cont.)

At TA = full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 80MHz, and external reference, unless otherwise noted.

ADS831E
PARAMETER CONDITIONS MIN TYP MAX UNITS
DIGITAL INPUTS

Logic Family
Convert Command Start Conversion
High Level Input Current
Low Level Input Current (V
High Level Input Voltage +3.5 V

(5)

(VIN = 5V) 100 µA

= 0V) 10 µA

IN

Low Level Input Voltage +1.0 V
Input Capacitance 5pF

DIGITAL OUTPUTS

Logic Family
Logic Coding
Low Output Voltage (I
Low Output Voltage, (I
High Output Voltage, (I
High Output Voltage, (I
Low Output Voltage, (I
High Output Voltage, (I
Output Capacitance 5pF

ACCURACY

(Internal Reference, 2Vp-p, Unless Otherwise Noted)

= 50µA) VDRV = 5V +0.1 V

OL

= 1.6mA) +0.2 V

OL

= 50µA) +4.9 V

OH

= 0.5mA) +4.8 V

OH

= 50µA) VDRV = 3V +0.1 V

OL

= 50µA) +2.8 V

OH

fS = 2.5MHz
Zero Error (Referred to –FS) at 25°C –2.5 ±0.5 +2.5 %FS
Zero Error Drift (Referred to –FS) ±53 ppm/°C
Gain Error
Gain Error Drift

(6)

(6)

at 25°C –2.5 ±0.5 +2.5 %FS

Power Supply Rejection of Gain ∆ VS = ±5% 55 dB
Internal REFT Tolerance Deviation from Ideal 3.0V ±10 ±100 mV
Internal REFB Tolerance Deviation from Ideal 2.0V ±10 ±100 mV
External REFT Voltage Range REFB + 0.8 3.0 V
External REFB Voltage Range 1.25 2.0 REFT – 0.8 V
Reference Input Resistance REFT to REFB 800 Ω

POWER SUPPLY REQUIREMENTS

Supply Voltage: +V
Supply Current: +I
Power Dissipation: VDRV = 5V External Reference 290 350 mW

S

S

Operating +4.75 +5.0 +5.25 V
Operating 58 70 mA

VDRV = 3V External Reference 275 mW
VDRV = 5V Internal Reference 310 mW
VDRV = 3V Internal Reference 285 mW

Thermal Resistance,

SSOP-20 115 °C/W

θ

JA

NOTES: (1) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to Full Scale. (3) Two-tone
intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-tone fundamental
envelope. (4) Effective number of bits (ENOB) is defined by (SINAD – 1.76) /6.02. (5) A 50kΩ pull-down resistor is inserted internally. (6) Excludes internal
reference.

CMOS Compatible

Rising Edge of Convert Clock

CMOS/TTL Compatible

Straight Offset Binary

±75 ppm/°C

– 1.25 V

S

ADS831

SBAS087A

3

PIN CONFIGURATION

Top View SSOP

GND

Bit 1 (MSB)

Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7

Bit 8 (LSB)

CLK

1
2
3
4
5

ADS831

6
7
8
9

10

20
19
18
17
16
15
14
13
12
11

VDRV
+V

S

GND
IN
IN
CM
REFT
REFB
INT/EXT
RSEL

TIMING DIAGRAM

PIN DESCRIPTIONS

PIN DESIGNATOR DESCRIPTION

1 GND Ground
2 Bit 1 Data Bit 1 (D7) (MSB)
3 Bit 2 Data Bit 2 (D6)
4 Bit 3 Data Bit 3 (D5)
5 Bit 4 Data Bit 4 (D4)
6 Bit 5 Data Bit 5 (D3)
7 Bit 6 Data Bit 6 (D2)
8 Bit 7 Data Bit 7 (D1)

9 Bit 8 Data Bit 8 (D0) (LSB)
10 CLK Convert Clock
11 RSEL Input Range Select: HI = 2V; LO = 1V
12 INT/EXT Reference Select: HI = External; LO = Internal
13 REFB Bottom Reference
14 REFT Top Reference
15 CM Common-Mode Voltage Output
16 IN Complementary Input
17 IN Analog Input
18 GND Ground
19 +V
20 VDRV Output Logic Driver Supply Voltage

S

+5V Supply

t

CONV

N+2

N+3

tLt

N+4

N+5

H

N+6

Analog In

N+1

N

t

D

Clock

Data Out

4 Clock Cycles

N–4N–3N–2N–1 N N+1 N+2 N+3

Data Invalid

t

2

t

1

SYMBOL DESCRIPTION MIN TYP MAX UNITS

t

CONV

t

L

t

H

t

D

t

1

t

2

Convert Clock Period 12.5 100µsns

Clock Pulse Low 5.8 6.25 ns
Clock Pulse High 5.8 6.25 ns

Aperture Delay 3 ns

Data Hold Time, CL = 0pF 3.9 ns

New Data Delay Time, CL = 15pF max 5.9 12 ns

N+7

4

ADS831

SBAS087A

SPECTRAL PERFORMANCE

Frequency (MHz)

010203040

Magnitude (dB)

0

–10
–20
–30
–40
–50
–60
–70
–80
–90

fIN = 10MHz

SNR = 49dBFS

SFDR = 67dBFS

q

)

q

)

TYPICAL CHARACTERISTICS

DIFFERENTIAL LINEARITY ERROR

Output Code

DLE (LSB)

0.5

0.25

0

–0.25

–0.5

0 64 128 192 256

fIN = 10MHz

At TA = full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 80MHz, and external reference, unless otherwise noted.

0

–10
–20
–30
–40
–50

Magnitude (dB)

–60
–70
–80
–90

010203040

0

–10
–20
–30
–40
–50

Magnitude (dB)

–60
–70
–80
–90

010203040

SPECTRAL PERFORMANCE

fIN = 1MHz

SNR = 49dBFS

SFDR = 68dBFS

Frequency (MHz)

SPECTRAL PERFORMANCE

fIN = 20MHz

SNR = 49dBFS

SFDR = 66dBFS

Frequency (MHz)

SPECTRAL PERFORMANCE

0

–10
–20
–30
–40
–50

Magnitude (dB)

–60
–70
–80
–90

010203040

(Single-Ended, 1Vp-p)

Fre

uency (MHz

fIN = 10MHz

SNR = 49dBFS

SFDR = 66dBFS

TWO-TONE INTERMODULATION DISTORTION

0

–10
–20
–30
–40
–50
–60

Magnitude (dBFSR)

–70
–80
–90

010203040

ADS831

SBAS087A

Fre

uency (MHz

f1 = 9.5MHz at –7dBFS
f

= 9.9MHz at –7dBFS

2

IMD(3) = –57dBc

5

TYPICAL CHARACTERISTICS (Cont.)

At TA = full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 80MHz, and external reference, unless otherwise noted.

1.0

0.5

0.25

0

DLE (LSB)

–0.25

–0.5

–1.0

0 64 128 192 256

80

70

60

SFDR, SNR (dBFS)

50

DIFFERENTIAL LINEARITY ERROR

Output Code

DYNAMIC PERFORMANCE vs INPUT FREQUENCY

fIN = 20MHz

SFDR

SNR

1.0

0.5

0

ILE (LSB)

–0.5

–1.0

0 64 128 192 256

350

330

310

290

Power Dissipation (mW)

270

INTEGRAL LINEARITY ERROR

fIN = 1MHz

Output Code

POWER DISSIPATION vs TEMPERATURE

Internal Reference

External Reference

VDRV = +5V

40

0.1 1 10 100
Input Frequency (MHz)

800k

600k

400k

Counts

200k

0

N–2N–1 N N+1 N+2

OUTPUT NOISE HISTOGRAM (DC Input)

250

–50 –25 0 25 50 10075

Temperature (°C)

Output Code

6

ADS831

SBAS087A

APPLICATION INFORMATION

THEORY OF OPERATION

The ADS831 is a high-speed CMOS A/D converter which
employs a pipelined converter architecture consisting of 6
internal stages. Each stage feeds its data into the digital error
correction logic ensuring excellent differential linearity and
no missing codes at the 8-bit level. The output data becomes
valid on the rising clock edge (see Timing Diagram). The
pipeline architecture results in a data latency of 4 clock
cycles.

The analog input of the ADS831 is a differential track and
hold, as shown in Figure 1. The differential topology along
with tightly matched capacitors produce a high level of ac
performance while sampling at very high rates.

The ADS831 allows its analog inputs to be driven either
single-ended or differentially. The typical configuration for
the ADS831 is for the single-ended mode in which the input
track and hold performs a single-ended to differential con­version of the analog input signal.

Both inputs (IN, IN) require external biasing using a com­mon-mode voltage that is typically at the mid-supply level
(+VS/2).

The following application discussion focuses on the single­ended configuration. Typically, its implementation is easier
to achieve and the rated specifications for the ADS831 are
characterized using the single-ended mode of operation.

DRIVING THE ANALOG INPUT

The ADS831 achieves excellent ac performance either in the
single-ended or differential mode of operation. The selection
for the optimum interface configuration will depend on the

Op Amp

C

IN

φ1

φ2 φ1

IN

φ1

Input Clock (50%)

Internal Non-overlapping Clock

φ1 φ2 φ1

I

C

I

Bias

φ1

φ1 φ1

Op Amp

Bias

V

CM

φ1

C

H

φ2

OUT
OUT

C

φ2

H

V

CM

individual application requirements and system structure.
For example, communication applications often process a
band of frequencies that does not include DC, whereas in
imaging applications, the previously restored DC level must
be maintained correctly up to the A/D converter. Features on
the ADS831, such as the input range select (RSEL pin) or
the option for an external reference, provide the needed
flexibility to accommodate a wide range of applications. In
any case, the ADS831 should be configured such that the
application objectives are met while observing the headroom
requirements of the driving amplifier in order to yield the
best overall performance.

INPUT CONFIGURATIONS
AC-Coupled, Single-Supply Interface

Figure 2 shows the typical circuit for an ac-coupled analog
input configuration of the ADS831 where all components
are powered from a single +5V supply.

With the RSEL pin connected HIGH, the full scale input
range is set to 2Vp-p. In this configuration, the top and
bottom references (REFT, REFB) provide an output voltage
of +3.0V and +2.0V, respectively. Two resistors ( 2 x 1kΩ)
are used to create a common-mode voltage (VCM) of ap­proximately +2.5V to bias the inputs of the driving ampli­fier. Using the OPA681 on a single +5V supply, its ideal
common-mode point is +2.5V. This coincides with the
recommended common-mode input level for the ADS831
thus, obviating the need for a coupling capacitor between the
amplifier and the converter. Even though the OPA681 has an
ac gain of +2, the dc gain is only +1 due to the blocking
capacitor at resistor RG.

The addition of a small series resistor (RS) between the
output of the op amp and the input of the ADS831 will be
beneficial in almost all interface configurations. This will
de-couple the op amp’s output from the capacitive load and
avoid gain peaking, which can result in increased noise. For
best spurious and distortion performance, the resistor value
should be kept below 75Ω. The series resistor in combina-
tion with the 47pF capacitor establishes a passive low-pass
filter limiting the bandwidth for the wideband noise thus
help improving the SNR performance.

AC-Coupled, Dual Supply Interface

The circuit provided in Figure 3 shows typical connections
for the analog input in case the selected amplifier operates
on dual supplies. This might be necessary to take full
advantage of very low distortion operational amplifiers, like
the OPA642. The advantage is that the driving amplifier can
be operated with a ground referenced bipolar signal swing.
This will keep the distortion performance at its lowest since
the signal range stays within the linear region of the op amp
and sufficient headroom to the supply rails can be main­tained. By capacitively coupling the single-ended signal to
the input of the ADS831, its common-mode requirements
can easily be satisfied with two resistors connected between
the top and bottom reference.

FIGURE 1. Simplified Circuit of Input Track and Hold with

Timing Diagram.

ADS831

SBAS087A

7

1kΩ

VCM = +2.5V

0.1µF

V

IN

+V

IN

0V

–V

IN

DC

OPA681

R

G

402Ω

0.1µF

+5V

R

402Ω

R

39Ω

F

1kΩ

S

47pF

CM

IN

0.1µF

REFB
+2.0V

IN

REFT
+3.0V

ADS831

RSEL

INT/EXT

+5V

+V

GND

S

FIGURE 2. AC-Coupled Input Configuration for a 2Vp-p Full-Scale Range and a Common-Mode Voltage, VCM, at +2.5V

Derived From the Internal Top (REFT) and Bottom Reference (REFB). The OPA680 can be used in place of the
OPA681 if a voltage feedback amplifier is preferred.

1kΩ

+5V

R

S

V

IN

OPA642

–5V
R

F

402Ω

R

G

402Ω

24.9Ω

0.1µF

1kΩ

47pF

CM

0.1µF

IN

IN

REFT
+3.0V

REFB
+2.0V INT/EXT

RSEL

ADS831

+5V

+V

GND

S

FIGURE 3. AC-Coupling the Dual Supply Amplifier OPA642 to the ADS831 for a 2Vp-p Full-Scale Input Range.

For applications requiring the driving amplifier to provide a
signal amplification with a gain ≥ 5, consider using decom­pensated voltage feedback op amps, such as the OPA643, or
current feedback op amps OPA681 and OPA658.

DC-Coupled with Level Shift

Several applications may require that the bandwidth of the
signal path includes DC, in which case the signal has to be
DC-coupled to the A/D converter. In order to accomplish
this, the interface circuit has to provide a DC level shift to
the analog input signal. The circuit shown in Figure 4
employs a dual op amp, A1, to drive the input of the
ADS831 and level shift the signal to be compatible with
the selected input range. With the RSEL pin tied to the
supply and the INT/EXT pin to ground, the ADS831 is
configured for a 2Vp-p input range and uses the internal
references. The complementary input (IN) may be appropri-

ately biased using the +2.5V common-mode voltage avail­able at the CM pin. One-half of the amplifier (OPA2681)
buffers the REFB pin and drives the voltage divider R1, R2.
Because of the op amp’s noise gain of +2V/V, assuming
RF = RIN , the common-mode voltage (VCM) has to be re­scaled to +1.25V, resulting in the correct DC level of +2.5V
for the signal input (IN). Any DC voltage differences
between the IN and IN inputs of the ADS831 effectively
produce an offset, which can be corrected for by adjusting
the resistor values of the divider, R1 and R2. The selection
criteria for a suitable op amp should include the supply
voltage, input bias current, output voltage swing, distortion,
and noise specification. Note that in this example the overall
signal phase is inverted. To re-establish the original signal
polarity, it is always possible to interchange the IN and IN
connections.

8

ADS831

SBAS087A

ADS831

REFT

CM REFB

Bypass Capacitors: 0.1µF || 2.2µF each

Bandgap Reference and Logic

V

REF

400Ω

400Ω

+1+1

+V

S

50kΩ 50kΩ

INT/EXTRSEL

2Vp-p

+5V

R

F

R

IN

V

499Ω

IN

499Ω

1/2

OPA2681

R

39Ω

S

IN

47pF

RSEL

ADS831

+V

S

FIGURE 4. DC-Coupled Interface Circuit with Dual Current-Feedback Amplifier OPA2681. The OPA2680 can be used in place

SINGLE ENDED-TO-DIFFERENTIAL CONFIGURATION
(Transformer Coupled)

If the application requires a signal conversion from a single­ended source to feed the ADS831 differentially, a RF trans­former might be a good solution. The selected transformer
must have a center tap in order to apply the common-mode
DC voltage necessary to bias the converter inputs.
AC grounding the center tap will generate the differential
signal swing across the secondary winding. Consider a step­up transformer to take advantage of a signal amplification
without the introduction of another noise source. Further­more, the reduced signal swing from the source may lead to
an improved distortion performance.

The differential input configuration may provide a notice­able advantage of achieving good SFDR performance over
a wide range of input frequencies. In this mode both inputs
of the ADS831 see closely matched impedances, and the
differential signal swing is reduced to half of the swing
required for single-ended drive. Figure 5 shows the sche­matic for the suggested transformer coupled interface cir-

R

G

V

IN

FIGURE 5. Transformer Coupled Input.

NOTE: R

= RIN, G = –1

F

V

CM

= +1.25V

R

499Ω

301Ω

1

+5V

R

2

1/2

OPA2681

R

1kΩ

of the OPA2681 if a voltage feedback amplifier is preferred.

0.1µF

1:n

22Ω

47pF

R

T

22Ω

+

47pF

10µF

IN

ADS831

IN

CM

INT/EXTRSEL

+5V

0.1µF

CM (+2.5V)

IN

0.1µF

50Ω

F

REFB

(+2.0V)

0.1µF

REFT

(+3.0V)

INT/EXT

0.1µF

cuit. The component values of the R-C lowpass may be
optimized depending on the desired roll-off frequency. The
resistor across the secondary side (RT) should be calculated
using the equation RT = n2 x RG to match the source
impedance (RG) for good power transfer and VSWR.

REFERENCE OPERATION

Figure 6 depicts the simplified model of the internal refer­ence circuit. The internal blocks are the bandgap voltage
reference, the drivers for the top and bottom reference, and

FIGURE 6. Equivalent Reference Circuit with Recommended

Reference Bypassing.

ADS831

SBAS087A

9

the resistive reference ladder. The bandgap reference circuit
includes logic functions that allow to set the analog input
swing of the ADS831 to either a 1Vp-p or 2Vp-p full-scale
range simply by tying the RSEL pin to a LOW or HIGH
potential, respectively. While operating the ADS831 in the
external reference mode, the buffer amplifiers for REFT and
REFB are disconnected from the reference ladder.

As shown, the ADS831 has internal 50kΩ pull-up resistors
at the Range Select pin (RSEL) and Reference Select pin
(INT/EXT). Leaving those pins open configures the ADS831
for a 2Vp-p input range and external reference operation.
Setting the ADS831 up for internal reference mode requires
to bring the INT/EXT pin LOW.

The reference buffers can be utilized to supply up to 1mA
(sink and source) to external circuitry. To ensure proper
operation with any reference configurations, it is necessary
to provide solid bypassing at the reference pins in order to
keep the clock feedthrough to a minimum (Figure 6). All
bypassing capacitors should be located as close to their
respective pins as possible.

REFT
+3.0V

1kΩ

+

ADS831

R

1

CMV

+2.5V

1kΩ

REFB
+2.0V

R

2

0.1µF0.1µF2.2µF

+

2.2µF

FIGURE 7. Alternative Circuit to Generate Common-Mode

Voltage.

The common-mode voltage available at the CM pin may be
used as a bias voltage to provide the appropriate offset for
the driving circuitry. However, care must be taken not to
appreciably load this node, which is not buffered and has a
high impedance. An alternative way of generating a com­mon-mode voltage is given in Figure 7. Here, two external
precision resistors (1% tolerance or better) are located
between the top and bottom reference pins. The common­mode voltage, CMV, will appear at the midpoint.

EXTERNAL REFERENCE OPERATION

For even more design flexibility, the internal reference can
be disabled and an external reference voltage be used. The
utilization of an external reference may be considered for
applications requiring higher accuracy, improved tempera­ture performance, or a wide adjustment range of the
converter’s full-scale range. Especially in multichannel
applications, the use of a common external reference has the
benefit of obtaining better matching of the full-scale range
between converters.

The external references can vary as long as the value of the
external top reference REFT

stays within the range of

EXT

(VS – 1.25V) and (REFB + 0.8V), and the external bottom
reference REFB

stays within 1.25V and (REFT – 0.8V),

EXT

as shown in Figure 8.
The full-scale input signal range (FSR) of the ADS831 is

determined by the voltage difference across the reference
pins REFT and REFB (FSR = REFT – REFB), while the
common-mode voltage is defined by CMV = (REFT +
REFB)/2. In order to maintain good ac performance, it is
recommended that the typical common-mode voltage be
kept at +2.5V while setting the external reference voltages.
It is possible, however, to deviate from this common-mode
level without significantly impacting the performance. In
particular, DC-coupled applications may benefit from a
lower CMV as it increases the signal headroom of the

+5V

A - Short for 1Vp-p Input Range
B - Short for 2Vp-p Input Range (Default)

+VS

INT/EXT

IN

IN

REFT

External Top Reference

REFT = REFB +0.8V to +3.75V

CMV

V

IN

FIGURE 8. Configuration Example for External Reference Operation.

10

BA

RSEL GND

ADS831

GND REFB

External Bottom Reference

REFB = REFT –0.8V to +1.25V

ADS831

SBAS087A

driving amplifier. The internal reference ladder has a nomi­nal impedance of 800Ω. Depending on the selected refer­ence voltages, the required drive current will vary accord­ingly and the external reference circuitry should be designed
to supply the maximum required current.

DIGITAL INPUTS AND OUTPUTS
Clock Input Requirements

Clock jitter is critical to the SNR performance of high speed,
high resolution Analog to Digital Converters. It leads to
aperture jitter (t

) which adds noise to the signal being

A

converted. The ADS831 samples the input signal on the
rising edge of the CLK input. Therefore, this edge should
have the lowest possible jitter. The jitter noise contribution
to total SNR is given by the following equation. If this value
is near your system requirements, input clock jitter must be
reduced.

Jitter SNR = 20log

1

2t

π

rms signal to rms noise

ƒ

IN A

Where: ƒIN is Input Signal Frequency

tA is rms Clock Jitter

Particularly in udersampling applications, special consider­ation should be given to clock jitter. The clock input should
be treated as an analog input in order to achieve the highest
level of performance. Any overshoot or undershoot of the
clock signal may cause degradation of the performance.
When digitizing at high sampling rates, the clock should
have a 50% duty cycle (tH = tL), along with fast rise and fall
times of 2ns or less.

Digital Outputs

The output data format of the ADS831 is in positive Straight
Offset Binary code, see Table I. This format can easily
converted into the Two’s Binary Complement code by
inverting the MSB.

SINGLE-ENDED INPUT (2Vp-p) STRAIGHT OFFSET BINARY
(IN = CMV) (SOB)

+FS (IN = +3.5V) 1111 1111
+1/2 FS 1100 0000
+1LSB 1000 0001
Bipolar Zero (IN = 2.5V) 1000 0000

–1LSB 0111 1111
–1/2 FS 0100 0000
–FS (IN = +1.5V) 0000 0000

Digital Output Driver (VDRV)

The ADS831 features a dedicated supply pin for the output
logic drivers, VDRV, which is not internally connected to
the other supply pins. Setting the voltage at VDRV to +5V
or +3V the ADS831 produces corresponding logic levels
and can directly interface to the selected logic family. The
output stages are designed to supply sufficient current to
drive a variety of logic families. However, it is recom­mended to use the ADS831 with +3V logic supply. This will
lower the power dissipation in the output stages due to the
lower output swing and reduce current glitches on the supply
line which may affect the ac performance of the converter.
In some applications, it might be advantageous to decouple
the VDRV pin with additional capacitors or a pi-filter.

GROUNDING AND DECOUPLING

Proper grounding and bypassing, short lead length, and the
use of ground planes are particularly important for high
frequency designs. Multilayer PC boards are recommended
for best performance since they offer distinct advantages
like minimizing ground impedance, separation of signal
layers by ground layers, etc. The ADS831 should be treated
as an analog component. Whenever possible, the supply pins
should be powered by the analog supply. This will ensure
the most consistent results since digital supply lines often
carry high levels of noise which otherwise would be coupled
into the converter and degrade the achievable performance.
All ground connections on the ADS831 are internally joined
together, obviating the design of split ground planes. The
ground pins (1, 18) should directly connect to an analog
ground plane which covers the PC board area around the
converter. While designing the layout, it is important to keep
the analog signal traces separated from any digital lines to
prevent noise coupling onto the analog signal path. Because
of its high sampling rate, the ADS831 generates high fre­quency current transients and noise (clock feedthrough) that
are fed back into the supply and reference lines. This
requires that all supply and reference pins are sufficiently
bypassed. Figure 9 shows the recommended decoupling
scheme for the ADS831. In most cases, 0.1µF ceramic chip
capacitors at each pin are adequate to keep the impedance
low over a wide frequency range. Their effectiveness largely
depends on the proximity to the individual supply pin.
Therefore, they should be located as close to the supply pins
as possible. In addition, a larger bipolar capacitor (1µF to
22µF) should be placed on the PC board in proximity of the
converter circuit.

TABLE I. Coding Table for the ADS831.
It is recommended to keep the capacitive loading on the data

lines as low as possible (≤ 15pF). Higher capacitive loading
will cause larger dynamic currents as the digital outputs are
changing. Those high current surges can feed back to the
analog portion of the ADS831 and affect the performance. If
necessary, external buffers or latches close to the converter’s
output pins may be used to minimize the capacitive loading.
They also provide the added benefit of isolating the ADS831
from any digital noise activities on the bus coupling back
high frequency noise.

ADS831

SBAS087A

ADS831

GND

+V

1

19

+5V

S

0.1µF

10µF
+

GND

VDRV

18

20

0.1µF

+3/+5V

FIGURE 9. Recommended Bypassing for the Supply Pins.

11

PACKAGE OPTION ADDENDUM

www.ti.com

17-Nov-2005

PACKAGING INFORMATION

Orderable Device Status

ADS831E ACTIVE SSOP/

ADS831E/2K5 ACTIVE SSOP/

ADS831E/2K5G4 ACTIVE SSOP/

ADS831EG4 ACTIVE SSOP/

(1)

The marketing status values are defined as follows:

(1)

Package

Type

QSOP

QSOP

QSOP

QSOP

Package

Drawing

Pins Package

Qty

Eco Plan

DBQ 20 56 Green (RoHS &

no Sb/Br)

DBQ 20 2500 Green (RoHS &

no Sb/Br)

DBQ 20 2500 Green (RoHS &

no Sb/Br)

DBQ 20 56 Green (RoHS &

no Sb/Br)

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-2-260C-1 YEAR

CU NIPDAU Level-2-260C-1 YEAR

CU NIPDAU Level-2-260C-1 YEAR

CU NIPDAU Level-2-260C-1 YEAR

(3)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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Addendum-Page 1

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