Texas Instruments ADS8166, ADS8167, ADS8168 Datasheet

Single external op-amp

(optional)

16-bit

ADC

ALERT

SPI

4.096V

+
+

±

AINX Data

HI threshold

LO threshold

MUX

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

REFIO

÷2

DVDD

AVDD

Channel

Sequencer

Enhanced-SPI

REFby2

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ADS8166,ADS8167,ADS8168

SBAS817C –NOVEMBER 2017–REVISED NOVEMBER 2019

ADS816x 8-Channel, 16-Bit, 1-MSPS, SAR ADC With Direct Sensor Interface

1 Features

1

• Compact low-power data acquisition system:
– MUX breakout enables single external driver

amplifier
– 16-bit SAR ADC
– Low-drift integrated reference and buffer
– 0.5 × V

• Excellent AC and DC performance:
– SNR: 92 dB, THD: –110 dB
– INL: ±0.3 LSB, 16-bit no missing codes

• Multiplexer with channel sequencer:
– Multiple channel-sequencing options:

– Manual mode, on-the-fly mode, auto

sequence mode, custom channel

sequencing
– Early switching enables direct sensor interface
– Fast response time with on-the-fly mode

• System monitoring features:
– Per channel programmable window

comparator

– False trigger avoidance with programmable

hysteresis

• Enhanced-SPI digital interface:
– 1-MSPS throughput with 16-MHz SCLK
– High-speed, 70-MHz digital interface

• Wide operating range:
– External V
– AVDD from 3 V to 5.5 V
– DVDD from 1.65 V to 5.5 V
– –40°C to +125°C temperature range

output for analog input DC biasing

REF

input range: 2.5 V to 5 V

REF

2 Applications

• Analog input modules

• Multiparameter patient monitors

• Anesthesia delivery systems

• LCD tests

• Intra-DC interconnect (metro)

• Optical modules

3 Description

The ADS816x is a family of 16-bit, 8-channel, high­precision successive approximation register (SAR)
analog-to-digital converters (ADCs) operating from a
single 5-V supply with a 1-MSPS (ADS8168),
500-kSPS (ADS8167), and 250-kSPS (ADS8166)
total throughput.

The input multiplexer supports extended settling time,
which makes driving the analog inputs easier. The
output of the multiplexer and ADC analog inputs are
available as device pins. This configuration allows
one ADC driver op amp to be used for all eight
analog inputs of the multiplexer.

The ADS816x features a digital window comparator
with programmable high and low alarm thresholds per
analog input channel. The single op-amp solution with
programmable alarm thresholds enables low power,
low cost, and smallest form-factor applications.

Device Information

PART NUMBER PACKAGE BODY SIZE (NOM)

ADS816x VQFN (32) 5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at

the end of the data sheet.

ADS816x Block Diagram

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

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SBAS817C –NOVEMBER 2017–REVISED NOVEMBER 2019

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 5

6.1 Absolute Maximum Ratings...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 6

6.4 Thermal Information.................................................. 7

6.5 Electrical Characteristics........................................... 8

6.6 Timing Requirements.............................................. 10

6.7 Switching Characteristics........................................ 11

6.8 Typical Characteristics............................................ 14

7 Detailed Description............................................ 19

7.1 Overview................................................................. 19

7.2 Functional Block Diagram....................................... 19

7.3 Feature Description................................................. 20

7.4 Device Functional Modes........................................ 30

7.5 Programming........................................................... 38

7.6 Register Maps......................................................... 44

8 Application and Implementation ........................ 72

8.1 Application Information............................................ 72

8.2 Typical Applications ................................................ 75

9 Power Supply Recommendations...................... 80

10 Layout................................................................... 81

10.1 Layout Guidelines ................................................. 81

10.2 Layout Example .................................................... 83

11 Device and Documentation Support................. 84

11.1 Documentation Support ........................................ 84

11.2 Related Links ........................................................ 84

11.3 Receiving Notification of Documentation Updates 84

11.4 Community Resources.......................................... 84

11.5 Trademarks........................................................... 84

11.6 Electrostatic Discharge Caution............................ 84

11.7 Glossary................................................................ 84

12 Mechanical, Packaging, and Orderable

Information........................................................... 85

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (December 2018) to Revision C Page

• Changed document title from ADS816x 8-Channel, 16-Bit, 1-MSPS, SAR ADC With Easy-to-Drive Analog Inputs to

ADS816x 8-Channel, 16-Bit, 1-MSPS, SAR ADC With Direct Sensor Interface.................................................................... 1

• Changed Low-leakage multiplexer with sequencer to Multiplexer with channel sequencer in Features section................... 1

• Changed Wide input range to Wide operating range in Features section, changed and added sub-bullets to this

Features bullet ....................................................................................................................................................................... 1

• Deleted hysteresis from alarm threshold discussion in Description section .......................................................................... 1

• Changed title of ADS816x Block Diagram figure.................................................................................................................... 1

• Changed AUTO_SEQ_CFG1 = 0x84 to AUTO_SEQ_CFG1 = 0x44 in Auto Sequence Mode section .............................. 34

• Changed default settings from 1 to 0xFF in Channel Sample Count column of Custom Channel Sequencing

Configuration Space table .................................................................................................................................................... 36

• Changed reset value from R/W-0000 0001b to R/W-1111 1111b in REPEAT_INDEX_m Registers section ..................... 60

• Changed description of registers 78h, 7Ah, 7Ch, and 7Eh in Digital Window Comparator Configuration Registers

Mapping table ...................................................................................................................................................................... 61

• Changed ALERT_LO_STATUS Register section and name .............................................................................................. 66

• Changed ALERT_STATUS Register section and name ..................................................................................................... 68

• Changed CURR_ALERT_LO_STATUS Register section and name .................................................................................. 69

• Changed CURR_ALERT_STATUS Register section and name ......................................................................................... 71

Changes from Revision A (July 2018) to Revision B Page

• Changed document status from Advanced Information to Production Data .......................................................................... 1

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32 AVDD9AIN0

1GND 24 SDI

31 GND10AIN1

2DECAP 23 CS

30 DVDD11AIN2

3REFIO 22 ALERT

29 RST12AIN3

4REFM 21 GND

28 READY13AIN4

5REFP 20 ADC-INM

27 SDO-1/SEQSTS14AIN5

6REFP 19 MUXOUT-M

26 SDO-015AIN6

7REFby2 18 MUXOUT-P

25 SCLK16AIN7

8AIN-COM 17 ADC-INP

Not to scale

Thermal

Pad

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5 Pin Configuration and Functions

ADS8166,ADS8167,ADS8168

SBAS817C –NOVEMBER 2017–REVISED NOVEMBER 2019

RHB Package

32-Pin VQFN

Top View

Pin Functions

PIN

FUNCTION DESCRIPTIONNAME NO.

ADC-INM 20 Analog input Negative ADC analog input
ADC-INP 17 Analog input Positive ADC analog input
AIN0 9 Analog input Analog input channel 0
AIN1 10 Analog input Analog input channel 1
AIN2 11 Analog input Analog input channel 2
AIN3 12 Analog input Analog input channel 3
AIN4 13 Analog input Analog input channel 4
AIN5 14 Analog input Analog input channel 5
AIN6 15 Analog input Analog input channel 6
AIN7 16 Analog input Analog input channel 7
AIN-COM 8 Analog input Common analog input

ALERT 22 Digital output
AVDD 32 Power supply Analog power-supply pin. Connect a 1-µF capacitor from this pin to GND.

CS 23 Digital input

DECAP 2 Power supply Connect a 1-µF capacitor to GND for the internal power supply.
DVDD 30 Power supply Interface power-supply pin. Connect a 1-µF capacitor from this pin to GND.

Digital ALERT output; active high.
This pin is the output of the logical OR of the enabled channel ALERTs.

Chip-select input pin; active low.
The device starts converting the active input channel on the rising edge of CS.
The device takes control of the data bus when CS is low.
The SDO-x pins go Hi-Z when CS is high.

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Pin Functions (continued)

PIN

FUNCTION DESCRIPTIONNAME NO.

GND 1, 21, 31 Power supply Ground
MUXOUT-M 19 Analog output MUX negative analog output
MUXOUT-P 18 Analog output MUX positive analog output

Multifunction output pin.

READY 28 Digital output

REFby2 7 Analog output

REFIO 3 Analog input/output
REFM 4 Analog input Reference ground potential; short this pin to GND externally.

REFP 5, 6 Analog input/output Reference buffer output, ADC reference input. Short pins 5 and 6 together.
RST 29 Digital input

SCLK 25 Digital input

SDI 24 Digital input
SDO-0 26 Digital output Serial communication pin: data output 0.

SDO-1/
SEQSTS

Thermal pad Supply Exposed thermal pad; connect to GND.

27 Digital output

When CS is held high, READY reflects the device conversion status. READY is low when
a conversion is in process.
When CS is low, the status of READY depends on the output protocol selection.

The output voltage on this pin is equal to half the voltage on the REFP pin.
Connect a 1-µF capacitor from this pin to GND.

Reference voltage input; internal reference is a 4.096-V output.
Connect a 1-µF capacitor from this pin to GND.

Asynchronous reset input pin.
A low pulse on the RST pin resets the device. All register bits return to their default states.

Clock input pin for the serial interface.
All system-synchronous data transfer protocols are timed with respect to the SCLK signal.

Serial data input pin.
This pin is used to transfer data or commands into the device.

Multifunction output pin. By default, this pin indicates the channel scanning status in the
auto and custom channel sequence modes.
In dual SDO data transfer mode this pin functions as a serial communication pin: data
output 1.

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6 Specifications

6.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)

AVDD to GND –0.3 7 V
DVDD to GND –0.3 7 V

(2)

AINx

, AIN-COM, MUXOUT-P, MUXOUT-M, ADC-INP, ADC-INM GND – 0.3 AVDD + 0.3 V
REFP REFM – 0.3 AVDD + 0.3 V
REFIO REFM – 0.3 AVDD + 0.3 V
REFM GND – 0.1 GND + 0.1 V
Digital input pins GND – 0.3 DVDD + 0.3 V
Digital output pins GND – 0.3 DVDD + 0.3 V
Input current to any pin except supply pins –10 10 mA
Junction temperature, T
Storage temperature, T

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) AINx refers to AIN0, AIN1, AIN2, AIN3, AIN4, AIN5, AIN6, and AIN7 pins.

J

stg

(1)

MIN MAX UNIT

–40 125 °C
–65 150 °C

6.2 ESD Ratings

Human body model (HBM), per

V

(ESD)

Electrostatic discharge

ANSI/ESDA/JEDEC JS-001, all pins
Charged device model (CDM), per JEDEC

specification JESD22-C101, all pins

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

(1)

(2)

VALUE UNIT

±2000

V

±500

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

POWER SUPPLY

AVDD

DVDD

ANALOG INPUTS - SINGLE ENDED CONFIGURATION

FSR Full-scale input range 0 V

V

IN

V

IN

ANALOG INPUTS - PSEUDO-DIFFERENTIAL CONFIGURATION

FSR Full-scale input range –V

V

IN

V

IN

EXTERNAL REFERENCE INPUT

V

REFIO

TEMPERATURE RANGE

T

A

(1) AINx refers to analog inputs AIN0, AIN1, AIN2, AIN3, AIN4, AIN5, AIN6, and AIN7.
(2) CHx_CHy_CFG bits set the analog input configuration as single-ended or pseudo-differential pair. See the AIN_CFG register for more

(3) AINy refers to analog inputs AIN1, AIN3, AIN5, and AIN7 when CHx_CHy_CFG = 01b or 10b. See the Multiplexer

Internal reference 4.5 5 5.5
External reference 3 5 5.5
Operating 1.65 3 5.5
Specified throughput 2.35 3 5.5

Absolute input voltage

(1)

AINx

to REFM and CHx_CHy_CFG

(3)

AINy

to REFM and CHx_CHy_CFG = 01b –0.1 0.1

(2)

= 00b –0.1 V

Absolute input voltage AIN-COM –0.1 0.1 V

/2 V

REF

Absolute input voltage

Absolute input voltage AIN-COM V

AINx to REFM and CHx_CHy_CFG = 00b –0.1 V
AINy to REFM and CHx_CHy_CFG = 10b V

/2 – 0.1 V

REF

/2 – 0.1 V

REF

REFIO input voltage REFIO configured as input pin 2.5 AVDD – 0.3 V

Ambient temperature –40 25 125 °C

details.

Configurations section for more details.

REF

+ 0.1

REF

REF

+ 0.1

REF

/2 + 0.1

REF

/2 + 0.1 V

REF

V

V

V

V

/2 V

V

6

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SBAS817C –NOVEMBER 2017–REVISED NOVEMBER 2019

6.4 Thermal Information

ADS816x

THERMAL METRIC

R

θJA

R

θJC(top)

R

θJB

Ψ

JT

Ψ

JB

R

θJC(bot)

Junction-to-ambient thermal resistance 29.5 °C/W
Junction-to-case (top) thermal resistance 18.6 °C/W
Junction-to-board thermal resistance 10.2 °C/W
Junction-to-top characterization parameter 0.2 °C/W
Junction-to-board characterization parameter 10.2 °C/W
Junction-to-case (bottom) thermal resistance 1.3 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(1)

UNITRHB (VQFN)

32 PINS

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6.5 Electrical Characteristics

at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, REFIO configured as output pin, and maximum throughput (unless otherwise
noted); minimum and maximum values at TA= –40°C to +125°C; typical values at TA= 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ANALOG INPUTS

C

SH

C

INMUX

I

LMUX_ON

DC PERFORMANCE

NMC No missing codes 16
INL Integral nonlinearity –0.8 ±0.35 0.8 LSB
DNL Differential nonlinearity –0.5 ±0.2 0.5 LSB
V

OS

dVOS/dT Input offset thermal drift 0.25 µV/°C
G

E

dGE/dT Gain error thermal drift Referred to REFIO ±1 ppm/°C
TNS Transition noise VIN= V

AC PERFORMANCE

SINAD Signal-to-noise + distortion fIN= 2 kHz 91.6 93.5 dB
SNR Signal-to-noise-ratio fIN= 2 kHz 91.8 93.6 dB
THD Total harmonic distortion fIN= 2 kHz -110 dB
SFDR Spurious-free dynamic range fIN= 2 kHz 112 dB

REFERENCE BUFFER

V

RO

C

REFP

R

ESR

REFby2 BUFFER

V

REFby2

I

REFby2

C

REFby2

INTERNAL REFERENCE OUTPUT

V

REFIO

dV

REFIO

C

REFIO

EXTERNAL REFERENCE INPUT

I

REFIO

C

REF

SAMPLING DYNAMICS

t

j-RMS

ADC Input capacitance 60 pF
MUX Input capacitance 13 pF
MUX input on-channel leakage

current

REFM < VIN< REFP –750 ±10 750 nA

Resolution 16 Bits

Input offset error –10 ±0.5 10 LSB
Input offset error match –1 ±0.5 1 LSB

Gain error Referred to REFIO –0.06 ±0.002 0.06 %FSR
Gain error match Referred to REFIO –0.005 ±0.0025 0.005 %FSR

/2 0.6 LSB

REF

Isolation crosstalk fIN= 100 kHz -115 dB

Reference buffer offset voltage

VRO= V
25°C

REFP

- V

REFIO

, TA=

–250 250 µV

Decoupling capacitor on REFP 22 µF
External series resistance 0 1.3 Ω

REFby2 output voltage V

/2 V

REFP

DC Sourcing current from
REFby2

Decoupling capacitor on
REFby2

REFIO output voltage
Internal reference temperature

/dT

drift

(1)

TA= 25°C, REFIO configured
as output pin

1 µF

4.091 4.096 4.101 V

4 18 ppm/°C

Decoupling capacitor on REFIO REFIO configured as output 1 µF

REFIO input current REFIO configured as input pin 0.1 1 µA
Internal capacitance on REFIO

pin

REFIO configured as input pin 10 pF

Aperture delay 4 ns
Aperture jitter 2 ps RMS

2 mA

(1) Does not include the variation in voltage resulting from solder effects.
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Electrical Characteristics (continued)

at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, REFIO configured as output pin, and maximum throughput (unless otherwise
noted); minimum and maximum values at TA= –40°C to +125°C; typical values at TA= 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f

-3-dB(small)

POWER SUPPLY CURRENTS

I

AVDD

I

DVDD

Small-signal bandwidth Measured at ADC inputs 23 MHz

ADS8168, AVDD = 5 V 5.3 6.4
ADS8167, AVDD = 5 V 3.9 5
ADS8166, AVDD = 5 V 3 4.1

Analog supply current

Static, no conversion 2.3
Static, PD_REFBUF = 1 1.6
Static, PD_REF = 1 800 µA

Digital supply current

Static, PD_REFBUF, PD_REF
and PD_REFby2 = 1

DVDD = 3 V, C
no conversion

LOAD

= 10 pF,

180 µA

0.45 µA

mA

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6.6 Timing Requirements

at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum values
at TA= –40°C to +125°C; typical values at TA= 25°C

MIN NOM MAX UNIT

CONVERSION CYCLE

ADS8168 1000

f

CYCLE

t

CYCLE

t

wh_CSZ

t

wl_CSZ

t

ACQ

t

qt_ACQ

t

d_CNVCAP

ASYNCHRONOUS RESET AND LOW POWER MODES

t

wl_RST

SPI-COMPATIBLE SERIAL INTERFACE

f

CLK

t

CLK

t

ph_CK

t

pl_CK

t

ph_CSCK

t

su_CKDI

t

ht_CKDI

t

ht_CKCS

SOURCE-SYNCHRONOUS SERIAL INTERFACE

f

CLK

t

CLK

Sampling frequency

kHzADS8167 500
ADS8166 250
ADS8168 1

ADC cycle-time period

ADS8166 4

Pulse duration: CS high 30 ns
Pulse duration: CS low 30 ns
Acquisition time 300 ns
Quite acquisition time 30 ns
Quiet aperture time 20 ns

Pulse duration: RST low 100 ns

2.35 V ≤ DVDD ≤ 5.5 V,
VIH> 0.7 DVDD, VIL< 0.3 DVDD

Serial clock frequency

1.65 V ≤ DVDD < 2.35 V,
VIH≥ 0.8 DVDD, VIL≤ 0.2 DVDD

1.65 V ≤ DVDD < 2.35 V,
VIH≥ 0.9 DVDD, VIL≤ 0.1 DVDD

Serial clock time period 1/f

CLK

SCLK high time 0.45 0.55 t
SCLK low time 0.45 0.55 t

70

20

68

MHz

CLK
CLK

Setup time: CS falling to the first SCLK capture edge 15 ns
Setup time: SDI data valid to the SCLK capture edge 3 ns
Hold time: SCLK capture edge to (previous) data valid on SDI 4 ns
Delay time: last SCLK falling to CS rising 7.5 ns

2.35 V ≤ DVDD ≤ 5.5 V, SDR

Serial clock frequency

(DATA_RATE = 0b)

2.35 V ≤ DVDD ≤ 5.5 V, DDR
(DATA_RATE = 1b)

Serial clock time period 1/f

CLK

70

MHz

35

ns

µsADS8167 2

ns

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6.7 Switching Characteristics

at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum values
at TA= –40°C to +125°C; typical values at TA= 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CONVERSION CYCLE

ADS8168 660

t

CONV

ASYNCHRONOUS RESET, AND LOW POWER MODES

t

d_RST

t

PU_ADC

t

PU_REFIO

t

PU_REFBUF

t

PU_Device

SPI-COMPATIBLE SERIAL INTERFACE

t

den_CSDO

t

dz_CSDO

t

d_CKDO

t

d_CSRDY_t

SOURCE-SYNCHRONOUS SERIAL INTERFACE (External Clock)

t

d_CKSTR_r

t

d_CKSTR_f

t

off_STRDO_f

t

off_STRDO_r

t

ph_STR

t

pl_STR

Conversion time

nsADS8167 1200

ADS8166 2500

Delay time: RST rising to READY rising 4 ms
Power-up time for converter module Change PD_ADC = 1b to 0b 1 ms
Power-up time for internal reference Change PD_REF = 1b to 0b 5 ms
Power-up time for internal reference

buffer

Change PD_REFBUF = 1b to 0b 10 ms

Power-up time for device 10 ms

Delay time: CS falling to data enable 15 ns
Delay time: CS rising to SDO going to

Hi-Z
Delay time: SCLK launch edge to (next)

data valid on SDO

15 ns

19 ns

Delay time: CS falling to READY falling 15 ns

Delay time: SCLK launch edge to
READY rising

Delay time: SCLK launch edge to
READY falling

Time offset: READY falling to (next) data
valid on SDO

Time offset: READY rising to (next) data
valid on SDO

–2 2 ns

–2 2 ns

Strobe output high time 2.35 V ≤ DVDD ≤ 5.5 V 0.45 0.55 t
Strobe output low time 2.35 V ≤ DVDD ≤ 5.5 V 0.45 0.55 t

23 ns

23 ns

STR
STR

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READY

t

wl_RST

SDO-x

RST

CS

SCLK

t

d_rst

ADCST (Internal)

t

cycle

READY

t

conv_min

t

conv_max

CS

t

conv

t

acq

Sample

S

Sample

S + 1

CNV (S) ACQ (S + 1)

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Figure 1. Conversion Cycle Timing

Figure 2. Asynchronous Reset Timing

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SCLK

SDO-x

CS

t

su_CSCK

t

ht_CKCS

t

den_CSDO

t

dz_CSDO

SCLK

READY

SDO-x

(DDR)

READY

t

d_CSRDY_f

t

d_CSRDY_r

t

ph_CK

t

pl_CK

t

CLK

t

d_CKSTR_r

t

d_CKSTR_f

t

off_STRDO_r

SDO-x

(SDR)

t

off_STRDO_r

t

off_STRDO_f

SCLK

(1)

SDO-x

t

su_CSCK

t

ht_CKCS

t

den_CSDO

t

dz_CSDO

SCLK

(1)

SDI

SDO-x

t

ph_CK

t

pl_CK

t

CLK

t

su_CKDI

t

ht_CKDI

t

d_CKDO

CS

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(1) The SCLK polarity, launch edge, and capture edge depend on the SPI protocol selected.

Figure 3. SPI-Compatible Serial Interface Timing

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Figure 4. Source-Synchronous Serial Interface Timing

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Free-Air Temperature (qC)

Integral Nonlinearity (LSB)

-40 -7 26 59 92 125

-0.5

-0.3

-0.1

0.1

0.3

0.5

D008

Maximum Minimum

Reference Voltage (V)

Differential Nonlinearity (LSB)

2.5 3 3.5 4 4.5 5

-1

-0.6

-0.2

0.2

0.6

1

D050

Maximum
Minimum

Frequency

0

200

400

600

800

1000

1200

1400

1600

1800

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

0 0

6

319

1647

278

0

50

952

1004

223

21

0

ADS8D053

Free-Air Temperature (qC)

Differential Nonlinearity (LSB)

-40 -7 26 59 92 125

-0.3

-0.18

-0.06

0.06

0.18

0.3

D005

Maximum Minimum

ADC Output Code

Differential Nonlinearity (LSB)

0 13107 26214 39321 52428 65535

-0.3

-0.18

-0.06

0.06

0.18

0.3

ADS8ADS8D004

ADC Output Code

Integral Nonlinearity (LSB)

0 13107 26214 39321 52428 65535

-0.5

-0.3

-0.1

0.1

0.3

0.5

D007

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6.8 Typical Characteristics

at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, REFIO configured as output pin, and maximum throughput (unless otherwise noted)

Typical DNL = ±0.15 LSB

Figure 5. Typical DNL

2250 devices

Figure 7. Typical INL Distribution (LSB)

Typical INL = ±0.3 LSB

Figure 6. Typical INL

Figure 8. DNL vs Temperature

14

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Figure 9. INL vs Temperature

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Figure 10. DNL vs Reference Voltage

Reference Voltage (V)

Offset Error (PV)

2.5 3 3.5 4 4.5 5

-50

-40

-30

-20

-10

0

10

20

30

40

50

D011

Free-Air Temperature (qC)

Gain (%FSR)

-40 -7 26 59 92 125

-0.003

-0.002

-0.001

0

0.001

0.002

0.003

0.004

D013

Frequency

0

200

400

600

800

1000

1200

-0.01

-0.005

0

0.0025

0.005

0.0075

0.01

0 0

20

322

1101

722

84

1

0

D055

Temperature (°C)

Offset Error (PV)

-40 -7 26 59 92 125

-50

-40

-30

-20

-10

0

10

D052

Reference Voltage (V)

Integral Nonlinearity (LSB)

2.5 3 3.5 4 4.5 5

-1

-0.6

-0.2

0.2

0.6

1

D051

Maximum
Minimum

Frequency

0

50

100

150

200

250

300

350

400

450

500

550

600

650

700

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

0

4

62

249

505

441

209

81

11

0

D054

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Typical Characteristics (continued)

at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, REFIO configured as output pin, and maximum throughput (unless otherwise noted)

2250 devices

Figure 11. INL vs Reference Voltage

2250 devices

Figure 13. Typical Gain Error Distribution (%FSR)

Figure 12. Typical Offset Distribution (LSB)

REF_SEL[2:0] = 000b

Figure 14. Offset Error vs Temperature

With the appropriate REF_SEL[2:0]; see the OFST_CAL register

Figure 15. Offset Error vs Reference Voltage

Figure 16. Gain Error (ADC + REFBUF) vs Temperature

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EN_MARG = 0b

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fIN, Input Frequency (kHz)

Amplitude (dB)

0 25 50 75 100 125

-200

-160

-120

-80

-40

0

D020

Free-Air Temperature (qC)

SNR, SINAD (dBFS)

ENOB (Bits)

-40 -7 26 59 92 125

92.8 14

93.2 14.4

93.6 14.8

94 15.2

94.4 15.6

94.8 16

D028

SNR
SINAD
ENOB

fIN, Input Frequency (kHz)

Amplitude (dB)

0 100 200 300 400 500

-200

-160

-120

-80

-40

0

D018

fIN, Input Frequency (kHz)

Amplitude (dB)

0 50 100 150 200 250

-200

-160

-120

-80

-40

0

D019

Frequency

0

5000

10000

15000

20000

25000

30000

35000

40000

183

27043

467

D002

Reference Voltage (V)

Gain error (%FSR)

2.5 3 3.5 4 4.5 5

0

0.002

0.004

0.006

0.008

0.01

D014

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Typical Characteristics (continued)

at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, REFIO configured as output pin, and maximum throughput (unless otherwise noted)

EN_MARG = 0b

Figure 17. Gain Error (ADC + REFBUF) vs Reference Voltage

fIN= 2 kHz, SNR = 93.8 dB, THD = –112.7 dB

Figure 19. Typical FFT, ADS8168

Standard deviation = 0.51 LSB

Figure 18. DC Input Histogram

fIN= 2 kHz, SNR = 93.8 dB, THD = –112.4 dB

Figure 20. Typical FFT, ADS8167

16

fIN= 2 kHz, SNR = 93.8 dB, THD = –111.4 dB

Figure 21. Typical FFT, ADS8166

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Figure 22. Noise Performance vs Temperature

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fIN= 2 kHz

AVDD (V)

I

AVDD (mA)

4.5 4.7 4.9 5.1 5.3 5.5

2

2.5

3

3.5

4

4.5

5

5.5

6

6.5

7

D043

1000 kSPS
500 kSPS
250 kSPS

fIN, Input Frequency (Hz)

THD (dBFS)

SFDR (dBFS)

0 20000 40000 60000 80000 100000

-120 70

-110 80

-100 90

-90 100

-80 110

-70 120

D026

THD
SFDR

Reference Voltage (V)

THD (dBFS)

SFDR (dBFS)

2.5 3 3.5 4 4.5 5

-109.5 116

-110 115

-110.5 114

-111 113

-111.5 112

-112 111

D032

THD
SFDR

fIN, Input Frequency (Hz)

SNR, SINAD (dBFS)

ENOB (Bits)

0 20000 40000 60000 80000 100000

84 13.6

86 14

88 14.4

90 14.8

92 15.2

94 15.6

ADS8ADS8D025

SNR
SINAD
ENOB

Free-Air Temperature (qC)

THD (dBFS)

SFDR (dBFS)

-40 -7 26 59 92 125

-113 106

-112 108

-111 110

-110 112

-109 114

-108 116

-107 118

-106 120

D031

THD
SFDR

Reference Voltage (V)

SNR, SINAD (dBFS)

ENOB (Bits)

2.5 3 3.5 4 4.5 5

90.5 14.7

91 14.8

91.5 14.9

92 15

92.5 15.1

93 15.2

93.5 15.3

94 15.4

94.5 15.5

95 15.6

D029

SNR
SINAD
ENOB

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Typical Characteristics (continued)

at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, REFIO configured as output pin, and maximum throughput (unless otherwise noted)

fIN= 2 kHz

Figure 23. Distortion Performance vs Temperature

fIN= 2 kHz

Figure 25. Distortion Performance vs Reference Voltage

fIN= 2 kHz

Figure 24. Noise Performance vs Reference Voltage

Figure 26. Noise Performance vs Input Frequency

Figure 27. Distortion Performance vs Input Frequency

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Figure 28. Analog Supply Current vs Supply Voltage

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Free-Air Temperature (qC)

I

AVDD (mA)

-40 -7 26 59 92 125

2

2.5

3

3.5

4

4.5

5

5.5

6

6.5

7

D037

1000 kSPS
500 kSPS
250 kSPS

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Typical Characteristics (continued)

at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, REFIO configured as output pin, and maximum throughput (unless otherwise noted)

AVDD = 5 V

Figure 29. Analog Supply Current vs Temperature

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ADC

4.096-V

÷2

Digital

LDO

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

MUXOUT-P ADC-INP AVDD DECAP

MUXOUT-N ADC-INM REFP

REFby2

REFIO

ALERT

READY

SDO-1/SEQSTS

4-WIRE SPI

RST

AIN-COM

Channel

Sequencer

MUX

DVDD

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7 Detailed Description

7.1 Overview

The ADS816x is a 16-bit, successive approximation register (SAR) analog-to-digital converter (ADC) with an
analog multiplexer. This device integrates a reference, reference buffer, REFby2 buffer, low-dropout regulator
(LDO), and features high performance at full throughput and low power consumption.

The ADS816x supports unipolar, single-ended and pseudo-differential analog input signals. The analog
multiplexer is optimized for low distortion and extended settling time. The internal reference generates a low-drift,

4.096-V reference output. The integrated reference buffer supports burst mode for data acquisition of external
reference voltages in the range 2.5 V to 5 V. For DC level shifting of the analog input signals, the device has a
REFby2 output. The REFby2 output is derived from the output of the integrated reference buffer (the REFP pin).

When a conversion is initiated, the differential input between the ADC-INP and ADC-INM pins is sampled on the
internal capacitor array. The device uses an internal clock to perform conversions. During the conversion
process, both analog inputs of the ADC are disconnected from the internal circuit. At the end of conversion
process, the device reconnects the sampling capacitors to the ADC-INP and ADC-INM pins and enters an
acquisition phase.

The integrated LDO allows the device to operate on a single supply, AVDD. The device consumes only

26.5 mW, 19.5 mW, and 15 mW of power when operating at 1 MSPS (ADS8168), 500 kSPS (ADS8167), and
250 kSPS (ADS8166), respectively, with the internal reference, reference buffer, REFby2 buffer, and LDO
enabled.

The enhanced-SPI digital interface is backward-compatible with traditional SPI protocols. Configurable features
boost analog performance and simplify board layout, timing, firmware, and support full throughput at lower clock
speeds. These features enable a variety of microcontrollers, digital signal processors (DSPs), and field­programmable gate arrays (FPGAs) to be used.

The ADS816x enables optical line cards, test and measurement, medical, and industrial applications to achieve
fast, low-noise, low-distortion, and low-power data acquisition in a small form-factor.

7.2 Functional Block Diagram

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AINx

R

MUX

40

SW

AINy,
AIN-COM

R

MUX

40

SW

C

MUX

13pF

ADC-INP

R

S1

50

SW

C

S1

60pF

ADC-INM

R

S2

50

SW

C

S2

60pF

MUXOUT-M

MUXOUT-P

OR

OR

MUX ADC

AVDD

AVDD

AVDD

AVDD

C

MUX

13pF

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7.3 Feature Description

The ADS816x is comprised of five modules: the converter (SAR ADC), multiplexer (MUX), the reference module,
the enhanced-SPI interface, and the low-dropout regulator (LDO); see the Functional Block Diagram section.

The LDO module is powered by the AVDD supply, and generates the bias voltage for the internal circuit blocks of
the device. The reference buffer drives the capacitive switching load present at the reference pins during the
conversion process. The multiplexer selects among eight analog input channels as the input for the converter
module. The converter module samples and converts the analog input into an equivalent digital output code. The
enhanced-SPI interface module facilitates communication and data transfer between the device and the host
controller.

7.3.1 Analog Multiplexer

Figure 30 shows the small-signal equivalent circuit of the sample-and-hold circuit. Each sampling switch is

represented by resistance (RS1and RS2, typically 50 Ω) in series with an ideal switch (SW). The sampling
capacitors, CS1and CS2, are typically 60 pF.

The multiplexer on-resistance (R
MUXOUT-P or MUXOUT-M pins. The multiplexer analog input typically has a 13-pF on-channel capacitance
(C

).

MUX

), is typically a 40-Ω resistor in series between the ON channel and the

MUX

Figure 30. Input Sampling Stage Equivalent Circuit

During the input signal acquisition phase, the ADC-INP and ADC-INM inputs are individually sampled on CS1and
CS2, respectively. During the conversion process, the device converts for the voltage difference between the two
sampled values: V

Each analog input pin has electrostatic discharge (ESD) protection diodes to AVDD and GND. Keep the analog
inputs within the specified range to avoid turning the diodes on.

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ADC-INP

– V

.

ADC-INM

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AIN-COM

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

8-channel MUX

Input Pair 1

Input Pair 2

Input Pair 3

Input Pair 4

AIN-COM not used

COM_CFG bit = 0

Configuration - 1 Configuration - 2

Configuration - 3

REFby2

Single-ended

AIN-COM = GND

Pseudo-differential

AIN-COM =

REFby2

AIN-COM

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

REFby2

COM_CFG bit = 1

AIN

X

AIN

Y

GND or REFby2

Single-ended

CHx_CHy_CFG = 01b

4-channel MUX

Pseudo-differential

CHx_CHy_CFG = 10b

CHx_CHy_CFG = 00b

Input Pair 1

Input Pair 2

AIN-COM

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

REFby2

6-channel MUX

Single-ended

CHx_CHy_CFG = 01b

Pseudo-differential

CHx_CHy_CFG = 10b

AIN

X

AIN

Y

GND or REFby2

4 single inputs
referred to AIN-COM

CHx_CHy_CFG = 00b

Single-ended

AIN-COM = GND

Pseudo-differential

AIN-COM =

REFby2

Channels Input Pairs

Single Inputs

8

7

6

5

0

1

2

3

8

6

4

2

4

4

0

Selectable Channel Configuration

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Feature Description (continued)

7.3.1.1 Multiplexer Configurations

The ADS816x supports single-ended and pseudo-differential analog input signals. The flexible analog input
channel configuration supports interfacing various types of sensors. Figure 31 shows how the analog inputs can
be configured.

Figure 31. Analog Input Configurations

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Feature Description (continued)

The analog inputs can be configured as:

• Configuration 1: Eight-channel MUX with the AIN_CFG register set to 00h. The AIN-COM input range is
decided by the COM_CFG register.

– Single-ended inputs with the AIN-COM input set to GND (set the COM_CFG register to 00h).
– Pseudo-differential inputs with the AIN-COM input set to V

• Configuration 2: Four-channel MUX.
– As shown in Table 1, the AIN_CFG register selects the analog input range of individual pairs.

• Configuration 3: Single-ended and pseudo-differential inputs.
– Among the eight analog inputs of the MUX, some inputs can be configured as pairs and some inputs are

configured as individual channels. Table 1 lists options for channel configuration.

– For channels configured as pairs, the AIN_CFG register selects the single-ended or pseudo-differential

configuration for individual pairs.

– For individual channels, the COM_CFG register decides the single-ended or pseudo-differential

configuration.

/ 2 (set the COM_CFG register to 01h).

REF

Table 1. Channel Configuration Options

SERIAL NUMBER TOTAL CHANNELS INPUT PAIRS INDIVIDUAL CHANNELS

1 8 0 8
2 7 1 6
3 6 2 4
4 5 3 2
5 4 4 0

(1) Channel pairs can be formed as [AIN0 - AIN1], [AIN2 - AIN3], [AIN4 - AIN5], and [AIN6 - AIN7].
(2) When channels are configured as pairs, AIN0, AIN2, AIN4, and AIN6 are positive inputs.

(1)(2)

NOTE

The COM_CFG register sets the input voltage range of the AIN-COM pin. AIN-COM pin
must be connected to GND (set the COM_CFG register to 0b) or REFby2 (set the
COM_CFG register to 1b) externally. When using the MUX in a four-channel configuration,
the COM_CFG register has no effect; connect the AIN-COM pin to GND to avoid noise
coupling.

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AINx

R

MUX

40

C

MUX

13pF

AINy,
AIN-COM

R

MUX

40

C

MUX

13pF

ADC-AINP

R

S1

50

C

S1

60pF

ADC-AINM

R

S2

50

C

S2

60pF

MUXOUT-M

MUXOUT-P

MUX

ADC

OR

OR

SW

MUX

SW

MUX

SW

ADC

SW

ADC

CH

X

SW

C

D

MUXOUT

Conventional MUX

C

S

CH

Y

SW

C

D

C

S

CH

X

SW

MUXOUT

ADS816x MUX

C

S

CH

Y

SW

C

S

SW

C

D

SW

C

D

SW

SW

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7.3.1.2 Multiplexer With Minimum Crosstalk

For precision measurement in a multichannel system, coupling (such as crosstalk) from one channel to another
can distort the measurement. In conventional multiplexers, as shown in Figure 32, the off channel parasitic
capacitance between the drain and the source of the switch (C

) couples the off channel signal to the on

DSY

channel.

Figure 32 shows that the ADS816x uses a T-switch structure. In this switch architecture, the off channel parasitic

capacitance is connected to ground, which significantly reduces coupling. Care must be taken to avoid signal
coupling on the printed circuit board (PCB), as described in the Layout section.

Figure 32. Isolation Crosstalk in a Conventional MUX versus the ADS816x

7.3.1.3 Early Switching for Direct Sensor Interface

Figure 33 shows the small-signal equivalent model of the ADS816x analog inputs. The multiplexer input has a

switch resistance (R

) and parasitic capacitance (C

MUX

). The parasitic capacitance causes a charge kickback

MUX

on the MUX analog input at the same time as the ADC sampling capacitor causes a charge kickback on ADC
inputs.

Figure 33. Synchronous and Timed Switching of the MUX and ADC Input Switches

In conventional multichannel SAR ADCs, the acquisition time of the ADC is also the settling time available at the
analog inputs of the multiplexer because these times are internally connected. Thus, high-bandwidth op amps
are required at the analog inputs of the multiplexer to settle the charge kickback. However, multiple high­bandwidth op amps significantly increase power dissipation, cost, and size of the solution.

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SW

ADC

CS

SW

MUX

t

CYCLE

CHX Input Settling Time

t

ACQ

100-ns

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The analog inputs of the ADS816x provide a long settling time (t

– 100 ns), resulting in long acquisition time

CYCLE

at the MUX inputs when using a driver amplifier between the MUX outputs and the ADC inputs. Figure 34 shows
a timing diagram of this long acquisition phase. The low parasitic capacitance together with the enhanced settling
time eliminate the need to use an op amp at the multiplexer input in most applications.

Figure 34. Early Switching of the MUX Enables a Long Acquisition Phase

Averaging several output codes of a particular MUX input channel without switching the MUX achieves better
accuracy and noise performance. The output of the multiplexer does not create a charge kickback as long as SDI
is set to 0 (that is, as long as SDI returns the NOP command); see Figure 43 and Figure 45. The multiplexer
does not switch during subsequent conversions except for the first time when a channel is selected. Thus high­impedance sources (such as the voltage from the resistor dividers) can be connected to the analog inputs of the
multiplexer without an op amp.

7.3.2 Reference

The ADS816x has a precision, low-drift reference internal to the device. See the Internal Reference section for
details about using the internal reference.

For best SNR performance, the input signal range must be equal to the full-scale input range of the ADC. To
maximize ENOB, an external reference voltage source can be used as described in the External Reference
section.

7.3.2.1 Internal Reference

The device features an internal reference source with a nominal output value of 4.096 V. On power-up, the
internal reference is enabled by default. A minimum 1-µF decoupling capacitor, as illustrated in Figure 35, is
recommended to be placed between the REFIO and REFM pins. The capacitor must be placed as close to the
REFIO pin as possible. The output impedance of the internal band-gap circuit creates a low-pass filter with this
capacitor to band-limit the noise of the reference. The internal reference is also temperature compensated to
provide excellent temperature drift over an extended industrial temperature range of –40°C to +125°C. By default
the internal reference is on and the voltage at REFIO is 4.096 V. The REFIO pin has ESD protection diodes to
the AVDD and GND pins.

The initial accuracy specification for the internal reference can be degraded if the die is exposed to any
mechanical or thermal stress. Heating the device when being soldered to a PCB and any subsequent solder
reflow is a primary cause for shifts in the internal reference voltage output. The main cause of thermal hysteresis
is a change in die stress and is therefore a function of the package, die-attach material, and molding compound,
as well as the layout of the device itself.

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ADC

4.096-V

REFP

REFIO

GND

REFM

REF5040

AVDD

OUT

PD_CNTL[3] = 1

(PD_REF)

10 …F 10 …F

1 …F

1-k

AVDD

5-V

ADS816x

ADC

REFP

REFIO

GND

REFM

AVDD

PD_CNTL[3] = 0

(PD_REF)

10 F 10 F

1 F

4.096-V

1-k

ADS816x

5-V

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Figure 35. Device Connections for Using an Internal 4.096-V Reference

7.3.2.2 External Reference

Figure 36 shows the connections for using the device with an external reference. A reference without a low-

impedance output buffer can be used because the input leakage current of the internal reference buffer is less
than 1 µA.

Figure 36. Device Connections for Using an External Reference

7.3.3 Reference Buffer

The ADC starts converting the sampled analog input channel on the CS rising edge and the internal capacitors
are switched to the REFP pins as per the successive approximation algorithm. Most of the switching charge
required during the conversion process is provided by an external decoupling capacitor C
from C
The subsequent conversion occurs with this different reference voltage, and causes a proportional error in the
output code. The internal reference buffer of the device maintains the voltage on the REFP pins within 0.5 LSB of
V
value of C

REFP

. All typical characteristics of the device are specified with the internal reference buffer and the specified

REFP

is not replenished before the next CS rising edge, the voltage on the REFP pins is less than V

.

REFP

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. If the charge lost

REFP

REFP

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REFIO

REFM

GND

AVDD

+

±

REFP

REFP

Margin

BUF

ADS816x

4.096-V

PD_REF

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In burst-mode operation, the ADC samples the selected analog input channel for a long duration of time and then
performs a burst of conversions. During the sampling time, the sampling capacitor (CS) is connected to the
differential input pins and no charge is drawn from the REFP pins. However, during the very first conversion
cycle, there is a step change in the current drawn from the REFP pins. This sudden change in load triggers a
transient settling response in the reference buffer. For a fixed input voltage, any transient settling error at the end
of the conversion cycle results in a change in output codes over the subsequent conversions. The internal
reference buffer of the ADS816x, when used with the recommended value of C

, keeps the transient settling

REFP

error at the end of each conversion cycle within 0.5 LSB. Therefore, the device supports burst-mode operation
with every conversion result as per the data sheet specifications.

Figure 37 shows the block diagram of the internal reference and reference buffer.

Figure 37. Internal Reference and Reference Buffer Block Diagram

For the minimum ADC input offset error (VOS), set the REF_SEL[2:0] bits to the value closest to V

OFST_CAL register). The internal reference buffer has a typical gain of 1 V/V with a minimal offset error (V

REF

(see the

(RO)

and the output of the buffer is available between the REFP and the REFM pins. Set the REF_OFST[4:0] (see the

REF_MRG1 register) bits to add or subtract an intentional offset voltage as described in Table 22.

Short the two REFP pins externally. Short the REFM pin to GND externally. Place a decoupling capacitor C

REFP

between the REFP and the REFM pins as close to the device as possible; see Figure 36. See the Layout section
for layout recommendations.

),

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+

-

Ref

Current Sense Amplifier

V

LOAD

Load

V

CC

ADC

REF

ADS816x

REFby2

Configuration 1: High-side / Low-side Current sensing

+

-

AC coupled

sensor

V

CC

ADC

REF

ADS816x

REFby2

Configuration 2: AC Coupled Sensor Interface

+

-

V

CC

ADC

REF

ADS816x

REFby2

Configuration 3:Unity Gain Sensor Interface

+

-

INA

V

CC

ADC

REF

ADS816x

REFby2

Configuration 4: High Impedance Sensor Interface with INA

RR

Ref

V

BRIDGE

INA

R

R

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7.3.4 REFby2 Buffer

To use the maximum dynamic range of the ADC, the input signal must be biased around the mid-scale of the
ADC input range. In the ADS816x, where the absolute input range is 0 V to the reference voltage (V
scale is V

/ 2. The REFby2 buffer generates the V

REF

/ 2 signal for mid-scale shifting of the input signal.

REF

REF

), mid-

Figure 38 shows that REFBy2 can be used in various types of sensor signal conditioning circuits.

Figure 38. Signal Conditioning With the REFby2 Buffer

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GND

AVDD

+

±

REFby2

BUF

ADS816x

REFIO

+

±

BUF

100-k

100-k

ADC
Reference

Margin

REFP

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A resistor divider at the output of the reference buffer, as shown in Figure 39, generates the V

/ 2 signal.

REF

When not using the internal reference buffer (see the PD_CNTL register), any voltage applied at the REFP pin is
applied to the resistor divider. The output of the resistor divider is buffered and available at the REFby2 pin.

Figure 39. REFby2 Buffer Model

The REFby2 buffer is capable of sourcing up to 2 mA of DC current. The REFby2 pin has ESD diode
connections to AVDD and GND.

7.3.5 Converter Module

The converter module samples the analog input signal (provided between the ADC-INP and ADC-INM pins),
compares this signal with the reference voltage (between the REFP pins and REFM pin), and generates an
equivalent digital output code.

The converter module receives the RST and CS inputs from the interface module, and outputs the conversion
result back to the interface module.

7.3.5.1 Internal Oscillator

The device features an internal oscillator (OSC) that provides the conversion clock. Conversion duration varies,
but is bounded by the minimum and maximum value of t

conv

.

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1

FFFF

8000

FSR ± 1 LSBMID-FSR

Analog Input

(AINP  AINM)

7FFF

ADC Code (Hex)

V

IN

0

MID ± 1 LSB

-FSR + 1 LSB

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7.3.5.2 ADC Transfer Function

The device supports single-ended and pseudo-differential analog inputs. The device output is in straight binary
format. Figure 40 and Table 2 show the ideal transfer characteristics for a 16-bit ADC with unipolar inputs.

Equation 1 gives the least significant bit (LSB) for the ADC:

1 LSB = V

REF

/ 2

16

(1)

Figure 40. Converter Transfer Characteristics

Table 2. Transfer Characteristics

DESCRIPTION

SINGLE-ENDED INPUT VOLTAGE

(V

= 4.096 V)

REF

FSR – 1 LSB 4.0959375 V 2.0479375 V FFFF
MID + 1 LSB 2.0480625 V 0.0000625 V 8001

MID 2.048 V 0 V 8000

MID – 1 LSB 2.0479375 V –0.0000625 V 7FFF

–FSR + 1 LSB 0.0000625 V –2.0479375 V 0001

–FSR 0 V –2.048 V 0000

PSEUDO-DIFFERENTIAL INPUT

VOLTAGE

(V

= 4.096 V)

REF

OUTPUT CODE

(HEX)

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LDO

GND

AVDD DECAP

C

LDO

1 F

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7.3.6 Low-Dropout Regulator (LDO)

To enable single-supply operation, the device features an internal low-dropout regulator (LDO). The LDO is
powered by the AVDD supply, and the 2.85-V (nominal) output is available on the DECAP pin. This LDO output
powers the critical analog blocks within the device, and must not be used for any other external purposes.

Decouple the DECAP pin with the GND pin, as shown in Figure 41, by placing a 1-µF, X7R-grade, ceramic
capacitor with a 6.3-V rating from DECAP to GND. There is no upper limit on the value of the decoupling
capacitor; however, a larger decoupling capacitor results in higher power-up time for the device. See the Layout
section for layout recommendations.

Figure 41. Internal LDO Connections

7.4 Device Functional Modes

The multiplexer includes a sequence control logic that supports various features as described in the Channel

Selection Using Internal Multiplexer section.

7.4.1 Channel Selection Using Internal Multiplexer

The ADS816x includes an 8-channel, linear, and low-leakage current analog multiplexer. The multiplexer
performs a break-before-make operation when switching channels. There are four modes of switching the
multiplexer input channels: manual mode, on-the-fly mode, auto sequence mode, and custom channel
sequencing mode.

These modes can be selected by configuring the SEQ_MODE[1:0] bits in the DEVICE_CFG register. On power­up the default mode is manual mode, SEQ_MODE[1:0] = 00b, and the default input channel is AIN0. The
multiplexer configuration registers can be accessed over the SPI; see Figure 50. The SPI interface eliminates the
need for separate MUX control lines.

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