TEXAS INSTRUMENTS ADS7862 Technical data

®

ADS7862

SBAS101B – JANUARY 1998 – REVISED AUGUST 2005

Dual 500kHz, 12-Bit, 2 + 2 Channel

Simultaneous Sampling

ANALOG-TO-DIGITAL CONVERTER

ADS7862

FEATURES

● 4 INPUT CHANNELS

● FULLY DIFFERENTIAL INPUTS

● 2µs TOTAL THROUGHPUT PER CHANNEL

● GUARANTEED NO MISSING CODES

● PARALLEL INTERFACE

● 1MHz EFFECTIVE SAMPLING RATE

● LOW POWER: 40mW

APPLICATIONS

● MOTOR CONTROL

● MULTI-AXIS POSITIONING SYSTEMS

● 3-PHASE POWER CONTROL

CH A0+
CH A0–

S/H

Amp

CH A1+
CH A1–

REF

REF

CH B0+
CH B0–

OUT

MUX

IN

Internal

2.5V

Reference

S/H

Amp

CDAC

DESCRIPTION

The ADS7862 is a dual 12-bit, 500kHz analog-to-digital
converter (A/D) with 4 fully differential input channels grouped
into two pairs for high speed simultaneous signal acquisition.
Inputs to the sample-and-hold amplifiers are fully differential
and are maintained differential to the input of the A/D con­verter. This provides excellent common-mode rejection of
80dB at 50kHz, which is important in high noise environ­ments.

The ADS7862 offers parallel interface and control inputs to
minimize software overhead. The output data for each channel
is available as a 12-bit word. The ADS7862 is offered in an
TQFP-32 package and is fully specified over the –40°C to
+85°C operating range.

SAR

COMP

COMP

Interface

Conversion

and

Control

Output

Registers

12

A0
CLOCK
CS
RD
BUSY
CONVST

Data Output

CH B1+
CH B1–

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

MUX

CDAC

SAR

Copyright © 1998-2005, Texas Instruments Incorporated

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ORDERING INFORMATION

MAXIMUM MAXIMUM
RELATIVE GAIN SPECIFICATION

PRODUCT (LSB) (%) PACKAGE DESIGNATOR RANGE NUMBER MEDIA, QUANTITY

ADS7862Y ±2 ±0.75 TQFP-32 PBS –40°C to +85°C ADS7862Y/250 Tape and Reel, 250
ADS7862Y
ADS7862YB ±1 ±0.5 TQFP-32 PBS –40°C to +85°C ADS7862YB/250 Tape and Reel, 250
ADS7862YB

NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI website at www.ti.com.

ACCURACY ERROR PACKAGE TEMPERATURE ORDERING TRANSPORT

"" " " "ADS7862Y/2K5 Tape and Reel, 2500
"" " " "ADS7862YB/2K5 Tape and Reel, 2500

(1)

ABSOLUTE MAXIMUM RATINGS

Analog Inputs to AGND: Any Channel Input ........ –0.3V to (+VD + 0.3V)

Digital Inputs to DGND .......................................... –0.3V to (+V

Ground Voltage Differences: AGND, DGND ................................... ±0.3V

Power Dissipation .......................................................................... 325mW

Maximum Junction Temperature................................................... +150°C

Operating Temperature Range ........................................–40°C to +85°C

Storage Temperature Range ......................................... –65°C to +150°C

Lead Temperature (soldering, 10s)............................................... +300°C

REF

............................. –0.3V to (+VD + 0.3V)

IN

+V

to AGND ......................... –0.3V to +6V

D

+ 0.3V)

D

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru­ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and
installation procedures can cause damage.

ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes
could cause the device not to meet its published specifications.

PIN CONFIGURATION

Top View

CH A0+

CH A0–

CH A1+

CH A1–

CH B0–

CH B0+

CH B1–

CH B1+

REF

REF

AGND

DB11
DB10

OUT

+V

DB9
DB8

32 31 30 29 28

1

IN

2
3
4

A

5
6
7
8

9 10111213141516

DB7

DB6

ADS7862

DB5

DB4

27 26 25

DB3

DB2

DB1

DB0

24
23
22
21
20
19
18
17

+V

D

DGND
A0
RD
CS
CLOCK
CONVST
BUSY

PIN DESCRIPTIONS

PIN NAME DESCRIPTION

1REF
2 REF

3 AGND Analog Ground
4+V

5 DB11 Data Bit 11, MSB
6 DB10 Data Bit 10
7 DB9 Data Bit 9
8 DB8 Data Bit 8

9 DB7 Data Bit 7
10 DB6 Data Bit 6
11 DB5 Data Bit 5
12 DB4 Data Bit 4
13 DB3 Data Bit 3
14 DB2 Data Bit 2
15 DB1 Data Bit 1
16 DB0 Data Bit 0, LSB
17 BUSY HIGH when a conversion is in progress.
18 CONVST Convert Start
19 CLOCK An external CMOS-compatible clock can be applied to

20 CS Chip Select
21 RD Synchronization pulse for the parallel output. During a

22 A0 On the falling edge of Convert Start, when A0 is LOW

23 DGND Digital Ground. Connect directly to analog ground (pin 3).
24 +V
25 CH B1+ Non-Inverting Input Channel B1
26 CH B1– Inverting Input Channel B1
27 CH B0+ Non-Inverting Input Channel B0
28 CH B0– Inverting Input Channel B0
29 CH A1– Inverting Input Channel A1
30 CH A1+ Non-Inverting Input Channel A1
31 CH A0– Inverting Input Channel A0
32 CH A0+ Non-Inverting Input Channel A0

Reference Input

IN

+2.5V Reference Output. Connect directly to REF

OUT

(pin 1) when using internal reference.

Analog Power Supply, +5VDC. Connect directly to

A

digital power supply (pin 24). Decouple to analog
ground with a 0.1µF ceramic capacitor and a 10µF
tantalum capacitor.

the CLOCK input to synchronize the conversion pro­cess to an external source. The CLOCK pin controls
the sampling rate by the equation: CLOCK 16 • f

Read operation, the first falling edge selects the A
register and the second edge selects the B register,
A0, then controls whether input 0 or input 1 is read.

Channel A0 and Channel B0 are converted and when
it is HIGH, Channel A1 and Channel B1 are converted.
During a Read operation, the first falling edge selects
the A register and the second edge selects the B of RD
register, A0, then controls whether input 0 or input 1 is
read.

Digital Power Supply, +5VDC

D

SAMPLE

IN

.

2

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ADS7862

SBAS101B

ELECTRICAL CHARACTERISTICS

All specifications T

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
RESOLUTION 12 ✻ Bits

ANALOG INPUT

Input Voltage Range-Bipolar V
Absolute Input Range +IN –0.3 V

Input Capacitance 15 ✻ pF
Input Leakage Current CLK = GND ±1 ✻ µA

SYSTEM PERFORMANCE

No Missing Codes 12 ✻ Bits
Integral Linearity ±0.75 ±2 ±0.5 ±1 LSB
Integral Linearity Match 0.5 1 ✻✻ LSB
Differential Linearity ±0.75 ±0.5 ±1 LSB
Bipolar Offset Error Referenced to REF
Bipolar Offset Error Match 3 2 LSB
Positive Gain Error Referenced to REF
Positive Gain Error Match 2 1 LSB
Negative Gain Error Referenced to REF
Negative Gain Error Match 2 1 LSB
Common-Mode Rejection Ratio At DC 80 ✻ dB

Noise 120 ✻ µV
Power Supply Rejection Ratio ±0.5 ±2 ✻✻ LSB

SAMPLING DYNAMICS

Conversion Time per A/D 1.75 ✻ µs
Acquisition Time 0.25 ✻ µs
Throughput Rate 500 ✻ kHz
Aperture Delay 3.5 ✻ ns
Aperture Delay Matching 100 ✻ ps
Aperture Jitter 50 ✻ ps
Small-Signal Bandwidth 40 ✻ MHz

DYNAMIC CHARACTERISTICS

Total Harmonic Distortion V
SINAD V
Spurious Free Dynamic Range V
Channel-to-Channel Isolation V

VOLTAGE REFERENCE

Internal 2.475 2.5 2.525 ✻✻✻ V
Internal Drift ±25 ✻ ppm/°C
Internal Noise 50 ✻ µV
Internal Source Current 2 ✻ mA
Internal Load Rejection 0.005 ✻ mV/µA
Internal PSRR 65 ✻ dB
External Voltage Range 1.2 2.5 2.6 ✻✻✻ V
Input Current 0.05 1 ✻✻ µA
Input Capacitance 5 ✻ pF

DIGITAL INPUT/OUTPUT

Logic Family CMOS ✻
Logic Levels: V

External Clock 0.2 8 ✻✻MHz
Data Format Binary Two’s Complement ✻

POWER SUPPLY REQUIREMENTS

Power Supply Voltage, +V 4.75 5 5.25 ✻✻✻ V
Quiescent Current, +V
Power Dissipation 25 40 ✻✻ mW

✻ Specifications same as ADS7862Y.

to T

MIN

, +VA = +VD = +5V, V

MAX

= internal +2.5V and f

REF

= 8MHz, f

CLK

= 500kHz, unless otherwise noted.

SAMPLE

ADS7862Y ADS7862YB

= Internal V

CENTER

–IN –0.3 V

V

= ±1.25VPP at 50kHz 80 ✻ dB

IN

= ±2.5VPP at 100kHz 75 ✻ dB

IN

= ±2.5VPP at 100kHz 71 ✻ dB

IN

= ±2.5VPP at 100kHz –78 ✻ dB

IN

= ±2.5VPP at 100kHz –80 ✻ dB

IN

IH

V

IL

V

OH

V

OL

A

IIH = +5µA 3.0
IIL = +5µA –0.3 0.8 ✻✻V

IOH = –500µA 3.5 ✻ V

IOL = 500µA 0.4 ✻ V

at 2.5V –V

REF

IN

IN

IN

REF

+V

REF

+ 0.3 V

CC

+ 0.3 V

CC

✻✻V

±0.75 ±3 ±0.5 ±2 LSB

±0.15 ±0.75 ±0.1 ±0.5 % of FSR

±0.15 ±0.75 ±0.1 ±0.5 % of FSR

+VDD + 0.3

✻✻V

58 ✻✻ mA

RMS

PP

ADS7862

SBAS101B

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3

BASIC OPERATION

+5V

Analog Supply

+

10µF

+

0.1µF

32

31

30

29

28

27

26

25

CH A0–

CH A1–

CH B0–

DB3
13

CH B1–

CH B0+

DB2

DB1

14

15

CH B1+

+V

DGND

A0
RD
CS

CLOCK

CONVST

BUSY

DB0
16

24

D

23
22
21
20
19
18
17

Address Select
Read Input
Chip Select
Clock Input
Conversion Start
Busy Output

CH A0+

DB7
9

CH A1+

ADS7862Y

DB6

DB5

10

11

DB4
12

1

REF

IN

2

REF

OUT

3

AGND

4

+V

A

5

DB11

6

DB10

7

DB9

8

DB8

4

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ADS7862

SBAS101B

TYPICAL PERFORMANCE CHARACTERISTICS

At TA = +25°C, +VA = +VD = +5V, V

= internal +2.5V and f

REF

= 8MHz, f

CLK

= 500kHz, unless otherwise noted.

SAMPLE

FREQUENCY SPECTRUM

0

–20

–40

–60

Amplitude (dB)

–80

–100

–120

0 62.5 125 250187.5

76

74

72

70

68

SNR and SINAD (dB)

66

64

(4096 Point FFT; f

Frequency (kHz)

SIGNAL-TO-NOISE RATIO AND

SIGNAL-TO-(NOISE+DISTORTION)

vs INPUT FREQUENCY

SNR

SINAD

10k 100k1k 1M

Input Frequency (Hz)

= 99.9kHz, –0.5dB)

IN

FREQUENCY SPECTRUM

0

–20

–40

–60

Amplitude (dB)

–80

–100

–120

0 62.5 125 250187.5

0.25

0.2

0.15

0.1

0.05
0

–0.05

–0.1

Delta from +25°C (dB)

–0.15

–0.2

–0.25

–40 25 85

(4096 Point FFT; f

CHANGE IN SIGNAL-TO-NOISE RATIO

AND SIGNAL-TO-(NOISE+DISTORTION)

vs TEMPERATURE

SINAD

SNR

= 199.9kHz, –0.5dB)

IN

Frequency (kHz)

Temperature (°C)

0.65

0.45

0.25

0.05

–0.15

–0.35

SFDR Delta from +25°C (dB)

–0.55

–0.75

ADS7862

SBAS101B

CHANGE IN SPURIOUS FREE DYNAMIC RANGE

AND TOTAL HARMONIC DISTORTION

vs TEMPERATURE

SFDR

THD

–40 25 85

Temperature (°C)

0.65

0.45

0.25

0.05

–0.15

–0.35

THD Delta from +25°C (dB)

–0.55

–0.75

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CHANGE IN POSITIVE GAIN MATCH

vs TEMPERATURE

(Maximum Deviation for All Four Channels)

0.6

0.5

0.4

0.3

0.2

0.1

Change in Positive Gain Match (LSB)

0

–40 25 85 150

Temperature (°C)

5