ADS7841
ADS7841
ADS7841
SBAS084B – JULY 2001
12-Bit, 4-Channel Serial Output Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
● SINGLE SUPPLY: 2.7V to 5V
● 4-CHANNEL SINGLE-ENDED OR
2-CHANNEL DIFFERENTIAL INPUT
● UP TO 200kHz CONVERSION RATE
● ±1LSB MAX INL AND DNL
● NO MISSING CODES
● 72dB SINAD
● SERIAL INTERFACE
● DIP-16 OR SSOP-16 PACKAGE
● ALTERNATE SOURCE FOR MAX1247
● ADS7841ES: +125°C Version
APPLICATIONS
● DATA ACQUISITION
● TEST AND MEASUREMENT
● INDUSTRIAL PROCESS CONTROL
● PERSONAL DIGITAL ASSISTANTS
● BATTERY-POWERED SYSTEMS
DESCRIPTION
The ADS7841 is a 4-channel, 12-bit sampling Analog-toDigital Converter (ADC) with a synchronous serial interface. The resolution is programmable to either 8 bits or 12
bits. Typical power dissipation is 2mW at a 200kHz throughput rate and a +5V supply. The reference voltage (V
be varied between 100mV and VCC, providing a corresponding input voltage range of 0V to V
. The device includes
REF
a shutdown mode which reduces power dissipation to under
15µW. The ADS7841 is tested down to 2.7V operation.
Low power, high speed, and on-board multiplexer make the
ADS7841 ideal for battery-operated systems such as personal digital assistants, portable multi-channel data loggers,
and measurement equipment. The serial interface also provides low-cost isolation for remote data acquisition. The
ADS7841 is available in a DIP-16 or a SSOP-16 package
and is specified over the –40°C to +125°C
(1)
temperature
range.
NOTE: (1) ES grade only.
REF
) can
CH0
CH1
CH2
CH3
COM
V
REF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Four
Channel
Multiplexer
CDAC
SAR
www.ti.com
Comparator
DCLK
CS
Serial
Interface
and
Control
Copyright © 2000, Texas Instruments Incorporated
SHDN
DIN
DOUT
MODE
BUSY
ABSOLUTE MAXIMUM RATINGS
+V
to GND ........................................................................ –0.3V to +6V
CC
Analog Inputs to GND ............................................ –0.3V to +V
Digital Inputs to GND ........................................................... –0.3V to +6V
Power Dissipation .......................................................................... 250mW
Maximum Junction Temperature................................................... +150°C
Operating Temperature Range .................................. –40°C to +125°C
Storage Temperature Range .........................................–65°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
NOTES: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability. (2) ADS7841ES
0nly. All other grades are: –40°C to +85°C.
(1)
+ 0.3V
CC
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
(2)
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
PACKAGE/ORDERING INFORMATION
MINIMUM MAXIMUM
RELATIVE GAIN SPECIFICATION PACKAGE
ACCURACY ERROR TEMPERATURE PACKAGE DRAWING ORDERING TRANSPORT
PRODUCT (LSB) (LSB) RANGE PACKAGE DESIGNATOR NUMBER NUMBER
ADS7841E ±2 ±4 –40°C to +85°C SSOP-16 DBQ 322 ADS7841E Rails
" " " " " " " ADS7841E/2K5 Tape and Reel
ADS7841P ±2 " –40°C to +85°C DIP-16 N 180 ADS7841P Rails
ADS7841EB ±1 ±3 –40°C to +85°C SSOP-16 DBQ 322 ADS7841EB Rails
" " " " " " " ADS7841EB/2K5 Tape and Reel
ADS7841PB ±1 " –40°C to +85°C DIP-16 N 180 ADS7841PB Rails
ADS7841ES ±2 ±4 –40°C to +125°C SSOP-16 DBQ 322 ADS7841ES/2K5 Tape and Reel
NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces
of “ADS7841E/2K5” will get a single 2500-piece Tape and Reel.
specifications.
(1)
MEDIA
PIN CONFIGURATIONS
Top View
+V
CH0
CH1
CH2
CH3
COM
SHDN
V
REF
1
CC
2
3
4
5
6
7
8
DIP
ADS7841
SSOP
DCLK
16
CS
15
DIN
14
BUSY
13
DOUT
12
MODE
11
GND
10
+V
9
CC
+V
CH0
CH1
CH2
CH3
COM
SHDN
V
REF
1
CC
2
3
4
5
6
7
8
ADS7841
DCLK
16
CS
15
DIN
14
BUSY
13
DOUT
12
MODE
11
GND
10
+V
9
CC
PIN DESCRIPTIONS
PIN NAME DESCRIPTION
1+VCCPower Supply, 2.7V to 5V
2 CH0 Analog Input Channel 0
3 CH1 Analog Input Channel 1
4 CH2 Analog Input Channel 2
5 CH3 Analog Input Channel 3
6 COM Ground Reference for Analog Inputs. Sets zero code voltage in single-ended mode. Connect this pin to ground or ground reference
7 SHDN Shutdown. When LOW, the device enters a very low power shutdown mode.
8V
9+V
10 GND Ground
11 MODE Conversion Mode. When LOW, the device always performs a 12-bit conversion. When HIGH, the resolution is set by the MODE bit in
12 DOUT Serial Data Output. Data is shifted on the falling edge of DCLK. This output is high impedance when CS is HIGH.
13 BUSY Busy Output. This output is high impedance when CS is HIGH.
14 DIN Serial Data Input. If CS is LOW, data is latched on rising edge of DCLK.
15 CS Chip Select Input. Controls conversion timing and enables the serial input/output register.
16 DCLK External Clock Input. This clock runs the SAR conversion process and synchronizes serial data I/O.
REF
CC
point.
Voltage Reference Input
Power Supply, 2.7V to 5V
the CONTROL byte.
2
ADS7841
SBAS084B
ELECTRICAL CHARACTERISTICS: +5V
At TA = T
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
ANALOG INPUT
Full-Scale Input Span
Absolute Input Range Positive Input –0.2
Capacitance 25 ✻✻pF
Leakage Current 200 200 200 nA
SYSTEM PERFORMANCE
Resolution 12 ✻✻Bits
No Missing Codes 12 12 11 Bits
Integral Linearity Error ±2 ±1 2 LSB
Differential Linearity Error ±0.8 ±0.5 ±1 ±0.8 LSB
Offset Error ±3 ✻✻LSB
Offset Error Match 0.15 1.0 ✻✻ ✻✻LSB
Gain Error ±4 ±3 ±4 LSB
Gain Error Match 0.1 1.0 ✻✻ ✻✻LSB
Noise 30 ✻✻µVrms
Power-Supply Rejection 70 ✻✻dB
SAMPLING DYNAMICS
Conversion Time 12 ✻✻Clk Cycles
Acquisition Time 3 ✻✻Clk Cycles
Throughput Rate 200 ✻✻kHz
Multiplexer Settling Time 500 ✻✻ns
Aperture Delay 30 ✻✻ns
Aperture Jitter 100 ✻✻ps
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion
Signal-to-(Noise + Distortion) V
Spurious-Free Dynamic Range
Channel-to-Channel Isolation V
REFERENCE INPUT
Range 0.1 +V
Resistance DCLK Static 5 ✻✻GΩ
Input Current 40 100 ✻✻ ✻✻µA
DIGITAL INPUT/OUTPUT
Logic Family CMOS ✻✻
Logic Levels
Data Format Straight Binary ✻✻
PWR SUPPLY REQUIREMENTS
+V
Quiescent Current 550 900 ✻✻µA
Power Dissipation 4.5 ✻✻mW
TEMPERATURE RANGE
Specified Performance –40 +85 ✻✻✻+125 °C
to T
MIN
, +VCC = +5V, V
MAX
REF
= +5V, f
= 200kHz, and f
SAMPLE
Positive Input - Negative Input
CLK
= 16 • f
= 3.2MHz, unless otherwise noted.
SAMPLE
ADS7841E, P ADS7841EB, PB
0V
REF
+VCC +0.2
✻✻✻ ✻V
✻✻✻ ✻V
ADS7841ES
Negative Input –0.2 +1.25 ✻✻✻ ✻V
(1)
(2)
VIN = 5Vp-p at 10kHz –78 –72 –80 –76 –78 –72 dB
= 5Vp-p at 10kHz 68 71 70 72 68 71 dB
IN
VIN = 5Vp-p at 10kHz 72 79 76 81 72 79 dB
= 5Vp-p at 50kHz 120 ✻ 120 dB
IN
✻✻✻ ✻V
CC
f
= 12.5kHz 2.5 ✻✻µA
SAMPLE
DCLK Static 0.001 3 ✻✻ ✻✻µA
V
IH
V
IL
V
OH
V
OL
CC
| IIH | ≤ +5µA 3.0 5.5 ✻✻✻ ✻V
| IIL | ≤ +5µA –0.3 +0.8 ✻✻✻ ✻V
IOH = –250µA 3.5 ✻✻ V
IOL = 250µA 0.4 ✻✻V
Specified Performance
f
= 12.5kHz 300 ✻✻µA
SAMPLE
Power-Down Mode
(3)
, CS = +V
4.75 5.25 ✻✻✻ ✻V
CC
3 ✻✻µA
✻ Same specifications as ADS7841E, P.
NOTE: (1) LSB means Least Significant Bit. With V
(PD1 = PD0 = 0) active or SHDN = GND.
ADS7841
SBAS084B
equal to +5.0V, one LSB is 1.22mV. (2) First five harmonics of the test frequency. (3) Auto power-down mode
REF
3
ELECTRICAL CHARACTERISTICS: +2.7V
At TA = –40°C to +85°C, +VCC = +2.7V, V
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
ANALOG INPUT
Full-Scale Input Span Positive Input - Negative Input 0 V
Absolute Input Range Positive Input –0.2 +V
Capacitance 25 ✻ pF
Leakage Current ±1 ✻ µA
SYSTEM PERFORMANCE
Resolution 12 ✻ Bits
No Missing Codes 12 12 Bits
Integral Linearity Error ±2 ±1 LSB
Differential Linearity Error ±0.8 ±0.5 ±1 LSB
Offset Error ±3 ✻ LSB
Offset Error Match 0.15 1.0 ✻✻LSB
Gain Error ±4 ±3 LSB
Gain Error Match 0.1 1.0 ✻✻ LSB
Noise 30 ✻ µVrms
Power-Supply Rejection 70 ✻ dB
SAMPLING DYNAMICS
Conversion Time 12 ✻ Clk Cycles
Acquisition Time 3 ✻ Clk Cycles
Throughput Rate 125 ✻ kHz
Multiplexer Settling Time 500 ✻ ns
Aperture Delay 30 ✻ ns
Aperture Jitter 100 ✻ ps
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion
(2)
Signal-to-(Noise + Distortion) V
Spurious-Free Dynamic Range V
Channel-to-Channel Isolation V
REFERENCE INPUT
Range 0.1 +V
Resistance DCLK Static 5 ✻ GΩ
Input Current 13 40 ✻✻ µA
DIGITAL INPUT/OUTPUT
Logic Family CMOS ✻
Logic Levels
V
IH
V
IL
V
OH
V
OL
Data Format Straight Binary ✻
POWER SUPPLY REQUIREMENTS
+V
CC
Quiescent Current 280 650 ✻✻ µA
Power Dissipation 1.8 ✻ mW
TEMPERATURE RANGE
Specified Performance –40 +85 ✻✻°C
= +2.5V, f
REF
= 125kHz, and f
SAMPLE
CLK
= 16 • f
= 2MHz, unless otherwise noted.
SAMPLE
ADS7841E, P ADS7841EB, PB
REF
+0.2 ✻✻V
Negative Input –0.2 +0.2 ✻✻V
CC
✻✻V
VIN = 2.5Vp-p at 10kHz –77 –72 –79 –76 dB
= 2.5Vp-p at 10kHz 68 71 70 72 dB
IN
= 2.5Vp-p at 10kHz 72 78 76 80 dB
IN
= 2.5Vp-p at 50kHz 100 ✻ dB
IN
CC
f
= 12.5kHz 2.5 ✻ µA
SAMPLE
DCLK Static 0.001 3 ✻✻ µA
| I
| ≤ +5µA+V
IH
| I
| ≤ +5µA –0.3 +0.8 ✻✻V
IL
IOH = –250µA+V
IOL = 250µA 0.4 ✻ V
• 0.7 5.5 ✻✻V
CC
• 0.8 ✻ V
CC
✻✻V
Specified Performance 2.7 3.6 ✻✻V
f
= 12.5kHz 220 ✻ µA
SAMPLE
Power-Down Mode
(3)
, CS = +V
CC
3 ✻ µA
(1)
✻ Same specifications as ADS7841E, P.
NOTE: (1) LSB means Least Significant Bit. With V
(PD1 = PD0 = 0) active or SHDN = GND.
4
equal to +2.5V, one LSB is 610mV. (2) First five harmonics of the test frequency. (3) Auto power-down mode
REF
ADS7841
SBAS084B
TYPICAL CHARACTERISTICS: +5V
0
–20
–40
–60
–80
–100
–120
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 10.3kHz, –0.2dB)
0 10025 7550
Frequency (kHz)
Amplitude (dB)
CHANGE IN SIGNAL-TO-(NOISE+DISTORTION)
vs TEMPERATURE
–20–40 100
Temperature (°C)
Delta from +25°C (dB)
0.4
0.2
0.0
–0.2
–0.4
–0.6
0.6
0 20 40 60 80
fIN = 10kHz, –0.2dB
At TA = +25°C, +VCC = +5V, V
(4096 Point FFT; fIN = 1,123Hz, –0.2dB)
0
–20
–40
–60
–80
Amplitude (dB)
–100
–120
0 10025 7550
= +5V, f
REF
FREQUENCY SPECTRUM
Frequency (kHz)
= 200kHz, and f
SAMPLE
CLK
= 16 • f
SAMPLE
= 3.2MHz, unless otherwise noted.
SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-
(NOISE+DISTORTION) vs INPUT FREQUENCY
74
73
72
SINAD
71
70
SNR and SINAD (dB)
69
68
12.0
11.8
11.6
SNR
101 100
Input Frequency (kHz)
EFFECTIVE NUMBER OF BITS
vs INPUT FREQUENCY
85
80
75
SFDR (dB)
70
65
SPURIOUS-FREE DYNAMIC RANGE AND TOTAL
HARMONIC DISTORTION vs INPUT FREQUENCY
–85
SFDR
–80
THD
–75
THD (dB)
–70
–65
101 100
Input Frequency (kHz)
ADS7841
11.4
Effective Number of Bits
11.2
11.0
Input Frequency (kHz)
SBAS084B
101 100
5
TYPICAL CHARACTERISTICS: +2.7V
At TA = +25°C, +VCC = +2.7V, V
= +2.5V, f
REF
= 125kHz, and f
SAMPLE
CLK
= 16 • f
SAMPLE
= 2MHz, unless otherwise noted.
(4096 Point FFT; fIN = 1,129Hz, –0.2dB)
0
–20
–40
–60
–80
Amplitude (dB)
–100
–120
0 62.515.6 46.931.3
SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-
(NOISE+DISTORTION) vs INPUT FREQUENCY
78
74
70
66
62
SNR and SINAD (dB)
58
54
FREQUENCY SPECTRUM
Frequency (kHz)
SNR
SINAD
101 100
Input Frequency (kHz)
(4096 Point FFT; fIN = 10.6kHz, –0.2dB)
0
–20
–40
–60
–80
Amplitude (dB)
–100
–120
0 62.515.6 46.931.3
SPURIOUS-FREE DYNAMIC RANGE AND TOTAL
HARMONIC DISTORTION vs INPUT FREQUENCY
90
85
80
75
70
65
SFDR (dB)
60
55
50
FREQUENCY SPECTRUM
Frequency (kHz)
SFDR
THD
101 100
Input Frequency (kHz)
–90
–85
–80
–75
–70
–65
–60
–55
–50
THD (dB)
12.0
11.5
11.0
10.5
10.0
Effective Number of Bits
9.5
9.0
6
EFFECTIVE NUMBER OF BITS
vs INPUT FREQUENCY
101 100
Input Frequency (kHz)
0.4
0.2
0.0
–0.2
–0.4
Delta from +25°C (dB)
–0.6
–0.8
CHANGE IN SIGNAL-TO-(NOISE+DISTORTION)
fIN = 10kHz, –0.2dB
–20–40 100
vs TEMPERATURE
0 20 40 60 80
Temperature (˚C)
ADS7841
SBAS084B
Output Code
1.00
0.75
0.50
0.25
0.00
–0.25
–0.50
–0.75
–1.00
DIFFERENTIAL LINEARITY ERROR vs CODE
800
H
FFF
H
000
H
DLE (LSB)
TYPICAL CHARACTERISTICS: +2.7V (Cont.)
At TA = +25°C, +VCC = +2.7V, V
SUPPLY CURRENT vs TEMPERATURE
400
= +2.5V, f
REF
= 125kHz, and f
SAMPLE
CLK
= 16 • f
= 2MHz, unless otherwise noted.
SAMPLE
140
POWER DOWN SUPPLY CURRENT
vs TEMPERATURE
350
300
250
200
Supply Current (µA)
150
100
1.00
0.75
0.50
0.25
0.00
ILE (LSB)
–0.25
–0.50
–0.75
–1.00
000
20–40 100–20 0 40
Temperature (˚C)
INTEGRAL LINEARITY ERROR vs CODE
800
H
H
Output Code
60 80
FFF
120
100
80
60
Supply Current (nA)
40
20
20–40 100–20 0 40
60 80
Temperature (˚C)
H
0.15
CHANGE IN GAIN vs TEMPERATURE
0.10
0.05
0.00
–0.05
Delta from +25˚C (LSB)
–0.10
–0.15
ADS7841
SBAS084B
20–40 100–20 0 40
Temperature (˚C)
60 80
0.6
0.4
0.2
0.0
–0.2
Delta from +25˚C (LSB)
–0.4
–0.6
CHANGE IN OFFSET vs TEMPERATURE
20–40 100–20 0 40
60 80
Temperature (˚C)
7
TYPICAL CHARACTERISTICS: +2.7V (Cont.)
At TA = +25°C, +VCC = +2.7V, V
= +2.5V, f
REF
= 125kHz, and f
SAMPLE
CLK
= 16 • f
= 2MHz, unless otherwise noted.
SAMPLE
REFERENCE CURRENT vs SAMPLE RATE
14
12
10
18
16
14
REFERENCE CURRENT vs TEMPERATURE
8
12
6
4
Reference Current (µA)
2
0
750 12525 50 100
Sample Rate (kHz)
SUPPLY CURRENT vs +V
CC
320
10
Reference Current (µA)
8
6
20–40 100–20 0 40
60 80
Temperature (˚C)
MAXIMUM SAMPLE RATE vs +V
CC
1M
300
f
= 12.5kHz
SAMPLE
280
260
V
REF
= +VCC
100k
240
10k
220
Supply Current (µA)
200
180
3.5252.5 4
(V)
+V
CC
4.53
Sample Rate (Hz)
1k
3.5252.5 4
+V
(V)
CC
V
REF
= +VCC
4.53
8
ADS7841
SBAS084B
Converter
+IN
–IN
CH0
CH1
CH2
CH3
COM
A2-A0
(Shown 001
B
)
SGL/DIF
(Shown HIGH)
THEORY OF OPERATION
The ADS7841 is a classic Successive Approximation Register (SAR) ADC. The architecture is based on capacitive
redistribution that inherently includes a sample-and-hold
function. The converter is fabricated on a 0.6µs CMOS
process.
The basic operation of the ADS7841 is shown in Figure 1.
The device requires an external reference and an external
clock. It operates from a single supply of 2.7V to 5.25V. The
external reference can be any voltage between 100mV and
+VCC. The value of the reference voltage directly sets the
input range of the converter. The average reference input
current depends on the conversion rate of the ADS7841.
The analog input to the converter is differential and is
provided via a four-channel multiplexer. The input can be
provided in reference to a voltage on the COM pin (which
is generally ground) or differentially by using two of the four
input channels (CH0 - CH3). The particular configuration is
selectable via the digital interface.
The input current on the analog inputs depends on the
conversion rate of the device. During the sample period, the
source must charge the internal sampling capacitor (typically 25pF). After the capacitor has been fully charged, there
is no further input current. The rate of charge transfer from
the analog source to the converter is a function of conversion rate.
A2 A1 A0 CH0 CH1 CH2 CH3 COM
001+IN –IN
101 +IN –IN
010 +IN –IN
110 +IN–IN
TABLE I. Single-Ended Channel Selection (SGL/DIF HIGH).
A2 A1 A0 CH0 CH1 CH2 CH3 COM
001+IN–IN
101–IN +IN
010 +IN–IN
110 –IN +IN
ANALOG INPUT
Figure 2 shows a block diagram of the input multiplexer on
the ADS7841. The differential input of the converter is
derived from one of the four inputs in reference to the COM
pin or two of the four inputs. Table I and Table II show the
relationship between the A2, A1, A0, and SGL/DIF control
bits and the configuration of the analog multiplexer. The
control bits are provided serially via the DIN pin, see the
Digital Interface section of this data sheet for more details.
When the converter enters the hold mode, the voltage
difference between the +IN and –IN inputs (as shown in
Figure 2) is captured on the internal capacitor array. The
voltage on the –IN input is limited between –0.2V and
1.25V, allowing the input to reject small signals that are
common to both the +IN and –IN input. The +IN input has
a range of –0.2V to +VCC + 0.2V.
+2.7V to +5V
+
1µF
to
10µF
Single-ended
or differential
analog inputs
0.1µF
0.1µF
TABLE II. Differential Channel Control (SGL/DIF LOW).
FIGURE 2. Simplified Diagram of the Analog Input.
ADS7841
1
+V
CC
2
CH0
3
CH1
4
CH2
5
CH3
6
COM
7
SHDN
8
V
REF
DCLK
CS
DIN
BUSY
DOUT
MODE
GND
+V
16
15
14
13
12
11
10
9
CC
Serial/Conversion Clock
Chip Select
Serial Data In
Serial Data Out
FIGURE 1. Basic Operation of the ADS7841.
ADS7841
SBAS084B
9
REFERENCE INPUT
The external reference sets the analog input range. The
ADS7841 will operate with a reference in the range of
100mV to +V
. Keep in mind that the analog input is the
CC
difference between the +IN input and the –IN input, see
Figure 2. For example, in the single-ended mode, a 1.25V
reference, and with the COM pin grounded, the selected input
channel (CH0 - CH3) will properly digitize a signal in the
range of 0V to 1.25V. If the COM pin is connected to 0.5V,
the input range on the selected channel is 0.5V to 1.75V.
There are several critical items concerning the reference input
and its wide voltage range. As the reference voltage is reduced, the analog voltage weight of each digital output code
is also reduced. This is often referred to as the LSB (least
significant bit) size and is equal to the reference voltage
divided by 4096. Any offset or gain error inherent in the ADC
will appear to increase, in terms of LSB size, as the reference
voltage is reduced. For example, if the offset of a given
converter is 2LSBs with a 2.5V reference, then it will typically
be 10LSBs with a 0.5V reference. In each case, the actual
offset of the device is the same, 1.22mV.
Likewise, the noise or uncertainty of the digitized output will
increase with lower LSB size. With a reference voltage of
100mV, the LSB size is 24µV. This level is below the
internal noise of the device. As a result, the digital output
code will not be stable and vary around a mean value by a
number of LSBs. The distribution of output codes will be
gaussian and the noise can be reduced by simply averaging
consecutive conversion results or applying a digital filter.
With a lower reference voltage, care should be taken to
provide a clean layout including adequate bypassing, a clean
(low-noise, low-ripple) power supply, a low-noise reference,
and a low-noise input signal. Because the LSB size is lower,
the converter will also be more sensitive to nearby digital
signals and electromagnetic interference.
The voltage into the V
input is not buffered and directly
REF
drives the Capacitor Digital-to-Analog Converter (CDAC)
portion of the ADS7841. Typically, the input current is
13µA with a 2.5V reference. This value will vary by
microamps depending on the result of the conversion. The
reference current diminishes directly with both conversion
rate and reference voltage. As the current from the reference
is drawn on each bit decision, clocking the converter more
quickly during a given conversion period will not reduce
overall current drain from the reference.
DIGITAL INTERFACE
Figure 3 shows the typical operation of the ADS7841’s
digital interface. This diagram assumes that the source of the
digital signals is a microcontroller or digital signal processor
with a basic serial interface (note that the digital inputs are
over-voltage tolerant up to 5.5V, regardless of +V
). Each
CC
communication between the processor and the converter
consists of eight clock cycles. One complete conversion can
be accomplished with three serial communications, for a
total of 24 clock cycles on the DCLK input.
The first eight clock cycles are used to provide the control
byte via the DIN pin. When the converter has enough
information about the following conversion to set the input
multiplexer appropriately, it enters the acquisition (sample)
mode. After three more clock cycles, the control byte is
complete and the converter enters the conversion mode. At
this point, the input sample-and-hold goes into the hold
mode. The next twelve clock cycles accomplish the actual
Analog-to-Digital conversion. A thirteenth clock cycle is
needed for the last bit of the conversion result. Three more
clock cycles are needed to complete the last byte (DOUT
will be LOW). These will be ignored by the converter.
CS
t
ACQ
DCLK
DIN
BUSY
DOUT
1
(START)
81
A2S
A1 A0
SGL/
MODE
PD1 PD0
DIF
AcquireIdle Conversion Idle
1098765 4 3210 Zero Filled...
11
(MSB)
81 8
(LSB)
FIGURE 3. Conversion Timing, 24-Clocks per Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated
serial port.
10
ADS7841
SBAS084B
Control Byte
Also shown in Figure 3 is the placement and order of the
control bits within the control byte. Tables III and IV give
detailed information about these bits. The first bit, the ‘S’ bit,
must always be HIGH and indicates the start of the control
byte. The ADS7841 will ignore inputs on the DIN pin until
the start bit is detected. The next three bits (A2 - A0) select
the active input channel or channels of the input multiplexer
(see Tables I and II and Figure 2).
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
(MSB) (LSB)
S A2 A1 A0 MODE SGL/DIF PD1 PD0
TABLE III. Order of the Control Bits in the Control Byte.
BIT NAME DESCRIPTION
7 S Start Bit. Control byte starts with first HIGH bit on
DIN. A new control byte can start every 15th clock
cycle in 12-bit conversion mode or every 11th clock
cycle in 8-bit conversion mode.
6 - 4 A2 - A0 Channel Select Bits. Along with the SGL/DIF bit,
these bits control the setting of the multiplexer input,
see Tables I and II.
3 MODE 12-Bit/8-Bit Conversion Select Bit. If the MODE pin
is HIGH, this bit controls the number of bits for the
next conversion: 12-bits (LOW) or 8-bits (HIGH). If
the MODE pin is LOW, this bit has no function and
the conversion is always 12 bits.
2 SGL/DIF Single-Ended/Differential Select Bit. Along with bits
A2 - A0, this bit controls the setting of the multiplexer
input, see Tables I and II.
1 - 0 PD1 - PD0 Power-Down Mode Select Bits. See Table V for
details.
TABLE IV.Descriptions of the Control Bits within the
Control Byte.
The MODE bit and the MODE pin work together to determine the number of bits for a given conversion. If the
MODE pin is LOW, the converter always performs a 12-bit
conversion regardless of the state of the MODE bit. If the
MODE pin is HIGH, then the MODE bit determines the
number of bits for each conversion, either 12 bits (LOW) or
8 bits (HIGH).
The SGL/DIF bit controls the multiplexer input mode: either
single-ended (HIGH) or differential (LOW). In single-ended
mode, the selected input channel is referenced to the COM
pin. In differential mode, the two selected inputs provide a
differential input. See Tables I and II and Figure 2 for more
information. The last two bits (PD1 - PD0) select the powerdown mode, as shown in Table V. If both inputs are HIGH,
the device is always powered up. If both inputs are LOW,
the device enters a power-down mode between conversions.
When a new conversion is initiated, the device will resume
normal operation instantly—no delay is needed to allow the
device to power up and the very first conversion will be
valid.
16-Clocks per Conversion
The control bits for conversion n+1 can be overlapped with
conversion ‘n’ to allow for a conversion every 16 clock
cycles, as shown in Figure 4. This figure also shows possible
serial communication occurring with other serial peripherals
between each byte transfer between the processor and the
converter. This is possible provided that each conversion
completes within 1.6ms of starting. Otherwise, the signal
that has been captured on the input sample-and-hold may
droop enough to affect the conversion result. In addition, the
ADS7841 is fully powered while other serial communications are taking place.
PD1 PD0 Description
0 0 Power-down between conversions. When each
conversion is finished, the converter enters a low
power mode. At the start of the next conversion,
the device instantly powers up to full power. There
is no need for additional delays to assure full
operation and the very first conversion is valid.
0 1 Reserved for Future Use
1 0 Reserved for Future Use
1 1 No power-down between conversions, device al-
ways powered.
TABLE V. Power-Down Selection.
CS
DCLK
DIN
BUSY
DOUT
1
S
CONTROL BITS
81
1098765 43210
11
81 18
S
CONTROL BITS
11 10 9
FIGURE 4. Conversion Timing, 16-Clocks per Conversion, 8-bit Bus Interface. No DCLK delay required with dedicated
serial port.
ADS7841
SBAS084B
11
Digital Timing
Figure 5 and Tables VI and VII provide detailed timing for
the digital interface of the ADS7841.
15-Clocks per Conversion
Figure 6 provides the fastest way to clock the ADS7841.
This method will not work with the serial interface of most
microcontrollers and digital signal processors as they are
generally not capable of providing 15 clock cycles per serial
transfer. However, this method could be used with Field
Programmable Gate Arrays (FPGAs) or Application Specific Integrated Circuits (ASICs). Note that this effectively
increases the maximum conversion rate of the converter
beyond the values given in the specification tables, which
assume 16 clock cycles per conversion.
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
t
t
t
t
ACQ
t
DS
t
DH
t
DO
t
DV
t
TR
CSS
CSH
t
CH
t
CL
t
BD
BDV
BTR
Acquisition Time 1.5 µs
DIN Valid Prior to DCLK Rising 100 ns
DIN Hold After DCLK HIGH 10 ns
DCLK Falling to DOUT Valid 200 ns
CS Falling to DOUT Enabled 200 ns
CS Rising to DOUT Disabled 200 ns
CS Falling to First DCLK Rising 100 ns
CS Rising to DCLK Ignored 0 ns
DCLK HIGH 200 ns
DCLK LOW 200 ns
DCLK Falling to BUSY Rising 200 ns
CS Falling to BUSY Enabled 200 ns
CS Rising to BUSY Disabled 200 ns
TABLE VI. Timing Specifications (+VCC = +2.7V to 3.6V,
TA = –40°C to +85°C, C
CS
t
CSS
DCLK
DIN
t
CH
t
DS
LOAD
= 50pF).
t
DH
t
CL
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
t
t
t
t
t
t
t
ACQ
t
DS
DH
DO
t
DV
t
TR
CSS
CSH
CH
t
CL
t
BD
BDV
BTR
Acquisition Time 900 ns
DIN Valid Prior to DCLK Rising 50 ns
DIN Hold After DCLK HIGH 10 ns
DCLK Falling to DOUT Valid 100 ns
CS Falling to DOUT Enabled 70 ns
CS Rising to DOUT Disabled 70 ns
CS Falling to First DCLK Rising 50 ns
CS Rising to DCLK Ignored 0 ns
DCLK HIGH 150 ns
DCLK LOW 150 ns
DCLK Falling to BUSY Rising 100 ns
CS Falling to BUSY Enabled 70 ns
CS Rising to BUSY Disabled 70 ns
TABLE VII. Timing Specifications (+VCC = +4.75V to
+5.25V, TA = –40°C to +85°C, C
t
BD
PD0
t
BD
t
D0
t
CSH
LOAD
= 50pF).
t
BDV
BUSY
t
DV
DOUT
FIGURE 5. Detailed Timing Diagram.
CS
DCLK
15 1 15 1
A2SA1A0
DIN
1
A2S
A1 A0
MODE
SGL/
DIF
PD1 PD0
BUSY
DOUT
11
109876543210 111098765432
FIGURE 6. Maximum Conversion Rate, 15-Clocks per Conversion.
11
MODE
SGL/
DIF
PD1 PD0
t
BTR
t
TR
10
A1 A0
A2S
12
ADS7841
SBAS084B
Data Format
The ADS7841 output data is in straight binary format, as
shown in Figure 7. This figure shows the ideal output code
for the given input voltage and does not include the effects
of offset, gain, or noise.
11...111
11...110
11...101
Output Code
00...010
00...001
00...000
FS = Full-Scale Voltage = V
1LSB = V
REF
1LSB
0V
Note 1: Voltage at converter input, after
multiplexer: +IN – (–IN). See Figure 2.
Input Voltage
/4096
(1)
(V)
REF
FS – 1LSB
gible. If the conversion rate is decreased by simply slowing
the frequency of the DCLK input, the two modes remain
approximately equal. However, if the DCLK frequency is
kept at the maximum rate during a conversion, but conversion are simply done less often, then the difference between
the two modes is dramatic. Figure 8 shows the difference
between reducing the DCLK frequency (“scaling” DCLK to
match the conversion rate) or maintaining DCLK at the
highest frequency and reducing the number of conversion
per second. In the later case, the converter spends an increasing percentage of its time in power-down mode (assuming
the auto power-down mode is active).
If DCLK is active and CS is LOW while the ADS7841 is in
auto power-down mode, the device will continue to dissipate
some power in the digital logic. The power can be reduced
to a minimum by keeping CS HIGH. The differences in
supply current for these two cases are shown in Figure 9.
Operating the ADS7841 in auto power-down mode will
result in the lowest power dissipation, and there is no
conversion time “penalty” on power-up. The very first
conversion will be valid. SHDN can be used to force an
immediate power-down.
FIGURE 7. Ideal Input Voltages and Output Codes.
8-Bit Conversion
The ADS7841 provides an 8-bit conversion mode that can
be used when faster throughput is needed and the digital
result is not as critical. By switching to the 8-bit mode, a
conversion is complete four clock cycles earlier. This could
be used in conjunction with serial interfaces that provide a
12-bit transfer or two conversions could be accomplished
with three 8-bit transfers. Not only does this shorten each
conversion by four bits (25% faster throughput), but each
conversion can actually occur at a faster clock rate. This is
because the internal settling time of the ADS7841 is not as
critical, settling to better than 8 bits is all that is needed. The
clock rate can be as much as 50% faster. The faster clock
rate and fewer clock cycles combine to provide a 2x increase
in conversion rate.
POWER DISSIPATION
There are three power modes for the ADS7841: full power
(PD1 - PD0 = 11B), auto power-down (PD1 - PD0 = 00B),
and shutdown (SHDN LOW). The affects of these modes
varies depending on how the ADS7841 is being operated. For
example, at full conversion rate and 16 clocks per conversion, there is very little difference between full power mode
and auto power-down. Likewise, if the device has entered
auto power-down, a shutdown (SHDN LOW) will not lower
power dissipation.
When operating at full-speed and 16-clocks per conversion
(see Figure 4), the ADS7841 spends most of its time acquiring or converting. There is little time for auto power-down,
assuming that this mode is active. Thus, the difference
between full power mode and auto power-down is negli-
1000
= 16 • f
f
CLK
100
10
Supply Current (µA)
1
SAMPLE
f
= 2MHz
CLK
TA = 25°C
+V
= +2.7V
CC
V
= +2.5V
REF
PD1 = PD0 = 0
10k 100k1k 1M
f
(Hz)
SAMPLE
FIGURE 8. Supply Current vs Directly Scaling the Fre-
quency of DCLK with Sample Rate or Keeping
DCLK at the Maximum Possible Frequency.
14
= 25°C
T
A
+V
CC
V
REF
f
= 16 • f
CLK
PD1 = PD0 = 0
8
6
4
2
0
= +2.7V
= +2.5V
SAMPLE
CS LOW
(GND)
CS HIGH (+V
10k 100k1k 1M
f
(Hz)
SAMPLE
)
CC
12
10
Supply Current (µA)
0.09
0.00
FIGURE 9. Supply Current vs State of CS.
ADS7841
SBAS084B
13
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS7841 circuitry. This is particularly true if the reference voltage is low and/or the conversion rate is high.
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the
output of the analog comparator. Thus, during any single
conversion for an n-bit SAR converter, there are n “windows” in which large external transient voltages can easily
affect the conversion result. Such glitches might originate
from switching power supplies, nearby digital logic, and
high power devices. The degree of error in the digital output
depends on the reference voltage, layout, and the exact
timing of the external event. The error can change if the
external event changes in time with respect to the DCLK
input.
With this in mind, power to the ADS7841 should be clean
and well bypassed. A 0.1µF ceramic bypass capacitor should
be placed as close to the device as possible. In addition, a
1µF to 10µF capacitor and a 5Ω or 10Ω series resistor may
be used to low-pass filter a noisy supply.
The reference should be similarly bypassed with a 0.1µF
capacitor. Again, a series resistor and large capacitor can be
used to low-pass filter the reference voltage. If the reference
voltage originates from an op amp, make sure that it can
drive the bypass capacitor without oscillation (the series
resistor can help in this case). The ADS7841 draws very
little current from the reference on average, but it does place
larger demands on the reference circuitry over short periods
of time (on each rising edge of DCLK during a conversion).
The ADS7841 architecture offers no inherent rejection of
noise or voltage variation in regards to the reference input.
This is of particular concern when the reference input is tied
to the power supply. Any noise and ripple from the supply
will appear directly in the digital results. While high frequency noise can be filtered out as discussed in the previous
paragraph, voltage variation due to line frequency (50Hz or
60Hz) can be difficult to remove.
The GND pin should be connected to a clean ground point.
In many cases, this will be the “analog” ground. Avoid
connections which are too near the grounding point of a
microcontroller or digital signal processor. If needed, run a
ground trace directly from the converter to the power supply
entry point. The ideal layout will include an analog ground
plane dedicated to the converter and associated analog
circuitry.
14
ADS7841
SBAS084B
PACKAGE OPTION ADDENDUM
www.ti.com
23-Apr-2005
PACKAGING INFORMATION
Orderable Device Status
ADS7841E ACTIVE SSOP/
ADS7841E/2K5 ACTIVE SSOP/
ADS7841E/2K5G4 ACTIVE SSOP/
ADS7841EB ACTIVE SSOP/
ADS7841EB/2K5 ACTIVE SSOP/
ADS7841EG4 ACTIVE SSOP/
ADS7841ES ACTIVE SSOP/
ADS7841ES/2K5 ACTIVE SSOP/
(1)
Package
Type
QSOP
QSOP
QSOP
QSOP
QSOP
QSOP
QSOP
QSOP
Package
Drawing
Pins Package
Qty
Eco Plan
DBQ 16 100 Green (RoHS &
no Sb/Br)
DBQ 16 2500 Green (RoHS &
no Sb/Br)
DBQ 16 2500 Green (RoHS &
no Sb/Br)
DBQ 16 100 Green (RoHS &
no Sb/Br)
DBQ 16 2500 Green (RoHS &
no Sb/Br)
DBQ 16 100 Green (RoHS &
no Sb/Br)
DBQ 16 100 Green (RoHS &
no Sb/Br)
DBQ 16 2500 Green (RoHS &
no Sb/Br)
ADS7841P ACTIVE PDIP N 16 25 TBD Call TI Level-3-220C-168 HR
ADS7841PB ACTIVE PDIP N 16 25 TBD Call TI Level-3-220C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and alifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples mayor may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Lead/Ball Finish MSL Peak Temp
CU SNPB Level-2-260C-1 YEAR
CU SNPB Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU SNPB Level-2-260C-1 YEAR
CU SNPB Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU SNPB Level-2-260C-1 YEAR
CU SNPB Level-2-260C-1 YEAR
(3)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specifiedlead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneousmaterial)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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