The ADS7818 is a 12-bit sampling analog-to-digital
converter (A/D) complete with sample/hold, internal
2.5V reference, and synchronous serial interface. Typical power dissipation is 11mW at a 500kHz throughput rate. The device can be placed into a power down
mode which reduces dissipation to just 2.5mW. The
input range is zero to two times the reference voltage,
and the internal reference can be overdriven by an
external voltage.
Low power, small size, and high-speed make the
ADS7818 ideal for battery operated systems such as
wireless communication devices, portable multi-channel data loggers, and spectrum analyzers. The serial
interface also provides low-cost isolation for remote
data acquisition. The ADS7818 is available in a plastic mini-DIP-8 or an MSOP-8 package and is guaranteed over the –40°C to +85°C temperature range.
CLK
SAR
CONV
SBAS078
+In
–In
S/H Amp
V
REF
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
1998 Burr-Brown CorporationPDS-1408BPrinted in U.S.A. May, 2000
CDAC
Buffer
Comparator
Internal
+2.5V Ref
10kΩ ±30%
1
Serial
Interface
DATA
ADS7818
®
SPECIFICATIONS
At TA = –40°C to +85°C, +VCC = +5V, f
PARAMETERCONDITIONSMINTYPMAXMINTYPMAXUNITS
ANALOG INPUT
Full-Scale Input Span
(1)
Absolute Input Range+In–0.2V
Capacitance15✻pF
Leakage Current1✻µA
SYSTEM PERFORMANCE
Resolution12✻Bits
No Missing Codes12✻Bits
Integral Linearity Error±1±2±0.5±1LSB
Differential Linearity Error±0.8±0.5±1LSB
Offset Error±2±5±1✻LSB
Gain Error
(3)
Common-Mode RejectionDC, 0.2Vp-p70✻dB
Noise150✻µVrms
Power Supply RejectionWorst Case ∆, +V
NOTES: (1) Ideal input span, does not include gain or offset error. (2) LSB means Least Significant Bit, with V
relative to an ideal, full-scale input (+In – (–In)) of 4.999V. Thus, gain error includes the error of the internal voltage reference. (4) Calculated on the first nine
harmonics of the input frequency. (5) If the internal reference is required to source current to an external load, the reference voltage will change due to the internal
10kΩ resistor. (6) Can vary ±30%.
SAMPLE
= 500kHz, f
CLK
= 16 • f
, internal reference, unless otherwise specified.
SAMPLE
ADS7818P, EADS7818PB, EB
+In – (–In)05✻✻V
+0.2✻✻V
–In–0.2+0.2✻✻V
CC
25°C±12±30±7±15LSB
–40°C to +85°C±50±35LSB
1MHz, 0.2Vp-p50✻dB
= 5V ±5%1.2✻LSB
CC
= 5Vp-p at 100kHz72✻dB
IN
VIN = 5Vp-p at 100kHz–78–72–82–75dB
= 5Vp-p at 100kHz68707072dB
IN
= 5Vp-p at 100kHz72787582dB
IN
= 02.4752.502.5252.48✻2.52V
OUT
Static Load50✻µA
= 020✻ppm/°C
OUT
≤ 5.25V0.6✻mV
CC
to Internal Reference Voltage10✻✻✻ kΩ
|IIH| ≤ +5µA3.0V
|IIL| ≤ +5µA–0.30.8✻✻V
+0.3✻✻V
CC
IOH = –500µA3.5✻✻V
IOL = 500µA0.4✻✻V
Specified Performance4.755.25✻✻V
= 500kHz2.2✻mA
SAMPLE
Power Down0.5✻mA
= 500kHz1120✻✻ mW
SAMPLE
Power Down2.5✻mW
equal to +2.5V, one LSB is 1.22mV. (3) Measured
REF
(2)
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
®
ADS7818
2
ABSOLUTE MAXIMUM RATINGS
+VCC to GND............................................................................ –0.3V to 6V
Analog Inputs to GND .............................................. –0.3V to (V
Digital Inputs to GND ............................................... –0.3V to (V
Power Dissipation .......................................................................... 325mW
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ......................................... –40°C to +85°C
Storage Temperature Range .......................................... –65°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability.
(1)
+ 0.3V)
CC
+ 0.3V)
CC
PIN CONFIGURATION
Top View
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. BurrBrown Corporation recommends that all integrated circuits
be handled and stored using appropriate ESD protection
methods.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.
V
REF
+In
–In
GND
1
2
ADS7818
3
4
Plastic Mini-DIP-8
+V
8
CC
CLK
7
DATA
6
CONV
5
V
REF
+In
–In
GND
1
2
ADS7818
3
4
MSOP-8
+V
8
CC
CLK
7
DATA
6
CONV
5
PIN ASSIGNMENTS
PINNAMEDESCRIPTION
1V
2+InNon-Inverting Input.
3–InInverting Input. Connect to ground or to remote ground sense point.
4GNDGround.
5CONVConvert Input. Controls the sample/hold mode, start of conversion, start of serial data transfer, type of serial transfer, and power
6DATASerial Data Output. The 12-bit conversion result is serially transmitted most significant bit first with each bit valid on the rising edge
7CLKClock Input. Synchronizes the serial data transfer and determines conversion speed.
8+V
REF
Reference Output. Decouple to ground with a 0.1µF ceramic capacitor and a 2.2µF tantalum capacitor.
down mode. See the Digital Interface section for more information.
of CLK. By properly controlling the CONV input, it is possibly to have the data transmitted least significant bit first. See the Digital
Interface section for more information.
Power Supply. Decouple to ground with a 0.1µF ceramic capacitor and a 10µF tantalum capacitor.
MSOP-8337–40°C to +85°CA18ADS7818E/250 Tape and Reel
"""" " ""ADS7818E/2K5 Tape and Reel
ADS7818EB±1±1MSOP-8337–40°C to +85°CA18ADS7818EB/250 Tape and Reel
"""" " ""ADS7818EB/2K5 Tape and Reel
ADS7818P±2N/S
ADS7818PB±1±1
NOTE: (1) For detail drawing and dimension table, please see end of data sheet or Package Drawing File on Web. (2) Performance Grade information is marked
on the reel. (3) Models with a slash(/) are available only in Tape and reel in quantities indicated (e.g. /250 indicates 250 units per reel, /2K5 indicates 2500 devices
per reel). Ordering 2500 pieces of ”ADS7818E/2K5“ will get a single 2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to the
www.burr-brown.com web site under Applications and Tape and Reel Orientation and Dimensions. (4) N/S = Not Specified, typical only. However, 12-Bits no missing
codes is guaranteed over temperature.
(4)
Plastic DIP-8006–40°C to +85°CADS7818PADS7818PRails
"" "ADS7818PBADS7818PBRails
(1)
RANGEMARKING
(2)
NUMBER
(3)
MEDIA
®
3
ADS7818
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VCC = +5V, f
2
= 500kHz, f
SAMPLE
CHANGE IN FULL-SCALE ERROR
vs TEMPERATURE
CLK
= 16 • f
SAMPLE
, and internal +2.5V reference, unless otherwise specified.
2.0
CHANGE IN OFFSET vs TEMPERATURE
0
–2
–4
–6
Delta from 25°C (LSB)
–8
–10
Temperature (°C)
POWER-DOWN SUPPLY CURRENT
470
460
450
440
430
420
410
400
Power-down Supply Current (µA)
390
vs TEMPERATURE
Temperature (°C)
20–40100–20040
20–40100–20040
6080
6080
1.6
1.2
0.8
0.4
Delta from 25°C (LSB)
0.0
–0.4
2.3
2.2
2.1
2.0
1.9
1.8
Supply Current (mA)
1.7
1.6
20–40100–20040
Temperature (°C)
SUPPLY CURRENT vs TEMPERATURE
f
= 500kHz
SAMPLE
f
= 125kHz
SAMPLE
20–40100–20040
Temperature (°C)
6080
6080
2.4
2.3
2.2
2.1
2.0
1.9
Supply Current (mA)
1.8
1.7
SUPPLY CURRENT vs SAMPLE RATE
®
ADS7818
400100600200300500
Sample Rate (kHz)
4
0.4
0.3
0.2
0.1
= 500kHz (LSB)
0.0
SAMPLE
–0.1
–0.2
Delta from f
–0.3
CHANGE IN INTEGRAL LINEARITY and
DIFFERENTIAL LINEARITY vs SAMPLE RATE
Change in Integral
Linearity (LSB)
Change in Differential
Linearity (LSB)
400100600200300500
Sample Rate (kHz)
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25°C, VCC = +5V, f
SAMPLE
= 500kHz, f
CLK
= 16 • f
, and internal +2.5V reference, unless otherwise specified.
SAMPLE
0.2
0.0
–0.2
–0.4
= 2.5V (mV)
REF
–0.6
–0.8
Delta from V
–1.0
–1.2
0.70
0.65
0.60
CHANGE IN FULL-SCALE ERROR
vs EXTERNAL REFERENCE VOLTAGE
2.32.02.52.12.22.4
External Reference Voltage (V)
PEAK-TO-PEAK NOISE
vs EXTERNAL REFERENCE VOLTAGE
0.5
0.4
0.3
0.2
0.1
= 2.5V (mV)
REF
0.0
–0.1
–0.2
Delta from V
–0.3
–0.4
30
25
20
CHANGE IN OFFSET
vs EXTERNAL REFERENCE VOLTAGE
2.51.93.12.12.32.72.9
External Reference Voltage (V)
POWER SUPPLY REJECTION
vs POWER SUPPLY RIPPLE FREQUENCY
0.55
0.50
Peak-to-Peak Noise (LSB)
0.45
0.40
0
–20
–40
–60
–80
Amplitude (dB)
–100
–120
025062.5187.5125
(4096 Point FFT; f
2.32.02.52.12.22.4
External Reference Voltage (LSB)
FREQUENCY SPECTRUM
= 10.9kHz, –0.2dB)
IN
Frequency (kHz)
15
10
5
Power Supply Rejection (mV/V)
0
1101001k10k100k1M
Power Supply Ripple Frequency (Hz)
FREQUENCY SPECTRUM
0
–20
–40
–60
–80
Amplitude (dB)
–100
–120
025062.5187.5125
(4096 Point FFT; f
= 102kHz, –0.2dB)
IN
Frequency (kHz)
®
5
ADS7818
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25°C, VCC = +5V, f
(4096 Point FFT; f
0
= 500kHz, f
SAMPLE
FREQUENCY SPECTRUM
= 16 • f
CLK
= 247kHz, –0.2dB)
IN
, and internal +2.5V reference, unless otherwise specified.
SAMPLE
76
SIGNAL-TO-NOISE RATIO and
SIGNAL-TO-(NOISE+DISTORTION)
vs INPUT FREQUENCY
–20
–40
–60
–80
Amplitude (dB)
–100
–120
025062.5187.5125
SPURIOUS FREE DYNAMIC RANGE AND
TOTAL HARMONIC DISTORTION
90
85
❉
THD
80
75
SFDR (dB)
70
❉
First nine harmonics
of the input frequency
65
Frequency (kHz)
vs INPUT FREQUENCY
SFDR
10k100k1k1M
Input Frequency (Hz)
74
72
70
68
SNR and SINAD (dB)
66
64
CHANGE IN SIGNAL-TO-NOISE RATIO
and SIGNAL-TO-(NOISE+DISTORTION)
–
90
–
85
–
80
–
75
–
70
–
65
THD (dB)
Delta from +25°C (dB)
0.3
0.2
0.1
0.0
–0.1
–0.2
fIN = 100kHz, –0.2dB
–0.3
SNR
SINAD
–20–40100
SNR
SINAD
10k100k1k1M
Input Frequency (Hz)
vs TEMPERATURE
020406080
Temperature (°C)
1.0
0.5
0.0
–0.5
–1.0
–1.5
SFDR Delta from +25°C (dB)
–2.0
CHANGE IN SPURIOUS FREE DYNAMIC RANGE
AND TOTAL HARMONIC DISTORTION
fIN = 100kHz, –0.2dB
❉
First nine harmonics
of the input frequency
–20–40100
®
vs TEMPERATURE
THD
SFDR
020406080
Temperature (°C)
ADS7818
–1.0
–0.5
❉
0.0
0.5
1.0
1.5
2.0
THD Delta from +25°C (dB)
6
THEORY OF OPERATION
The ADS7818 is a high speed successive approximation
register (SAR) analog-to-digital converter (A/D) with an
internal 2.5V bandgap reference. The architecture is based
on capacitive redistribution which inherently includes a
sample/hold function. The converter is fabricated on a 0.6µ
CMOS process. See Figure 1 for the basic operating circuit
for the ADS7818.
The ADS7818 requires an external clock to run the conversion process. This clock can vary between 200kHz (12.5Hz
throughput) and 8MHz (500kHz throughput). The duty cycle
of the clock is unimportant as long as the minimum HIGH
and LOW times are at least 50ns and the clock period is at
least 125ns. The minimum clock frequency is set by the
leakage on the capacitors internal to the ADS7818.
The analog input is provided to two input pins: +IN and –IN.
When a conversion is initiated, the differential input on these
pins is sampled on the internal capacitor array. While a
conversion is in progress, both inputs are disconnected from
any internal function.
The range of the analog input is set by the voltage on the
V
pin. With the internal 2.5V reference, the input range
REF
is 0 to 5V. An external reference voltage can be placed on
V
, overdriving the internal voltage. The range for the
REF
external voltage is 2.0V to 2.55V, giving an input voltage
range of 4.0V to 5.1V.
The digital result of the conversion is provided in a serial
manner, synchronous to the CLK input. The result is provided most significant bit first and represents the result of
the conversion currently in progress—there is no pipeline
delay. By properly controlling the CONV and CLK inputs,
it is possible to obtain the digital result least significant bit
first.
ANALOG INPUT
The +IN and –IN input pins allow for a differential input
signal to be captured on the internal hold capacitor when the
converter enters the hold mode. The voltage range on the
–IN input is limited to –0.2V to 0.2V. Because of this, the
differential input can be used to reject only small signals that
are common to both inputs. Thus, the –IN input is best used
to sense a remote ground point near the source of the +IN
signal. If the source driving the +IN signal is nearby, the
–IN should be connected directly to ground.
The input current into the analog input depends on input
voltage and sample rate. Essentially, the current into the
device must charge the internal hold capacitor during the
sample period. After this capacitance has been fully charged,
there is no further input current. The source of the analog
input voltage must be able to charge the input capacitance to
a 12-bit settling level within the sample period—which can
be as little as 350ns in some operating modes. While the
converter is in the hold mode or after the sampling capacitor
has been fully charged, the input impedance of the analog
input is greater than 1GΩ.
Care must be taken regarding the input voltage on the +In
and –IN pins. To maintain the linearity of the converter, the
+In input should remain within the range of GND – 200mV
to +VCC + 200mV. The –IN input should not drop below
GND – 200mV or exceed GND + 200mV. Outside of these
ranges, the converter’s linearity may not meet specifications.
REFERENCE
The reference voltage on the V
scale range of the analog input. The ADS7818 can operate
with a reference in the range of 2.0V to 2.55V, for a fullscale range of 4.0V to 5.1V.
The voltage at the V
pin is internally buffered and this
REF
buffer drives the capacitor DAC portion of the converter.
This is important because the buffer greatly reduces the
dynamic load placed on the reference source. However, the
voltage at V
will still contain some noise and glitches
REF
from the SAR conversion process. These can be reduced by
carefully bypassing the V
REF
sections that follow.
INTERNAL REFERENCE
The ADS7818 contains an on-board 2.5V reference, resulting in a 0V to 5V input range on the analog input. The
specification table gives the various specifications for the
pin directly sets the full-
REF
pin to ground as outlined in the
+
2.2µF
0.1µF10µF
0 to 5V
Analog Input
FIGURE 1. Basic Operation of the ADS7818.
+5V
ADS7818
1
V
REF
2
+In
3
–In
4
GND
+V
CLK
DATA
CONV
8
CC
7
6
5
0.1µF
Serial Clock
Serial Data
Convert Start
7
+
from
Microcontroller
or DSP
®
ADS7818
internal reference. This reference can be used to supply a
small amount of source current to an external load, but the
load should be static. Due to the internal 10kΩ resistor, a
dynamic load will cause variations in the reference voltage,
and will dramatically affect the conversion result. Note that
even a static load will reduce the internal reference voltage
seen at the buffer input. The amount of reduction depends on
the load and the actual value of the internal “10kΩ” resistor.
The value of this resistor can vary by ±30%.
The V
pin should be bypassed with a 0.1µF capacitor
REF
placed as close as possible to the ADS7818 package. In
addition, a 2.2 µF tantalum capacitor should be used in
parallel with the ceramic capacitor. Placement of this capacitor is not as critical.
EXTERNAL REFERENCE
The internal reference is connected to the V
pin and to the
REF
internal buffer via a 10kΩ series resistor. Thus, the reference
voltage can easily be overdriven by an external reference
voltage. The voltage range for the external voltage is 2.0V
to 2.55V, corresponding to an analog input range of 4.0V to
5.1V.
While the external reference will not source significant
current into the V
pin, it does have to drive the series
REF
10kΩ resistor that is terminated into the 2.5V internal
reference (the exact value of the resistor will vary up to
±30% from part to part). In addition, the V
pin should
REF
still be bypassed to ground with at least a 0.1 µF ceramic
capacitor (placed as close to the ADS7818 as possible). The
reference will have to be stable with this capacitive load.
Depending on the particular reference and A/D conversion
speed, additional bypass capacitance may be required, such
as the 2.2µF tantalum capacitor shown in Figure 1.
Reasons for choosing an external reference over the internal
reference vary, but there are two main reasons. One is to
achieve a given input range. For example, a 2.048V reference provides for a 0V to 4.095V input range—or 1mV per
LSB. The other is to provide greater stability over temperature. The internal reference is typically 20ppm/°C which
translates into a full-scale drift of roughly 1 output code for
every 12°C (this does not take into account other sources of
full-scale drift). If greater stability over temperature is needed,
then an external reference with lower temperature drift will
be required.
DIGITAL INTERFACE
Figure 2 shows the serial data timing and Figure 3 shows the
basic conversion timing for the ADS7818. The specific
timing numbers are listed in Table I. There are several
important items in Figure 3 which give the converter additional capabilities over typical 8-pin converters. First, the
transition from sample mode to hold mode is synchronous to
the falling edge of CONV and is not dependent on CLK.
Second, the CLK input is not required to be continuous
during the sample mode. After the conversion is complete,
the CLK may be kept LOW or HIGH.
t
CKP
CLK
DATA
t
CKH
t
CKL
t
CKDS
t
CKDH
FIGURE 2. Serial Data and Clock Timing.
SYMBOLDESCRIPTIONMINTYPMAXUNITS
t
ACQ
t
CONV
t
CKP
t
CKL
t
CKH
t
CKDH
t
CKDS
t
CVL
t
CVH
t
CKCH
t
CKCS
t
CKDE
t
CKDD
t
CKSP
t
CKPD
t
CVHD
t
CVSP
t
CVPU
t
CVDD
t
CVPD
t
DRP
Note: (1) This timing is not required under some situations. See text for more information.
Acquisition Time350ns
Conversion Time1.5µs
Clock Period1255000ns
Clock LOW50ns
Clock HIGH50ns
Clock Falling to Current Data515ns
Bit No Longer Valid
Clock Falling to Next Data Valid3050ns
CONV LOW40ns
CONV HIGH40ns
CONV Hold after Clock Falls
CONV Setup to Clock Falling
Clock Falling to DATA Enabled2050ns
Clock Falling to DATA70100ns
High Impedance
Clock Falling to Sample Mode5ns
Clock Falling to Power-down Mode50ns
CONV Falling to Hold Mode5ns
(Aperture Delay)
CONV Rising to Sample Mode5n s
CONV Rising to Full Power-up50ns
CONV Changing State to DATA70100ns
High Impedance
CONV Changing State to50ns
Power-down Mode
CONV Falling to Start of CLK5µs
(for hold droop < 0.1 LSB)
(1)
10ns
(1)
10ns
TABLE I. Timing Specifications (TA = –40°C to +85°C,
C
= 30pF).
LOAD
The asynchronous nature of CONV to CLK raises some
interesting possibilities, but also some design considerations. Figure 3 shows that CONV has timing restraints in
relation to CLK (t
CKCH
and t
). However, if these times
CKCS
are violated (which could happen if CONV is completely
asynchronous to CLK), the converter will perform a conversion correctly, but the exact timing of the conversion is
indeterminate. Since the setup and hold time between CONV
and CLK has been violated in this example, the start of
conversion could vary by one clock cycle. (Note that the
start of conversion can be detected by using a pull-up
resistor on DATA. When DATA drops out of high-impedance and goes LOW, the conversion has started and that
clock cycle is this first of the conversion.)
In addition if CONV is completely asynchronous to CLK
and CLK is continuous, then there is possibility that CLK
will transition just prior to CONV going LOW. If this occurs
®
ADS7818
8
faster than the 10ns indicated by t
, then there is a
CKCH
chance that some digital feedthrough may be coupled onto
the hold capacitor. This could cause a small offset error for
that particular conversion.
Thus, there are two basic ways to operate the ADS7818.
CONV can be synchronous to CLK and CLK can be continuous. This would be the typical situation when interfacing
the converter to a digital signal processor. The second
method involves having CONV asynchronous to CLK and
gating the operation of CLK (a non-continuous clock). This
method would be more typical of an SPI-like interface on a
microcontroller. This method would also allow CONV to be
generated by a trigger circuit and to initiate (after some
delay) the start of CLK. These two methods are covered
under DSP Interfacing and SPI Interfacing.
POWER-DOWN TIMING
The conversion timing shown in Figure 3 does not result in
the ADS7818 going into the power-down mode. If the
conversion rate of the device is high (approaching 500kHz),
then there is very little power that can be saved by using the
power-down mode. However, since the power-down mode
incurs no conversion penalty (the very first conversion is
valid), at lower sample rates, significant power can be saved
by allowing the device to go into power-down mode between conversions.
Figure 4 shows the typical method for placing the A/D into
the power-down mode. If CONV is kept LOW during the
conversion and is LOW at the start of the 13 clock cycle,
then the device enters the power-down mode. It remains in
this mode until the rising edge of CONV. Note that CONV
must be HIGH for at least t
in order to sample the signal
ACQ
properly as well as to power-up the internal nodes.
There are two different methods for clocking the ADS7818.
The first involves scaling the CLK input in relation to the
conversion rate. For example, an 8MHz input clock and the
timing shown in Figure 3 results in a 500kHz conversion
rate. Likewise, a 1.6MHz clock would result in a 100kHz
conversion rate. The second method involves keeping the
clock input as close to the maximum clock rate as possible
and starting conversions as needed. This timing is similar to
that shown in Figure 4. As an example, a 50kHz conversion
rate would require 160 clock periods per conversion instead
of the 16 clock periods used at 500kHz.
The main distinction between the two is the amount of time
that the ADS7818 remains in power down. In the first mode,
the converter only remains in power down for a small
number of clock periods (depending on how many clock
periods there are per each conversion). As the conversion
rate scales, the converter always spends the same percentage
of time in power down. Since less power is drawn by the
digital logic, there is a small decrease in power consumption, but it is very slight. This effect can be seen in the
typical performance curve “Supply Current vs Sample Rate.”
CONV
CLK
DATA
SAMPLE/HOLD
MODE
INTERNAL
CONVERSION
STATE
t
CVL
t
t
CKCH
(1)
t
CVHD
(2)
NOTES: (1) Clock periods 14 and 15 are shown for clarity, but are not required for proper operation of the ADS7818, provided that the
minimum t
mode occurs on the falling edge of CONV. This transition is not dependent on CLK. (3) The device remains fully powered when
operated as shown. If the sample time is longer than 3 clock periods, power consumption can be reduced by allowing the device to
enter a power down mode. See the power down timing for more information.
time is met. The CLK input may remain HIGH or LOW during this period. (2) The transition from sample mode to hold
ACQ
CKCS
12341112131415141516161
t
CKDE
D11
(MSB)
D10D9D2D1
HOLD
t
CONV
CONVERSION IN PROGRESS IDLE IDLE
t
D0
(LSB)
CVCK
t
CKSP
t
CKDD
t
ACQ
SAMPLESAMPLE
(
3)
HOLD
FIGURE 3. Basic Conversion Timing.
®
9
ADS7818
CONV
CLK
DATA
SAMPLE/HOLD
MODE
INTERNAL
CONVERSION
STATE
POWER MODEFULL POWERFULL POWERLOW POWER
NOTES: (1) The low power mode (“power-down”) is entered when CONV remains LOW during the conversion and is still LOW at the
start of the 13th clock cycle. (2) The low power mode is exited when CONV goes HIGH. (3) When in power-down, the transition from
hold mode to sample mode is initiated by CONV going HIGH.
1231213
D11
(MSB)
CONVERSION IN PROGRESS IDLE IDLE
D10D1
HOLDSAMPLESAMPLEHOLD
t
CKPD
D0
(LSB)
(1)(2)
FIGURE 4. Power-down Timing.
t
CVH
CONV
t
CVSP
t
ACQ
(3)
t
CVPU
t
CKCH
CLK
DATA
SAMPLE/HOLD
MODE
INTERNAL
CONVERSION
STATE
POWER MODEFULL POWERLOW POWER
NOTES: (1) The serial data can be transmitted LSB first by pulling CONV LOW during the 13th clock cycle. (2) After the MSB has been
transmitted, the DATA output pin will remain LOW until CONV goes HIGH. (3) When CONV is taken LOW to initiate the LSB first transfer,
the converter enters the power-down mode.
1 2 31213142324
t
CKCS
CONVERSION IN PROGRESSIDLE
D11
(MSB)
D10D1
HOLDSAMPLE
t
CVPD
D0
(LSB)
(1)(2)
(3)
D1D10
IDLE
FIGURE 5. Serial Data “LSB-First” Timing.
In contrast, the second method (clocking at a fixed rate)
means that each conversion takes X clock cycles. As the
time between conversions get longer, the converter remains
in power-down an increasing percentage of time. This re-
duces total power consumption by a considerable amount.
For example, a 50kHz conversion rate results in roughly
1/10 of the power (minus the reference) that is used at a
500kHz conversion rate.
D11
(MSB)
LOW...
t
CVDD
®
ADS7818
10
Table II offers a look at the two different modes of operation
and the difference in power consumption.
POWER WITHPOWER WITH
f
SAMPLE
500kHz11mW11mW
250kHz10mW7mW
100kHz9mW4mW
CLK = 16 • f
SAMPLE
CLK = 8MHz
TABLE II. Power Consumption versus CLK Input.
LSB FIRST DATA TIMING
Figure 5 shows a method to transmit the digital result in a
least-significant bit (LSB) format. This mode is entered
when CONV is pulled HIGH during the conversion (before
the end of the 12th clock) and then pulled LOW during the
13th clock (when D0, the LSB, is being transmitted). The
next 11 clocks then repeat the serial data, but in an LSB first
format. The converter enters the power-down mode during
the 13th clock and resumes normal operation when CONV
goes HIGH.
SHORT-CYCLE TIMING
The conversion currently in progress can be “short-cycled”
with the technique shown in Figure 6. This term means that
the conversion will terminate immediately, before all 12-bits
have been decided. This can be a very useful feature when
a resolution of 12-bits is not needed. An example would be
when the converter is being used to monitor an input voltage
until some condition is met. At that time, the full resolution
of the converter would then be used. Short-cycling the
conversion can result in a faster conversion rate or lower
power dissipation.
There are several very important items shown in Figure 6.
The conversion currently in progress is terminated when
CONV is taken HIGH during the conversion and then taken
LOW prior to t
before the start of the 13th clock cycle.
CKCH
Note that if CONV goes LOW during the 13th clock cycle,
then the LSB first mode will be entered (Figure 5). Also,
when CONV goes LOW, the DATA output immediately
transitions to high impedance. If the output bit that is present
during that clock period is needed, CONV must not go LOW
until the bit has been properly latched into the receiving
logic.
DATA FORMAT
The ADS7818 output data is in straight binary format as
shown in Figure 7. This figure shows the ideal output code
for the given input voltage and does not include the effects
of offset, gain, or noise.
(1)
CONV
t
CVH
CLK
DATA
SAMPLE/HOLD
MODE
INTERNAL
CONVERSION
STATE
POWER MODEFULL POWERLOW POWER
NOTE: (1) The conversion currently in progress can be stopped by pulling CONV LOW during the conversion. This must occur at
least t
mode when CONV is pulled LOW.
prior to the start of the 13th clock cycle. The DATA output pin will tri-state and the device will enter the power-down
CKCS
1235467
t
CVDD
D11
(MSB)
D10D8D9D7
CONVERSION IN PROGRESSIDLEIDLE
t
CVPD
D6
HOLDSAMPLE
t
CVL
FIGURE 6. Short-cycle Timing.
11
®
ADS7818
11...111
11...110
11...101
Output Code
00...010
00...001
00...000
FS = Full-Scale Voltage = 2 • V
1 LSB = FS/4096
1 LSB
REF
microcontrollers form various manufacturers. CONV would
be tied to a general purpose I/O pin (SPI) or to a PCX pin
(QSPI), CLK would be tied to the serial clock, and DATA
would be tied to the serial input data pin such as MISO
(master in slave out).
Note the time t
shown in Figure 9. This represents the
DRP
maximum amount of time between CONV going LOW and
the start of the conversion clock. Since CONV going LOW
places the sample and hold in the hold mode and because the
hold capacitor looses charge over time, there is a requirement that time t
period (t
CKP
).
be met as well as the maximum clock
DRP
(1)
0V
Input Voltage
NOTES: (1) For external reference, value is 2 • V
at converter input: +IN–(–IN).
(2)
4.999V
(V)
– 1 LSB. (2) Voltage
REF
FIGURE 7. Ideal Input Voltages and Output Codes.
DSP INTERFACING
Figure 8 shows a timing diagram that might be used with a
typical digital signal processor such as a TI DSP. For the
buffered serial port (BSP) on the TMS320C54X family,
CONV would tied to BFSX, CLK would be tied to BCLKX,
and DATA would be tied to BDR.
SPI/QSPI INTERFACING
Figure 9 shows the timing diagram for a typical serial
peripheral interface (SPI) or queued serial peripheral interface (QSPI). Such interfaces are found on a number of
CONV
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS7818 circuitry. This is particularly true if the CLK input is approaching the maximum
input rate.
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the
output of the analog comparator. Thus, during any single
conversion for an n-bit SAR converter, there are n “windows” in which large external transient voltages can easily
affect the conversion result. Such glitches might originate
from switching power supplies, nearby digital logic, and
high power devices. The degree of error in the digital output
depends on the reference voltage, layout, and the exact
timing of the external event. The error can change if the
external event changes in time with respect to the CLK
input.
CLK
DATA
121516312131415161234
D11
(MSB)
D10D1
FIGURE 8. Typical DSP Interface Timing.
t
DRP
CONV
CLK
DATA
231413141516123
D11
(MSB)
D10D1
FIGURE 9. Typical SPI/QSPI Interface Timing.
®
ADS7818
12
D0
(LSB)
D0
(LSB)
D11
(MSB)
t
ACQ
D10D9
D11
(MSB)
With this in mind, power to the ADS7818 should be clean
and well bypassed. A 0.1µF ceramic bypass capacitor should
be placed as close to the device as possible. In addition, a
1µF to 10µF capacitor is recommended. If needed, an even
larger capacitor and a 5Ω or 10Ω series resistor my be used
to lowpass filter a noisy supply.
The ADS7818 draws very little current from an external
reference on average as the reference voltage is internally
buffered. However, glitches from the conversion process
appear at the V
input and the reference source must be
REF
able to handle this. Whether the reference is internal or
external, the V
pin should be bypassed with a 0.1µF
REF
capacitor. An additional larger capacitor may also be used,
if desired. If the reference voltage is external and originates
from an op-amp, make sure that it can drive the bypass
capacitor or capacitors without oscillation.
The GND pin should be connected to a clean ground point.
In many cases, this will be the “analog” ground. Avoid
connections which are too near the grounding point of a
microcontroller or digital signal processor. If needed, run a
ground trace directly from the converter to the power supply
entry point. The ideal layout will include an analog ground
plane dedicated to the converter and associated analog
circuitry.
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Lead/Ball Finish MSL Peak Temp
Call TILevel-2-260C-1 YEAR
Call TILevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
(3)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty . Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
ProductsApplications
Amplifiersamplifier.ti.comAudiowww.ti.com/audio
Data Convertersdataconverter.ti.comAutomotivewww.ti.com/automotive
DSPdsp.ti.comBroadbandwww.ti.com/broadband
Interfaceinterface.ti.comDigital Controlwww.ti.com/digitalcontrol
Logiclogic.ti.comMilitarywww.ti.com/military
Power Mgmtpower.ti.comOptical Networkingwww.ti.com/opticalnetwork
Microcontrollersmicrocontroller.ti.comSecuritywww.ti.com/security
Telephonywww.ti.com/telephony
Video & Imagingwww.ti.com/video
Wirelesswww.ti.com/wireless
Mailing Address:Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
Loading...
+ hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.