TEXAS INSTRUMENTS ADS7807 Technical data

AD

S7807

A

D

S

7

8

0

7

SBAS022B – NOVEMBER 1992 – REVISED SEPTEMBER 2003

Low-Power, 16-Bit, Sampling CMOS

ANALOG-to-DIGITAL CONVERTER

ADS7807

FEATURES

● 35mW max POWER DISSIPATION

● 50µW POWER-DOWN MODE

● 25µs max ACQUISITION AND CONVERSION

● ±1.5LSB max INL

● DNL: 16 bits “No Missing Codes”

● 86dB min SINAD WITH 1kHz INPUT

●±10V, 0V TO +5V, AND 0V TO +4V INPUT RANGES

● SINGLE +5V SUPPLY OPERATION

● PARALLEL AND SERIAL DATA OUTPUT

● PIN-COMPATIBLE WITH THE 12-BIT ADS7806

● USES INTERNAL OR EXTERNAL REFERENCE

● 0.3" DIP-28 AND SO-28

R1

R2

Clock

40kΩ

IN

20kΩ

10kΩ

IN

CAP

40kΩ

Buffer

Successive Approximation Register and Control Logic

CDAC

DESCRIPTION

The ADS7807 is a low-power, 16-bit, sampling Analog-to­Digital (A/D) converter using state-of-the-art CMOS struc­tures. It contains a complete 16-bit, capacitor-based, Suc­cessive Approximation Register (SAR) A/D converter with
sample-and-hold, clock, reference, and microprocessor inter­face with parallel and serial output drivers.

The ADS7807 can acquire and convert 16-bits to within
±1.5LSB in 25µs max while consuming only 35mW max.
Laser trimmed scaling resistors provide standard industrial
input ranges of ±10V and 0V to +5V. In addition, a 0V to +4V
range allows development of complete single-supply sys­tems.

The ADS7807 is available in a 0.3" DIP-28 and SO-28, both
fully specified for operation over the industrial –40°C to
+85°C temperature range.

R/C
CS
BYTE
Power
Down

BUSY

Comparator

Parallel

and

Serial

Data

Out

Serial Data
Clock

Serial Data

Parallel Data

8

REF

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

6kΩ

Internal

+2.5V Ref

www.ti.com

Reference
Power-Down

Copyright © 1992-2003, Texas Instruments Incorporated

ABSOLUTE MAXIMUM RATINGS

Analog Inputs: R1IN........................................................................... ±12V

Ground Voltage Differences: DGND, AGND1, and AGND2 ............. ±0.3V

V

ANA

V

to V

DIG

V

........................................................................................................ 7V

DIG

Digital Inputs ............................................................. –0.3V to V

Maximum Junction Temperature ................................................... +165°C

Internal Power Dissipation ............................................................. 825mW

Lead Temperature (soldering, 10s) ............................................... +300°C

NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.

R2

.......................................................................... ±5.5V

IN

CAP .................................. V

REF .........................................Indefinite Short to AGND2,

....................................................................................................... 7V

...................................................................................... +0.3V

ANA

(1)

+ 0.3V to AGND2 – 0.3V

ANA

Momentary Short to V

DIG

ANA

+ 0.3V

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru­ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degrada­tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.

PACKAGE/ORDERING INFORMATION

MAXIMUM SPECIFIED SIGNAL-TO­INTEGRAL NO MISSING (NOISE + SPECIFIED
LINEARITY CODE LEVEL DISTORTION) PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT

PRODUCT ERROR (LSB) (LSB) RATIO (DB) PACKAGE-LEAD DESIGNATOR

ADS7807P ±31583Dip-28NT–40°C to +85°C ADS7807P ADS7807P Tubes, 13
ADS7807PB ±1.5 16 86
ADS7807U ±3 15 83 SO-28 DW –40°C to +85°C ADS7807U ADS7807U Tubes, 28

" " " " " " " " ADS7807U/1K Tape and Reel, 1000

ADS7807UB ±1.5 16 86

" " " " " " " " ADS7807UB/1K Tape and Reel, 1000

NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.

MINIMUM

(1)

RANGE MARKING NUMBER MEDIA, QUANTITY

"""ADS7807PB ADS7807PB Tubes, 13

"""ADS7807UB ADS7807UB Tubes, 28

ELECTRICAL CHARACTERISTICS

At TA = –40°C to +85°C, fS = 40kHz, V

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
RESOLUTION 16 ✻ Bits
ANALOG INPUT

Voltage Ranges ±10, 0 to +5, 0 to +4 V
Impedance (See Table II)
Capacitance 35 ✻ pF

THROUGHPUT SPEED

Conversion Time 20 ✻ µs
Complete Cycle Acquire and Convert 25 ✻ µs
Throughput Rate 40 ✻ kHz

DC ACCURACY

Integral Linearity Error ±3 ±1.5 LSB
Differential Linearity Error +3, –2 +1.5, –1LSB
No Missing Codes 15 16 Bits
Transition Noise
Gain Error ±0.2 ±0.1 %
Full-Scale Error
Full-Scale Error Drift ±7 ±5 ppm/°C
Full-Scale Error
Full-Scale Error Drift Ext. 2.5000V Ref ±0.5 ✻ ppm/°C
Bipolar Zero Error
Bipolar Zero Error Drift ±10V Range ±0.5 ✻ ppm/°C
Unipolar Zero Error
Unipolar Zero Error Drift 0V to 5V, 0V to 4V Ranges ±0.5 ✻ ppm/°C
Recovery Time to Rated Accuracy 2.2µF Capacitor to CAP 1 ✻ ms

from Power-Down

Power-Supply Sensitivity +4.75V < VS < +5.25V ±8 ✻ LSB

(V

DIG

= V

ANA

(2)

(3,4)

(3,4)

(3)

(3)

(5)

= VS)

= V

DIG

= +5V, and using internal reference and fixed resistors (see Figure 7b), unless otherwise specified.

ANA

ADS7807P, U ADS7807PB, UB

0.8 ✻ LSB

±0.5 ±0.25 %

Ext. 2.5000V Ref ±0.5 ±0.25 %

±10V Range ±10 ✻ mV

0V to 5V, 0V to 4V Ranges ±3 ✻ mV

(1)

2

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ADS7807

SBAS022B

ELECTRICAL CHARACTERISTICS (Cont.)

At TA = –40°C to +85°C, fS = 40kHz, V

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
AC ACCURACY

Spurious-Free Dynamic Range f
Total Harmonic Distortion f
Signal-to-(Noise + Distortion) f

Signal-to-Noise f
Usable Bandwidth

(7)

Full-Power Bandwidth (–3dB) 600 ✻ kHz

SAMPLING DYNAMICS

Aperture Delay 40 ✻ ns
Aperture Jitter 20 ✻ ps
Transient Response FS Step 5 ✻ µs
Over-Voltage Recovery

(8)

REFERENCE

Internal Reference Voltage No Load 2.48 2.5 2.52 ✻✻✻ V
Internal Reference Source Current 1 ✻ µA

(Must use external buffer.)

Internal Reference Drift 8 ✻ ppm/°C
External Reference Voltage Range 2.3 2.5 2.7 ✻✻ ✻ V

for Specified Linearity

External Reference Current Drain External 2.5000V Ref 100 ✻ µA

DIGITAL INPUTS

Logic Levels

V

IL

(9)

V

IH

I

IL

I

IH

DIGITAL OUTPUTS Parallel 16 bits in 2-bytes; Serial
Data Format Binary Two’s Complement or Straight Binary
Data Coding

V

OL

V

OH

Leakage Current High-Z State, ±5 ✻ µA

Output Capacitance High-Z State 15 ✻ pF

DIGITAL TIMING

Bus Access Time R
Bus Relinquish Time R

POWER SUPPLIES

Specified Performance

V

DIG

V

ANA

I

DIG

I

ANA

Power Dissipation V

TEMPERATURE RANGE

Specified Performance –40 +85 ✻✻ °C
Derated Performance –55 +125 ✻✻ °C
Storage –65 +150 ✻✻ °C
Thermal Resistance (

DIP 75 ✻ °C/W

θ

)

JA

SO 75 ✻ °C/W

✻ Same specifications as ADS7807P, U.
NOTES: (1) LSB means Least Significant Bit. One LSB for the ±10V input range is 305µV. (2) Typical rms noise at worst-case transition. (3) As measured with

fixed resistors, see Figure 7b. Adjustable to zero with external potentiometer. (4) Full-scale error is the worst case of –Full-Scale or +Full-Scale untrimmed deviation
from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. (5) This is the
time delay after the ADS7807 is brought out of Power-Down mode until all internal settling occurs and the analog input is acquired to rated accuracy. A Convert
command after this delay will yield accurate results. (6) All specifications in dB are referred to a full-scale input. (7) Usable bandwidth defined as full-scale input
frequency at which Signal-to-(Noise + Distortion) degrades to 60dB. (8) Recovers to specified performance after 2 • FS input overvoltage. (9) The minimum V
level for the DATACLK signal is 3V.

= V

DIG

= +5V, and using internal reference and fixed resistors (see Figure 7b), unless otherwise specified.

ANA

ADS7807P, U ADS7807PB, UB

= 1kHz, ±10V 90 100 96 ✻ dB

IN

= 1kHz, ±10V –100 –90 ✻ –96 dB

IN

= 1kHz, ±10V 83 88 86 ✻ dB

IN

–60dB Input 30 32 dB

= 1kHz, ±10V 83 88 86 ✻ dB

IN

130 ✻ kHz

750 ✻ ns

–0.3 +0.8 ✻✻V

+2.0 VD + 0.3V ✻✻V
VIL = 0V ±10 ✻ µA
VIH = 5V ±10 ✻ µA

I

= 1.6mA +0.4 ✻ V

SINK

I

= 500µA+4 ✻ V

SOURCE

V

= 0V to V

OUT

= 3.3kΩ, CL = 50pF 83 ✻ ns

L

= 3.3kΩ, CL = 10pF 83 ✻ ns

L

Must be ≤ V

ANA

DIG

+4.75 +5 +5.25 ✻✻✻ V
+4.75 +5 +5.25 ✻✻✻ V

0.6 ✻ mA

5.0 ✻ mA

= V

ANA

= 5V, fS = 40kHz 28 35 ✻✻mW

DIG

REFD HIGH 23 ✻ mW

PWRD and REFD HIGH 50 ✻ µW

(6)

IH

ADS7807

SBAS022B

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3

PIN DESCRIPTIONS

ANA
DIG

DIGITAL

IN

IN

Analog Input. See Figure 7.

Analog Input. See Figure 7.

unconnected when using serial output.

enables the parallel output.

falling edge will start the transmission of serial data results from the previous conversion.

have been updated.

Analog Supply. Nominally +5V. Decouple with 0.1µF ceramic and 10µF tantalum capacitors.
Digital Supply. Nominally +5V. Connect directly to pin 27. Must be ≤ V

ANA

.

PIN # NAME I/O DESCRIPTION

1R1
2 AGND1 Analog Sense Ground.
3R2
4 CAP Reference Buffer Output. 2.2µF tantalum capacitor to ground.
5 REF Reference Input/Output. 2.2µF tantalum capacitor to ground.
6 AGND2 Analog Ground
7 SB/BTC I Selects Straight Binary or Binary Two’s Complement for Output Data Format.
8 EXT/INT I External/Internal data clock select.
9 D7 O Data Bit 7 if BYTE is HIGH. Data bit 15 (MSB) if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW. Leave

10 D6 O Data Bit 6 if BYTE is HIGH. Data bit 14 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
11 D5 O Data Bit 5 if BYTE is HIGH. Data bit 13 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
12 D4 O Data Bit 4 if BYTE is HIGH. Data bit 12 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
13 D3 O Data Bit 3 if BYTE is HIGH. Data bit 11 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
14 DGND Digital Ground
15 D2 O Data Bit 2 if BYTE is HIGH. Data bit 10 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
16 D1 O Data Bit 1 if BYTE is HIGH. Data bit 9 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
17 D0 O Data Bit 0 (LSB) if BYTE is HIGH. Data bit 8 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
18 DATACLK I/O Data Clock Output when EXT/INT is LOW. Data clock input when EXT/INT is HIGH.
19 SDATA O Serial Output Synchronized to DATACLK
20 TAG I Serial Input When Using an External Data Clock
21 BYTE I Selects 8 most significant bits (LOW) or 8 least significant bits (HIGH) on parallel output pins.
22 R/C I With CS LOW and BUSY HIGH, a Falling Edge on R/C Initiates a New Conversion. With CS LOW, a rising edge on R/C

23 CS I Internally OR’d with R/C. If R/C is LOW, a falling edge on CS initiates a new conversion. If EXT/INT is LOW, this same

24 BUSY O At the start of a conversion, BUSY goes LOW and stays LOW until the conversion is completed and the digital outputs

25 PWRD I PWRD HIGH shuts down all analog circuitry except the reference. Digital circuitry remains active.
26 REFD I REFD HIGH shuts down the internal reference. External reference will be required for conversions.
27 V
28 V

PIN CONFIGURATION

Top View DIP, SO

R1

AGND1

R2
CAP
REF

AGND2

SB/BTC

EXT/INT

D7
D6
D5
D4
D3

DGND

1

IN

2
3

IN

4
5
6
7

ADS7807

8

9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

V

DIG

V

ANA

REFD
PWRD
BUSY
CS
R/C
BYTE
TAG
SDATA
DATACLK
D0
D1
D2

ANALOG CONNECT R1INCONNECT R2

INPUT VIA 200Ω VIA 100Ω

IN

RANGE TO TO IMPEDANCE

±10V V
0V to 5V AGND V
0V to 4V V

IN

IN

CAP 45.7kΩ

IN

V

IN

20.0kΩ

21.4kΩ

TABLE I. Input Range Connections. See Figure 7.

4

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ADS7807

SBAS022B

TYPICAL CHARACTERISTICS

SIGNAL-TO-(NOISE + DISTORTION)

vs INPUT FREQUENCY AND INPUT AMPLITUDE

Input Signal Frequency (kHz)

02468101214161820

100

80

90

70
60
50
40
30
20
10

SINAD (dB)

0dB

–20dB

–60dB

AC PARAMETERS vs TEMPERATURE

(f

IN

= 1kHz, 0dB)

SFDR

THD

Temperature (°C)

–75 –50 –25 0 25 50 75 100 125 150

110

105

100

95

90

85

80

–80

–85

–90

–95

–100

–105

–110

SFDR, SINAD, and SNR (dB)

THD (dB)

SNR

SINAD

At TA = +25°C, fS = 40kHz, V

DIG

= V

= +5V, and using internal reference and fixed resistors (see Figure 7b), unless otherwise specified.

ANA

FREQUENCY SPECTRUM

0

–10
–20
–30
–40
–50
–60
–70
–80

Amplitude (dB)

–90
–100
–110
–120
–130

0 5 10 15 20

100

90
80
70
60
50

SINAD (dB)

40
30
20
10

100 1k 10k 100k 1M

(8192 Point FFT; f

Frequency (kHz)

SIGNAL-TO-(NOISE + DISTORTION)

vs INPUT FREQUENCY (f

Input Signal Frequency (Hz)

= 1kHz, 0dB)

IN

= 0dB)

IN

FREQUENCY SPECTRUM

0

–10
–20
–30
–40
–50
–60
–70
–80

Amplitude (dB)

–90
–100
–110
–120
–130

0 5 10 15 20

(8192 Point FFT; f

Frequency (kHz)

= 15kHz, 0dB)

IN

SIGNAL-TO-(NOISE + DISTORTION) vs TEMPERATURE

100

95

90

85

SINAD (dB)

80

75

–75 –50 –25 0 25 50 75 100 125 150

ADS7807

SBAS022B

(f

= 1kHz, 0dB; fS = 10kHz to 40kHz)

IN

Temperature (°C)

10kHz

20kHz

30kHz

40kHz

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5

TYPICAL CHARACTERISTICS (Cont.)

At TA = +25°C, fS = 40kHz, V

3
2
1
0

–1

16-Bit (LSBs)16-Bit (LSBs)

–2

All Codes INL

–3

3
2
1
0

–1
–2

All Codes DNL

–3

0 8192 16384 24576 32768

DIG

= V

= +5V, and using internal reference and fixed resistors (see Figure 7b), unless otherwise specified.

ANA

40960 49152 57344 65535

Decimal Code

POWER-SUPPLY RIPPLE SENSITIVITY

INL/DNL DEGRADATION PER LSB OF P-P RIPPLE

1

–1

10

–2

10

–3

10

–4

10

Linearity Degradation (LSB/LSB)

–5

10

1

10

2

10

3

10

Power-Supply Ripple Frequency (Hz)

INL

DNL

4

10

5

10

6

10

7

10

3
2

BPZ Error

1
0

–1
–2

mV From Ideal

0.20

0

ENDPOINT ERRORS (20V Bipolar Range)

Percent

From Ideal

–0.20

0.20

+F

–F

Error

S

Error

S

0

Percent

From Ideal

–0.20

–75 –50 –25 0 25

50 75 100 125 150

Temperature (°C)

INTERNAL REFERENCE VOLTAGE vs TEMPERATURE

2.520

2.515

2.510

2.505

2.500

2.495

Internal Reference (V)

2.490

2.485

2.480
–75 –50 –25 0 25 50 75 100 125 150

Temperature (°C)

3
2

UPO Error

1
0

–1
–2

mV From Ideal

0.40

0.20

ENDPOINT ERRORS (Unipolar Ranges)

Percent

Percent

+F

From Ideal

0.40

0.20

From Ideal

Error (4V Range)

S

0

–F

Error (5V Range)

S

0

–75 –50 –25 0 25

50 75 100 125 150

Temperature (°C)

CONVERSION TIME vs TEMPERATURE

19.4

19.2

19

18.8

Conversion Time (µs)

18.6

–75 –50 –25 0 25 50 75 100 125 150

Temperature (°C)

6

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ADS7807

SBAS022B

BASIC OPERATION

PARALLEL OUTPUT

Figure 1a shows a basic circuit to operate the ADS7807 with
a ±10V input range and parallel output. Taking
LOW for a minimum of 40ns (12µs max) will initiate a
conversion.

BUSY

(pin 24) will go LOW and stay LOW until
the conversion is completed and the output register is up­dated. If BYTE (pin 21) is LOW, the eight Most Significant
Bits (MSBs) will be valid when

BUSY

rises; if BYTE is HIGH,
the eight Least Significant Bits (LSBs) will be valid when

BUSY

rises. Data will be output in Binary Two’s Complement

(BTC) format.

BUSY

going HIGH can be used to latch the
data. After the first byte has been read, BYTE can be toggled
allowing the remaining byte to be read. All convert com­mands will be ignored while

BUSY

is LOW.

The ADS7807 will begin tracking the input signal at the end
of the conversion. Allowing 25µs between convert com­mands assures accurate acquisition of a new signal.

The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors compen­sate for this adjustment and can be left out if the offset and gain
will be corrected in software (refer to the Calibration section).

SERIAL OUTPUT

Figure 1b shows a basic circuit to operate the ADS7807 with
a ±10V input range and serial output. Taking
LOW for 40ns (12µs max) will initiate a conversion and

R/C

R/C

(pin 22)

(pin 22)

output valid data from the previous conversion on SDATA
(pin 19) synchronized to 16 clock pulses output on DATACLK
(pin 18).

BUSY

(pin 24) will go LOW and stay LOW until the
conversion is completed and the serial data has been trans­mitted. Data will be output in BTC format, MSB first, and will
be valid on both the rising and falling edges of the data clock.

BUSY

going HIGH can be used to latch the data. All convert

commands will be ignored while

BUSY

is LOW.

The ADS7807 will begin tracking the input signal at the end
of the conversion. Allowing 25µs between convert com­mands assures accurate acquisition of a new signal.

The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors compen­sate for this adjustment and can be left out if the offset and
gain will be corrected in software (refer to the Calibration
section).

STARTING A CONVERSION

The combination of CS (pin 23) and
minimum of 40ns puts the sample-and-hold of the ADS7807
in the hold state and starts conversion ‘n’.
go LOW and stay LOW until conversion ‘n’ is completed and
the internal output register has been updated. All new con­vert commands during
or

R/C

must go HIGH before

BUSY

LOW will be ignored. CS and/

conversion will be initiated without sufficient time to acquire
a new signal.

R/C

(pin 22) LOW for a

BUSY

BUSY

goes HIGH, or a new

(pin 24) will

Parallel Output

200Ω

Pin 21

LOW

HIGH

±10V

+5V

B14 B11

(MSB)

B6 B3

66.5kΩ

2.2µF

B13 B12B15

B5 B4B7Pin 21

100Ω

2.2µF

++

1
2
3
4
5
6
7

ADS7807

8

9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

B10 B9 B8

0.1µF
+

BUSY

BYTE

(1)

NC

B2 B1 B0

(LSB)

10µF

+

R/C

+5V

Convert Pulse

40ns min

NOTE: (1) SDATA (pin 19) is always active.

FIGURE 1a. Basic ±10V Operation, both Parallel and Serial

Output.

Serial Output

200Ω

±10V

+5V

66.5kΩ

2.2µF

100Ω

2.2µF

++

(1)

NC

(1)

NC

(1)

NC

(1)

NC

(1)

NC

1
2
3
4
5
6
7

ADS7807

8

9
10
11
12
13
14

28

0.1µF

10µF

27

+

26
25
24
23
22
21
20
19
18
17
16
15

DATACLK

(1)

NC

(1)

NC

(1)

NC

+

BUSY

SDATA

+5V

Convert Pulse

R/C

40ns min

NOTE: (1) These pins should be left unconnected.
They will be active when

R/C

is HIGH.

FIGURE 1b. Basic ±10V Operation with Serial Output.

ADS7807

SBAS022B

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7

The ADS7807 will begin tracking the input signal at the end
of the conversion. Allowing 25µs between convert com­mands assures accurate acquisition of a new signal. Refer to
Tables II and III for a summary of

CS, R/C

, and

BUSY

states,

and Figures 2 through 6 for timing diagrams.

CS R/C BUSY OPERATION

1 X X None. Databus is in Hi-Z state.
↓ 0 1 Initiates conversion ‘n’. Databus remains

0 ↓ 1 Initiates conversion ‘n’. Databus enters Hi-Z

01↑ Conversion ‘n’ completed. Valid data from

↓ 1 1 Enables databus with valid data from

↓ 1 0 Enables databus with valid data from

0 ↑ 0 Enables databus with valid data from

00↑ New conversion initiated without acquisition

X X 0 New convert commands ignored. Conversion

NOTE: (1) See Figures 2 and 3 for constraints on data valid from
conversion ‘n – 1’.

in Hi-Z state.

state.

conversion ‘n’ on the databus.

conversion ‘n’.

conversion ‘n – 1’

conversion ‘n – 1’

of a new signal. Data will be invalid. CS and/or
R/C must be HIGH when BUSY goes HIGH.

‘n’ in progress.

(1)

. Conversion n in progress.

(1)

. Conversion ‘n’ in progress.

TABLE III. Control Functions When Using Parallel Output

(DATACLK tied LOW,

EXT/INT

tied HIGH).

CS

and

R/C

are internally OR’ed and level triggered. There
is not a requirement which input goes LOW first when
initiating a conversion. If, however, it is critical that

CS

or

R/C

initiates conversion ‘n’, be sure the less critical input is LOW
at least 10ns prior to the initiating input. If

EXT/INT

(pin 8) is
LOW when initiating conversion ‘n’, serial data from conver­sion ‘n – 1’ will be output on SDATA (pin 19) following the
start of conversion ‘n’. See Internal Data Clock in the Read­ing Data section.

To reduce the number of control pins,
using

R/C

to control the read and convert modes. This will

CS

can be tied LOW

have no effect when using the internal data clock in the serial
output mode. The parallel output and the serial output (only
when using an external data clock), however, will be affected
whenever

R/C

goes HIGH. Refer to the Reading Data

section.

READING DATA

The ADS7807 outputs serial or parallel data in Straight Binary
(SB) or Binary Two’s Complement data output format. If

SB/BTC

if LOW, the output will be in BTC format. Refer to Table IV for
ideal output codes.

The parallel output can be read without affecting the internal
output registers; however, reading the data through the serial
port will shift the internal output registers one bit per data

(pin 7) is HIGH, the output will be in SB format, and

CS R/C BUSY EXT/INT DATACLK OPERATION

↓ 0 1 0 Output Initiates conversion ‘n’. Valid data from conversion ‘n – 1’ clocked out on SDATA.
0 ↓ 1 0 Output Initiates conversion ‘n’. Valid data from conversion ‘n – 1’ clocked out on SDATA.
↓ 0 1 1 Input Initiates conversion ‘n’. Internal clock still runs conversion process.
0 ↓ 1 1 Input Initiates conversion ‘n’. Internal clock still runs conversion process.

↓ 1 1 1 Input Conversion ‘n’ completed. Valid data from conversion ‘n’ clocked out on SDATA synchronized

↓ 1 0 1 Input Valid data from conversion ‘n – 1’ output on SDATA synchronized to external data clock.

0 ↑ 0 1 Input Valid data from conversion ‘n – 1’ output on SDATA synchronized to external data clock.

00↑ X X New conversion initiated without acquisition of a new signal. Data will be invalid. CS and/or R/C

X X 0 X X New convert commands ignored. Conversion ‘n’ in progress.

NOTE: (1) See Figures 4, 5, and 6 for constraints on data valid from conversion “n-1”.

to external data clock.

Conversion ‘n’ in progress.

Conversion ‘n’ in progress.

must be HIGH when BUSY goes HIGH.

TABLE III. Control Functions When Using Serial Output.

DESCRIPTION ANALOG INPUT

Full-Scale Range ±10 0V to 5V 0V to 4V
Least Significant Bit (LSB) 305µV76µV61µV

+Full-Scale (FS – 1LSB) 9.999695V 4.999924V 3.999939V 0111 1111 1111 1111 7FFF 1111 1111 1111 1111 FFFF
Midscale 0V 2.5V 2V 0000 0000 0000 0000 0000 1000 0000 0000 0000 8000
One LSB Below Midscale –305µV 2.499924V 1.999939V 1111 1111 1111 1111 FFFF 0111 1111 1111 1111 7FFF
–Full-Scale –10V 0V 0V 1000 0000 0000 0000 8000 0000 0000 0000 0000 0000

BINARY TWO’S COMPLEMENT STRAIGHT BINARY

(SB/BTC LOW) (SB/BTC HIGH)

BINARY CODE CODE BINARY CODE CODE

DIGITAL OUTPUT

HEX HEX

TABLE IV. Output Codes and Ideal Input Voltages.

8

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ADS7807

SBAS022B