Texas Instruments ADS7142-Q1 Datasheet

SAR-ADC

Oscillator and

Timing Control

I2C Interface

Conversion Result

ALERT

ADDR

SCL

SDA

AINP/AIN0

AINM/AIN1

AVDD

DVDD

GND

BUSY/RDY

Accumulator

Conversion Result [0]

«««.

Conversion Result [15]

Data Buffer

Analog Input and

Multiplexer

«««.

«««.

High/Low Threshold

± Hysteresis

Digital

Window

Comparator

I2C Address

Selector

Offset

Calibration

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ADS7142-Q1

SBAS891A –NOVEMBER 2018–REVISED OCTOBER 2019

ADS7142-Q1 Automotive, 2-Channel, 12-Bit, 140-kSPS, I2C-Compatible ADC With

Programmable Threshold and Host Wake-Up Features

1 Features

1

• AEC-Q100 qualified for automotive applications:
– Device temperature grade 1:

–40°C to 125°C, T

• Small package size: 3 mm × 2 mm

• 12-bit noise-free resolution

• Up to 140-kSPS sampling rate

• Efficient host sleep and wake-up:
– Autonomous monitoring at 900 nW
– Windowed comparator for event-triggered host

wake-up

• Independent configuration and calibration:
– Dual-channel, pseudo-differential, or ground-

sense input configuration
– Programmable thresholds for calibration
– Internal calibration improves offset and drift

• False trigger prevention:
– Programmable thresholds per channel
– Programmable hysteresis for noise immunity
– Event counter for transient rejection

• I2C interface:
– Compatible from 1.65 V to 3.6 V
– 8 configurable addresses
– Up to 3.4 MHz (high speed)

• Analog supply: 1.65 V to 3.6 V

A

2 Applications

General-purpose voltage, current and temperature
monitoring in:

• Automotive camera modules

• Driver monitoring and assistance systems

• Infotainment systems and clusters

• Electric and ICE powertrain systems

3 Description

The ADS7142-Q1 is 12-bit, 140-kSPS successive­approximation register (SAR) analog-to-digital
converter (ADC) that can autonomously monitor
signals while maximizing system power, reliability,
and performance. The device implements event­triggered interrupts per channel using a digital
window comparator with programmable high and low
thresholds, hysteresis, and event counter. The device
includes a dual-channel analog multiplexer in front of
a SAR ADC followed by an internal data buffer for
converting and capturing data from sensors.

The ADS7142-Q1 is available in a 10-pin WSON
package and can achieve low power consumption of
only 900 nW. The small form-factor and low-power
consumption make this device suitable for space­constrained applications.

Device Information

PART NAME PACKAGE BODY SIZE (NOM)

ADS7142-Q1 WSON (10) 3.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at

the end of the datasheet.

(1)

1

Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

ADS7142-Q1

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics: All Modes......................... 5

6.6 Electrical Characteristics: Manual Mode................... 6

6.7 Electrical Characteristics: Autonomous Modes......... 7

6.8 Electrical Characteristics: High Precision Mode ....... 8

6.9 Timing Requirements................................................ 8

6.10 Switching Characteristics...................................... 10

6.11 Typical Characteristics: All Modes........................ 12

6.12 Typical Characteristics: Manual Mode.................. 13

6.13 Typical Characteristics: Autonomous Modes........ 17

6.14 Typical Characteristics: High-Precision Mode ...... 18

7 Detailed Description............................................ 19

4 Revision History

7.1 Overview................................................................. 19

7.2 Functional Block Diagram....................................... 19

7.3 Feature Description................................................. 20

7.4 Device Functional Modes........................................ 28

7.5 Programming........................................................... 39

7.6 Register Map........................................................... 42

8 Application and Implementation ........................ 59

8.1 Application Information............................................ 59

8.2 Typical Applications ................................................ 59

9 Power Supply Recommendations...................... 65

9.1 AVDD and DVDD Supply Recommendations......... 65

10 Layout................................................................... 66

10.1 Layout Guidelines ................................................. 66

10.2 Layout Example .................................................... 67

11 Device and Documentation Support................. 68

11.1 Receiving Notification of Documentation Updates 68

11.2 Community Resources.......................................... 68

11.3 Trademarks........................................................... 68

11.4 Electrostatic Discharge Caution............................ 68

11.5 Glossary................................................................ 68

12 Mechanical, Packaging, and Orderable

Information........................................................... 68

Changes from Original (November 2018) to Revision A Page

• Changed document status from advance information to production data.............................................................................. 1

2

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1GND 10 DVDD

2AVDD 9 SCL

3AINP/AIN0 8 SDA

4AINM/AIN1 7 ALERT

5ADDR 6 BUSY/RDY

Not to scale

Thermal

Pad

ADS7142-Q1

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SBAS891A –NOVEMBER 2018–REVISED OCTOBER 2019

5 Pin Configuration and Functions

DQC Package

10-Pin WSON

Top View

Pin Functions

PIN

NO. NAME

1 GND Supply Ground for power supply, all analog and digital signals are referred to this pin.
2 AVDD Supply Analog supply input, also used as the reference voltage for analog-to-digital conversion.

3 AINP/AIN0 Analog input

4 AINM/AIN1 Analog input

5 ADDR Analog Input

6 BUSY/RDY Digital output

7 ALERT Digital output
8 SDA Digital input/output Serial data input/output for the I2C interface. Connect a pullup resistor from DVDD to this pin.

9 SCL Digital input Serial clock for the I2C interface. Connect a pullup resistor from DVDD to this pin.
10 DVDD Supply Digital I/O supply voltage.

I/O DESCRIPTION

Single-channel operation: positive analog signal input.
Two-channel operation: analog signal input, channel 0.

Single-channel operation: negative analog signal input.
Two-channel operation: analog signal input, channel 1.

Input for selecting the I2C address of the device.
See the I2C Address Selection section for details.

The device pulls this pin high when scanning through channels in a sequence and brings this pin
low when the sequence is completed or aborted.

Active low, open-drain output. The status of this pin is controlled by the digital window
comparator block. Connect a pullup resistor from DVDD to this pin.

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

ADDR to GND –0.3 AVDD + 0.3 V
AVDD to GND –0.3 3.9 V
DVDD to GND –0.3 3.9 V
AINP/AIN0 to GND –0.3 AVDD + 0.3 V
AINM/AIN1 to GND –0.3 AVDD + 0.3 V
Input current on any pin except supply pins –10 10 mA
Digital input to GND –0.3 DVDD + 0.3 V
Junction temperature, T
Storage temperature, T

J

stg

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

Human-body model (HBM), per AEC Q100-002

V

(ESD)

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

Electrostatic discharge

Charged-device model (CDM), per AEC
Q100-011

(1)

MIN MAX UNIT

–40 150 °C
–60 150 °C

VALUE UNIT

(1)

Corner pins (1, 5, 6, and

10)

±2000

±750

V

All other pins ±500

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

AVDD Analog supply voltage range 1.65 3.6 V
DVDD Digital supply voltage range 1.65 3.6 V
T

A

Ambient temperature –40 125 °C

6.4 Thermal Information

ADS7142-Q1

THERMAL METRIC

R

θJA

R

θJC(top)

R

θJB

Ψ

JT

Ψ

JB

R

θJC(bot)

Junction-to-ambient thermal resistance 61.8 °C/W
Junction-to-case (top) thermal resistance 66.3 °C/W
Junction-to-board thermal resistance 29.8 °C/W
Junction-to-top characterization parameter 2.1 °C/W
Junction-to-board characterization parameter 29.7 °C/W
Junction-to-case (bottom) thermal resistance 6.1 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(1)

UNITDQC (WSON)

10 PINS

4

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6.5 Electrical Characteristics: All Modes

at TA= -40°C to 125°C, AVDD = 3 V, DVDD = 1.65 V to 3.6 V, All Channel Configurations (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ANALOG INPUT (Two-Channel Single-Ended Configuration)

Full-scale input voltage

(1)

span
Absolute input voltage

range

ANALOG INPUT (Single-Channel Single-Ended Configuration with Remote Ground Sense)

Full-scale input voltage

(1)

span
Absolute input voltage

range

ANALOG INPUT (Single-Channel Pseudo-Differential Configuration with Remote Ground Sense)

Full-scale input voltage

(1)

span
Absolute input voltage

range

INTERNAL OSCILLATOR

t

HSO

t

LPO

Time period for high­speed oscillator

Time period for low-power
oscillator

DIGITAL INPUT/OUTPUT (SCL, SDA)

V
V

V

I

OL

I

OL

I

I

C

High-level input voltage 0.7 × DVDD DVDD V

IH

Low-level input voltage 0 0.3 × DVDD V

IL

Low-level output voltage

OL

Low-level output current
(sink)

Low-level output current
(sink)

Input current on pin 10 µA
Input capacitance on pin 10 pF

I

DIGITAL OUTPUT (BUSY/RDY)

V
V

High-level output voltage I

OH

Low-level output voltage I

OL

DIGITAL OUTPUT (ALERT)

I

OL

V

Low-level output current VOL< 0.25 V 5 mA
Low-level output voltage I

OL

POWER-SUPPLY REQUIREMENTS

AVDD Analog supply voltage 1.65 3.6 V
DVDD Digital I/O supply voltage 1.65 3.6 V

(1) Ideal Input span, does not include gain or offset error.

AINP/AIN0 to GND or AINM/AIN1 to GND 0 AVDD V

AINP/AIN0 to GND or AINM/AIN1 to GND –0.1 AVDD + 0.1 V

AINP/AIN0 to AINM/AIN1 0 AVDD V
AINP/AIN0 to GND –0.1 AVDD + 0.1

AINM/AIN1 to GND –0.1 0.1

AINP/AIN0 to AINM/AIN1 –AVDD/2 AVDD/2 V
AINP/AIN0 to GND –0.1 AVDD + 0.1

AINM/AIN1 to GND AVDD/2–0.1 AVDD/2+0.1

50 110 ns

95.2 300 µs

With 3 mA sink current and DVDD > 2 V 0 0.4
With 3 mA sink current and 1.65 V < DVDD <

2 V
VOL= 0.4 V for standard and fast mode (100,

400 kHz)

0 0.2 × DVDD

3

VOL= 0.6 V for fast mode (400 kHz) 6
VOL= 0.4 V fast mode Plus (1 MHz) 20

VOL= 0.4 V high speed (1.7 MHz, 3.4 MHz) 25 mA

= 2 mA 0.7 × DVDD DVDD V

source

= 2 mA 0 0.3 × DVDD V

sink

= 5 mA 0 0.25 V

sink

(1)

V

V

V

mA

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6.6 Electrical Characteristics: Manual Mode

at TA= -40°C to 125°C, AVDD = 3 V, DVDD = 1.65 V to 3.6 V, All Channel Configurations (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SAMPLING DYNAMICS

t

conv

t

acq

t

cycle

DC SPECIFICATIONS

NMC No missing codes AVDD = 1.65 V to 3.6 V 12 Bits
DNL Differential nonlinearity AVDD = 1.65 V to 3.6 V –0.99 ±0.3 1 LSB
INL Integral nonlinearity –2.75 ±0.5 2.75 LSB
E

O

dVOS/dT Offset drift with temperature Post offset calibration 5 ppm/°C
E

G

AC SPECIFICATIONS

(2)

SNR

(2)(3)

THD

SINAD

SFDR
BW –3-dB small-signal bandwidth 25 MHz

POWER CONSUMPTION

I

AVDD

I

DVDD

I

AVDD

I

DVDD

(1) LSB means least significant byte. See the ADC Transfer Function for details.
(2) All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full-scale,

unless otherwise specified.

(3) Calculated on the first nine harmonics of the input frequency.

Conversion time AVDD = 1.65 V to 3.6 V 1.8 µs
Acquisition time AVDD = 1.65 V to 3.6 V 18 T
Cycle time AVDD = 1.65 V to 3.6 V, SCL = 3.4 MHz 7.1 µs

Resolution 12 Bits

Offset error Post offset calibration –4 ±0.5 4 LSB

Gain error –0.1 ±0.03 0.1 %FSR
Gain error drift with

temperature

Signal-to-noise ratio

Total harmonic distortion

(2)

Signal-to-noise and distortion

(2)

Spurious-free dynamic range

Analog supply current

Digital supply current

fIN= 2 kHz, AVDD = 3 V,
f

= 140 kSPS

SAMPLE

68.75 70

fIN= 2 kHz, AVDD = 1.8 V,
f

= 140 kSPS

SAMPLE

fIN= 2 kHz, AVDD = 3 V,
f

= 140 kSPS

SAMPLE

fIN= 2 kHz, AVDD = 1.8 V,
f

= 140 kSPS

SAMPLE

fIN= 2 kHz, AVDD = 3 V,
f

= 140 kSPS

SAMPLE

68.5 69.5

fIN= 2 kHz, AVDD = 1.8 V,
f

= 140 kSPS

SAMPLE

fIN= 2 kHz, AVDD = 3 V,
f

= 140 kSPS

SAMPLE

f

= 140 kSPS, SCL = 3.4 MHz 265 300

SAMPLE

f

= 5.5 kSPS, SCL = 100 kHz 8

SAMPLE

f

= 140 kSPS, SCL = 3.4 MHz, AVDD

SAMPLE

= 1.8 V
f

= 5.5 kSPS, SCL = 100 kHz, AVDD

SAMPLE

= 1.8 V
f

= 140 kSPS, SCL = 3.4 MHz, SDA =

SAMPLE

AAA0h
f

= 5.5 kSPS, SCL = 100 kHz, SDA =

SAMPLE

AAA0h
f

= 140 kSPS, SCL = 3.4 MHz, AVDD

SAMPLE

= 1.8 V, SDA = AAA0h

5 ppm/°C

68

–85

–80

67.5

90 dB

160

5

25

2

15

Static analog supply current No activity on SCL and SDA 6 nA
Static digital supply current No activity on SCL and SDA 2 nA

(1)

SCL

(1)

dB

dB

dB

µA

µA

6

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6.7 Electrical Characteristics: Autonomous Modes

at TA= -40°C to 125°C, AVDD = 3 V, DVDD = 1.65 V to 3.6 V, All Channel Configurations (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SAMPLING DYNAMICS

t

conv

t

acq

t

cycle

Conversion time

Acquisition time

Cycle time

DC SPECIFICATIONS

Resolution 12 Bits
E
E

Offset error Post offset calibration ±0.5 LSB

O

Gain error ±0.03 %FSR

G

POWER CONSUMPTION

I

AVDD

I

DVDD

I

AVDD

I

DVDD

Analog supply current

Digital supply current

Static analog supply current No activity on SCL and SDA 5 nA

Static digital supply current No activity on SCL and SDA 0.6 nA

High-speed oscillator 14 t
Low-power oscillator 14 t
High-speed oscillator 7 t
Low-power oscillator 4 t
High-speed oscillator nCLK t
Low-power oscillator nCLK t

With low-power oscillator, nCLK = 18 0.75
With low-power oscillator, AVDD = 1.8 V,

nCLK = 18

0.45

With low-power oscillator, nCLK = 250 0.5
With low-power oscillator, nCLK = 21 940
With low-power oscillator, nCLK = 18, DVDD

= 3.3 V
With low-power oscillator, DVDD = 1.8 V,

nCLK = 18
With low-power oscillator, nCLK = 250,

DVDD = 3.3 V
With high-power oscillator, nCLK = 21,

DVDD = 3.3 V

0.15

0.25

0.15

0.15

HSO

LPO

HSO

LPO

HSO

LPO

µA

µA

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6.8 Electrical Characteristics: High Precision Mode

at TA= -40°C to 125°C, AVDD = 3 V, DVDD = 1.65 V to 3.6 V, All Channel Configurations (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DC SPECIFICATIONS

Resolution
ENOB Effective number of bits With DC input of AVDD / 2
E
E

Offset error Post offset calibration ±10 LSB

O

Gain error ±0.03 %FSR

G

POWER CONSUMPTION

I

AVDD

I

DVDD

I

AVDD

I

DVDD

Analog supply current

Digital supply current

Static analog supply current No activity on SCL and SDA 5 nA

Static analog supply current No activity on SCL and SDA 0.7 nA

(1) Sampling dynamics for high precision mode are same as for autonomous modes.
(2) See Equation 5
(3) For DC input, ENOB = Ln[FSR/Standard deviation of Codes]/Ln[2]. See

(2)

(3)

16

15.4

With low-power oscillator, nCLK = 18 0.6
With low-power oscillator, AVDD = 1.8 V,

nCLK = 18

0.3

With low-power oscillator, nCLK = 250 0.5
With high-speed oscillator, nCLK = 21 980
With low-power oscillator, nCLK = 21, DVDD

= 3.3 V
With low-power oscillator, DVDD = 1.8 V,

nCLK = 21
With low-power oscillator, nCLK = 250,

DVDD = 3.3 V
With high-speed oscillator, nCLK = 21,

DVDD = 3.3 V

0.2

0.25

0.2

0.2

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(1)

Bits

µA

µA

6.9 Timing Requirements

at TA= -40°C to 125°C, AVDD = 3 V, DVDD = 1.65 V to 3.6 V, All Channel Configurations (unless otherwise noted)

PARAMETER MIN MAX UNIT

STANDARD MODE (100 kHz)

f

SCL

t

HD-STA

t

LOW

t

HIGH

t

SU-STA

(2)(3)

t

HD-DAT

t

SU-DAT

t

SU-STO

t

BUF

C

b

FAST MODE (400 kHz)

f

SCL

t

HD-STA

t

LOW

t

HIGH

(1) All values referred to V
(2) t
(3) The maximum t

8

is the data hold time that is measured from the falling edge of SCL and applies to data in transmission and the acknowledge.

HD-DAT

t

by a transition time. This maximum must only be met if the device does not stretch the LOW period (t

VD-ACK

the clock is streched, the data must be valid by the setup time before being released.

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SCL clock frequency 0 100 kHz
Hold time (repeated) START condition 4 µs
Low period of SCL 4.7 µs
High period of SCL 4 µs
Setup time for a repeated start condition 4.7 µs
Data hold time 0 µs
Data setup time 250 ns
Data setup time 4 µs
Bus free time between a STOP and START

condition

4.7 µs

Capacitive load on each line 400 pF

SCL clock frequency 0 400 kHz
Hold time (repeated) START condition 0.6 µs
Low period of SCL 1.3 µs
High period of SCL 0.6 µs

(0.7 DVDD) and V

IH(min)

can be 3.45 µs and 0.9 µs for standard-mode and fast-mode, but must be less than the maximum of t

HD-DAT

IL(max)

(0.3 DVDD).

) of the SCL signal. If

LOW

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Timing Requirements (continued)

at TA= -40°C to 125°C, AVDD = 3 V, DVDD = 1.65 V to 3.6 V, All Channel Configurations (unless otherwise noted)

PARAMETER MIN MAX UNIT

t

SU-STA

t

HD-DAT

t

SU-DAT

t

SU-STO

t

BUF

C

b

FAST MODE PLUS (1000 kHz)

f

SCL

t

HD-STA

t

LOW

t

HIGH

t

SU-STA

t

HD-DAT

t

SU-DAT

t

SU-STO

t

BUF

C

b

HIGH SPEED MODE (1.7 MHz, Cb= 400 pF max)

f

SCLH

t

HD-STA

t

LOW

t

HIGH

t

SU-STA

t

HD-DAT

t

SU-DAT

t

SU-STO

C

b

HIGH SPEED MODE (3.4 MHz, Cb= 100 pF max)

f

SCLH

t

HD-STA

t

LOW

t

HIGH

t

SU-STA

t

HD-DAT

t

SU-DAT

t

SU-STO

C

b

Setup time for a repeated start condition 0.6 µs
Data hold time 0 µs
Data setup time 100 ns
Data setup time 0.6 µs
Bus free time between a STOP and START

condition

1.3 µs

Capacitive load on each line 400 pF

SCL clock frequency 0 1000 kHz
Hold time (repeated) START condition 0.26 µs
Low period of SCL 0.5 µs
High period of SCL 0.26 µs
Setup time for a repeated start condition 0.26 µs
Data hold time 0 µs
Data setup time 50 ns
Data setup time 0.26 µs
Bus free time between a STOP and START

condition

0.5 µs

Capacitive load on each line 550 pF

SCLH clock frequency 0 1.7 MHz
Hold time (repeated) START condition 160 ns
Low period of SCL 320 ns
High period of SCL 120 ns
Setup time for a repeated start condition 160 ns
Data hold time 0 150 ns
Data setup time 10 ns
Data setup time 160 ns
Capacitive load on each line 100 pF

SCLH clock frequency 0 3.4 MHz
Hold time (repeated) START condition 160 ns
Low period of SCL 160 ns
High period of SCL 60 ns
Setup time for a repeated start condition 160 ns
Data hold time 0 70 ns
Data setup time 10 ns
Data setup time 160 ns
Capacitive load on each line 100 pF

(1)

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6.10 Switching Characteristics

at TA= -40°C to 125°C, AVDD = 3 V, DVDD = 1.65 V to 3.6 V, All Channel Configurations (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

STANDARD MODE (100 kHz)

t

rCL

t

rDA

t

fCL

t

fDA

(2)

t

VD-DAT

(2)

t

VD-ACK

FAST MODE (400 kHz)

t

rCL

t

rDA

t

fCL

t

fDA

t

VD-DAT

t

VD-ACK

(3)

t

SP

FAST MODE PLUS (1000 kHz)

t

rCL

t

rDA

t

fCL

t

fDA

t

VD-DAT

t

VD-ACK

t

SP

HIGH SPEED MODE (1.7 MHz, Cb= 400 pF max)

t

rCL

t

rCL1

t

rDA

t

fCL

t

fDA

t

SP

HIGH SPEED MODE (3.4 MHz, Cb= 100 pF max)

t

rCL

t

rCL1

t

rDA

t

fCL

t

fDA

t

SP

Rise time of SCL 1000 ns
Rise time of SDA 1000 ns
Fall time of SCL 300 ns
Fall time of SDA 300 ns
Data valid time 3.45 µs
Data hold time 3.45 µs

Rise time of SCL 20 300 ns
Rise time of SDA 20 300 ns
Fall time of SCL 20 × DVDD/3.6 300 ns
Fall time of SDA 20 × DVDD/3.6 300 ns
Data valid time 0.9 µs
Data hold time 0.9 µs
Pulse duration of spikes suppressed by the

input filter

0 50 ns

Rise time of SCL 120 ns
Rise time of SDA 120 ns
Fall time of SCL 20 × DVDD/3.6 120 ns
Fall time of SDA 20 × DVDD/3.6 120 ns
Data valid time 0.45 µs
Data hold time 0.45 µs
Pulse duration of spikes suppressed by the

input filter

0 50 ns

Rise time of SCLH 20 80 ns
Rise time of SCLH after a repeated start

condition and after an acknowledge bit

20 160 ns

Rise time of SDAH 20 160 ns
Fall time of SCLH 20 80 ns
Fall time of SDAH 20 160 ns
Pulse duration of spikes suppressed by the

input filter

0 10 ns

Rise time of SCLH 10 40 ns
Rise time of SCLH after a repeated start

condition and after an acknowledge bit

10 80 ns

Rise time of SDAH 10 80 ns
Fall time of SCLH 10 40 ns
Fall time of SDAH 10 80 ns
Pulse duration of spikes suppressed by the

input filter

0 10 ns

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(1)

(1) All values referred to V
(2) t
(3) Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.

10

= time for data signal from SCL LOW to SDA output.

VD-DAT

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( 0.7 DVDD ) and V

IH(min)

IL(max)

( 0.3 DVDD ).

Product Folder Links: ADS7142-Q1

Sr

t

fDA

t

rDA

t

HD-DAT

t

SU-DAT

SDAH or SDA

t

SU-STA

t

HD-STA

SCLH or SCL

t

rCL1

t

HIGH

t

LOW

t

FCL

t

rCL

t

LOW

t

HIGH

t

rCL1

t

SU-STO

Sr P

0.7 x V

DD

0.3 x V

DD

0.7 x V

DD

0.3 x V

DD

= MCS current source pull-up

= Rp resistor pull-up

(1)

(1)

t

f

t

r

t

SU-DAT

t

HD-DAT

t

VD-DAT

«

cont.

«

cont.

9th clock

SDA

SCL

70%

30%

70%

30%

70%

30% 30%

70%

70%

30%

70%

30%

t

HIGH

t

LOW

t

HD-STA

S

1/f

SCL

1st clock cycle

. . . SDA

. . . SCL

t

r

t

SU-STA

t

HD-STA

Sr

t

SP

t

VD-ACK

70%

30%

9th clock

t

BUF

S

P

t

SU-STO

VIL = 0.3V

DD

VIH = 0.7V

DD

t

f

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ADS7142-Q1

SBAS891A –NOVEMBER 2018–REVISED OCTOBER 2019

Figure 1. Timing Diagram for Standard Mode, Fast Mode, and Fast Mode Plus

(1) First rising edge of the SCLH signal after Sr and after each acknowledge bit.

Figure 2. Timing Diagram for High-Speed Mode

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11

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Free-Air Temperature (qC)

Time Period (ns)

-40 -7 26 59 92 125

40

44

48

52

56

60

ADS7

Free-Air Temperature (qC)

Time Period (Ps)

-40 -7 26 59 92 125

60

80

100

120

140

160

ADS7

ADS7142-Q1

SBAS891A –NOVEMBER 2018–REVISED OCTOBER 2019

6.11 Typical Characteristics: All Modes

at TA= 25°C, AVDD = 3 V, DVDD = 3.3 V, and two-channel single-ended configuration (unless otherwise noted)

Figure 3. High-Speed Oscillator Time Period vs Temperature Figure 4. Low-Power Oscillator Time Period vs Temperature

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12

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Free-Air Temperature (qC)

THD (dB)

-40 -7 26 59 92 125

-90

-88.4

-86.8

-85.2

-83.6

-82

ADS7

Free-Air Temperature (qC)

SFDR (dB)

-40 -7 26 59 92 125

88

88.6

89.2

89.8

90.4

91

ADS7

Free-Air Temperature (qC)

Amplitude (dB)

-40 -7 26 59 92 125

68

69

70

71

72

73

ADS7

SNR
SINAD

Free-Air Temperature (qC)

Amplitude (dB)

1.8 2.16 2.52 2.88 3.24 3.6

67

68

69

70

71

72

ADS7

SNR
SINAD

fIN, Input Frequency (Hz)

Amplitude (dB)

0 10000 20000 30000 40000 50000

-160

-140

-120

-100

-80

-60

-40

-20

0

ADS7

fIN, Input Frequency (Hz)

Amplitude (dB)

0 10000 20000 30000 40000 50000

-180

-160

-140

-120

-100

-80

-60

-40

-20

0

ADS7

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SBAS891A –NOVEMBER 2018–REVISED OCTOBER 2019

6.12 Typical Characteristics: Manual Mode

at TA= 25°C, AVDD = 3 V, DVDD = 3.3 V, and two-channel single-ended configuration (unless otherwise noted)

ADS7142-Q1

SNR = 69.6 dB, THD = –84 dB, ENOB = 11.2,

f

= 140 kSPS, SFDR = 87 dB, AVDD = 1.8 V

sample

Figure 5. Typical FFT in Manual Mode

f

= 140 kSPS

sample

Figure 7. SNR and SINAD in Manual Mode vs Temperature

SNR = 71.3 dB, THD = –87 dB, ENOB = 11.5,

f

= 140 kSPS, SFDR = 89.3 dB, AVDD = 3 V

sample

Figure 6. Typical FFT in Manual Mode

f

= 140 kSPS

sample

Figure 8. SNR and SINAD in Manual Mode vs AVDD

Figure 9. THD in Manual Mode vs Temperature

f

sample

= 140 kSPS

Figure 10. SFDR in Manual Mode vs Temperature

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f

sample

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= 140 kSPS

13

Free-Air Temperature (qC)

Gain Error (FSR)

-40 -7 26 59 92 125

-0.05

-0.03

-0.01

0.01

0.03

0.05

ADS7

AVDD (V)

Gain Error (FSR)

1.8 2.16 2.52 2.88 3.24 3.6

-0.02

-0.002

0.016

0.034

0.052

0.07

ADS7

Free-Air Temperature (qC)

Offset Error (LSB)

-40 -7 26 59 92 125

1

1.4

1.8

2.2

2.6

3

ADS7

AVDD (V)

Offset Error (LSB)

1.8 2.16 2.52 2.88 3.24 3.6

0.5

0.9

1.3

1.7

2.1

2.5

ADS7

AVDD (V)

THD (dB)

1.8 2.16 2.52 2.88 3.24 3.6

-93

-90

-87

-84

-81

-78

ADS7

Output Code

Number of Hits

0

20000

40000

60000

2047 2048 2049

3790

3046

ADS7

ADS7142-Q1

SBAS891A –NOVEMBER 2018–REVISED OCTOBER 2019

Typical Characteristics: Manual Mode (continued)

at TA= 25°C, AVDD = 3 V, DVDD = 3.3 V, and two-channel single-ended configuration (unless otherwise noted)

www.ti.com

f

= 140 kSPS

sample

Figure 11. THD in Manual Mode vs AVDD

Mean code = 2047.9, standard deviation = 0.32

Figure 12. Typical DC Code Spread in Manual Mode

Figure 13. Offset Error in Manual Mode vs Temperature Figure 14. Offset Error in Manual Mode vs AVDD

14

Figure 15. Gain Error in Manual Mode vs Free-Air

Temperature

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Figure 16. Gain Error in Manual Mode vs AVDD

Free-Air Temperature (qC)

Differential Nonlinearity (LSB)

-40 -7 26 59 92 125

-1

-0.6

-0.2

0.2

0.6

1

ADS7

Maximum
Minimum

AVDD (V)

Differential Nonlinearity (LSB)

1.8 2.16 2.52 2.88 3.24 3.6

-1

-0.6

-0.2

0.2

0.6

1

ADS7

Maximum
Minimum

Output Code

Integral Nonlinearity (LSB)

0 819 1638 2457 3276 4095

-1.2

-0.6

0

0.6

1.2

ADS7

Output Code

Integral Nonlinearity (LSB)

0 819 1638 2457 3276 4095

-1

-0.6

-0.2

0.2

0.6

1

ADS7

Output Code

Differential Nonlinearity (LSB)

0 819 1638 2457 3276 4095

-0.5

-0.3

-0.1

0.1

0.3

0.5

ADS7

Output Code

Differential Nonlinearity (LSB)

0 819 1638 2457 3276 4095

-0.5

-0.3

-0.1

0.1

0.3

0.5

ADS7

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SBAS891A –NOVEMBER 2018–REVISED OCTOBER 2019

Typical Characteristics: Manual Mode (continued)

at TA= 25°C, AVDD = 3 V, DVDD = 3.3 V, and two-channel single-ended configuration (unless otherwise noted)

ADS7142-Q1

AVDD = 3 V

Figure 17. Typical DNL in Manual Mode

AVDD = 3 V

Figure 19. Typical INL in Manual Mode

AVDD = 1.8 V

Figure 18. Typical DNL in Manual Mode

AVDD = 1.8 V

Figure 20. Typical INL in Manual Mode

Figure 21. DNL in Manual Mode vs Temperature Figure 22. DNL in Manual Mode vs AVDD

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15

SCL (kHz)

I

DVDD

(PA)

0 500 1000 1500 2000 2500 3000 3500

0

2.5

5

7.5

10

12.5

15

17.5

20

ADS7

Free-Air Temperature (qC)

I

AVDD

(PA)

-40 -7 26 59 92 125

-0.2

0

0.2

0.4

0.6

0.8

ADS7

AVDD = 1.8 V
AVDD = 3 V

AVDD (V)

I

AVDD

(PA)

1.8 2.16 2.52 2.88 3.24 3.6

100

150

200

250

300

350

ADS7

Free-Air Temperature (qC)

I

AVDD

(PA)

-40 -7 26 59 92 125

230

236

242

248

254

260

ADS7

Free-Air Temperature (qC)

Integral Nonlinearity (LSB)

-40 -7 26 59 92 125

-1.5

-1

-0.5

0

0.5

1

ADS7

Maximum
Minimum

AVDD (V)

Integral Nonlinearity (LSB)

1.8 2.16 2.52 2.88 3.24 3.6

-2

-1.4

-0.8

-0.2

0.4

1

ADS7

Maximum
Minimum

ADS7142-Q1

SBAS891A –NOVEMBER 2018–REVISED OCTOBER 2019

Typical Characteristics: Manual Mode (continued)

at TA= 25°C, AVDD = 3 V, DVDD = 3.3 V, and two-channel single-ended configuration (unless otherwise noted)

Figure 23. INL in Manual Mode vs Temperature Figure 24. INL in Manual Mode vs AVDD

www.ti.com

f

= 140 kSPS, SCL = 3.4 MHz

Sample

Figure 25. I

16

Figure 27. I

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in Manual Mode vs AVDD Figure 26. I

AVDD

DVDD = 1.8 V

in Manual Mode vs SCL

DVDD

Figure 28. Static I

Product Folder Links: ADS7142-Q1

in Manual Mode vs Temperature

AVDD

No activity on SCL and SDA

in Manual Mode vs Temperature

AVDD

Free-Air Temperature (qC)

I

AVDD

(nA)

-40 -7 26 59 92 125

0

300

600

900

1200

1500

ADS7

AVDD = 1.8 V
AVDD = 3 V

Free-Air Temperature (qC)

I

AVDD

(PA)

-40 -7 26 59 92 125

0

300

600

900

1200

1500

Auto

AVDD = 1.8 V
AVDD = 3 V

nCLK

Analog Input Current (PA)

0 45 90 135 180 225 270

0

3

6

9

12

ADS7

nCLK

Analog Input Current (nA)

0 45 90 135 180 225 270

0

1.6

3.2

4.8

6.4

8

AINC

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SBAS891A –NOVEMBER 2018–REVISED OCTOBER 2019

6.13 Typical Characteristics: Autonomous Modes

at TA= 25°C, AVDD = 3 V, DVDD = 3.3 V, and two-channel single-ended configuration (unless otherwise noted)

ADS7142-Q1

Input voltage = 1.5 V, CH0, high-speed oscillator, stop burst mode

Figure 29. Analog Input Current in Autonomous Modes vs

nCLK

Stop burst mode, low-power oscillator, nCLK = 25

Figure 31. I

in Autonomous Modes vs Temperature

AVDD

Input voltage = 1.5 V, CH0, low-power oscillator, stop burst mode

Figure 30. Analog Input Current in Autonomous Modes vs

nCLK

Stop burst mode, high-speed oscillator, nCLK = 25

Figure 32. I

in Autonomous Modes vs Temperature

AVDD

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17

Free-Air Temperature (qC)

I

AVDD

(nA)

-40 -7 26 59 92 125

0

300

600

900

1200

ADS7

AVDD = 1.8 V
AVDD = 3 V

Free-Air Temperature (qC)

I

AVDD

(PA)

-40 -7 26 59 92 125

0

300

600

900

1200

AVDD = 1.8 V
AVDD = 3 V

Free-Air Temperature (qC)

Offset Error (LSB)

-40 -7 26 59 92 125

-2

1

4

7

10

Offs

Free-Air Temperature(qC)

Gain Error (FSR)

-40 -7 26 59 92 125

-0.03

-0.018

-0.006

0.006

0.018

0.03

Gain

ADS7142-Q1

SBAS891A –NOVEMBER 2018–REVISED OCTOBER 2019

6.14 Typical Characteristics: High-Precision Mode

at TA= 25°C, AVDD = 3 V, DVDD = 3.3 V, and two-channel single-ended configuration (unless otherwise noted)

www.ti.com

Figure 33. Offset Error in High-Precision Mode vs

Temperature

Low-power oscillator, nCLK = 25

Figure 35. I

in High-Precision Mode vs Temperature

AVDD

Figure 34. Gain Error in High-Precision Mode vs

Temperature

High-speed oscillator, nCLK = 25

Figure 36. I

in High-Precision Mode vs Temperature

AVDD

18

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SAR-ADC

Oscillator and

Timing Control

I2C Interface

Conversion Result

ALERT

ADDR

SCL

SDA

AINP/AIN0

AINM/AIN1

AVDD

DVDD

GND

BUSY/RDY

Accumulator

Conversion Result [0]

«««.

Conversion Result [15]

Data Buffer

Analog Input and

Multiplexer

«««.

«««.

High/Low Threshold

± Hysteresis

Digital

Window

Comparator

I2C Address

Selector

Offset

Calibration

ADS7142-Q1

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SBAS891A –NOVEMBER 2018–REVISED OCTOBER 2019

7 Detailed Description

7.1 Overview

The ADS7142-Q1 is a small size, dual-channel, 12-bit programmable sensor monitor with an integrated analog­to-digital converter (ADC), input multiplexer, digital comparator, data buffer, accumulator and internal oscillator.
The input multiplexer can be either configured as two single-ended channels, one single-ended channel with
remote ground sensing, or one pseudo-differential channel where the input can swing to approximately AVDD /

2. The device includes a digital window comparator with a dedicated output pin, which can be used to alert the
host when a programmed high or low threshold is crossed. The device address is configured by the I2C address

selector block. The device uses internal oscillators (high speed or low power) for conversion. The start of

conversion is controlled by the host in manual mode and by the device in the autonomous modes.
The device also features a data buffer and an accumulator. The data buffer can store up to 16 conversion results

of the ADC in the autonomous modes and the accumulator can accumulate up to 16 conversion results of the
ADC in high-precision mode.

The device includes an offset calibration to calibration its own offset.

7.2 Functional Block Diagram

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19

AINP/AIN0

AINM/AIN1

AVDD

GND

GND + 100mV

GND -100mV

GND

C

s1

C

s

2

V_BIAS

SW

1

R

s1

R

s2

GND

SW

2

MUX

CHANNEL_INPUT_CFG_REG

AINP/AIN0

AINM/AIN1

AVDD

GND

AVDD/2 + 100mV

AVDD/2-100mV

AVDD/2

C

s1

C

s

2

V_BIAS

SW

1

R

s1

R

s2

GND

SW

2

MUX

CHANNEL_INPUT_CFG_REG

AVDD/2

C

s1

C

s

2

AVDD

AVDD

V_BIAS

AINP/AIN0

AINM/AIN1

SW

1

R

s1

R

s2

GND

SW

2

MUX

CHANNEL_INPUT_CFG_REG

AVDD

GND

AVDD

GND

CH0

CH1

C

s1

C

s

2

V_BIAS

AINP/AIN0

AINM/AIN1

SW

1

R

s

1

R

s2

GND

SW

2

MUX

CHANNEL_INPUT_CFG_REG

CH0
CH1

ADS7142-Q1

SBAS891A –NOVEMBER 2018–REVISED OCTOBER 2019

www.ti.com

7.3 Feature Description

7.3.1 Analog Input and Multiplexer

Figure 37 shows a small-signal equivalent circuit for the analog input pins. The device includes a two-channel

analog multiplexer with each input pin having ESD protection diodes to AVDD and GND. The sampling switches
are represented by ideal switches SW1and SW2in series with resistors Rs1and Rs2(typically 150 Ω). The
sampling capacitors, Cs1and Cs2, are typically 15 pF. The multiplexer configuration is set by the
CH_INPUT_CFG register.

During acquisition, switches SW1and SW2are closed to allow the input signal to charge the internal sampling
capacitors.

During conversion, switches SW1and SW2are opened to disconnect the input signal from the sampling
capacitors.

The analog input of the device are optimized to be driven by high impedance source (up-to 100 kΩ) in

Autonomous Modes or in High Precision Mode mode with low power oscillator. It is recommended to drive the

analog input of the device with an external amplifier when in Autonomous Modes or in High Precision Mode
mode with a high-speed oscillator. Figure 29 and Figure 30 provide the analog input current for CH0 and CH1 of
the device.

Figure 38, Figure 39 and Figure 40 provide a simplified circuit for analog input for input configurations described

in Two-Channel, Single-Ended Configuration, Single-Channel, Single-Ended Configuration and Single-Channel,

Pseudo-Differential Configuration respectively. The analog multiplexer supports following input configurations (set

by writing into the CH_INPUT_CFG register).

Figure 37. Equivalent Circuit for Analog Input

Figure 38. Two-Channel, Single-Ended Configuration

Figure 39. Single-Channel, Single-Ended Configuration

With Remote Ground Sensing

7.3.1.1 Two-Channel, Single-Ended Configuration

Figure 38 shows a simplified block diagram showing a two-channel, single-ended configuration. Set the

CH0_CH1_IP_CFG bits = 00b or 11b to select this configuration. This configuration is also the default for the
device after power up. In this configuration, CS2always samples the GND pin and CS1samples the input signal
provided on channel 0 (AINP/AIN0) or channel 1 (AINM/AIN1) based on the channel selection. Each analog input
channel can accept input signals in the range 0 V to AVDD V.

20

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Figure 40. Single-Channel, Pseudo-Differential

Configuration

ADS7142-Q1

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SBAS891A –NOVEMBER 2018–REVISED OCTOBER 2019

Feature Description (continued)

On power-up, the device wakes up in manual mode with two-channel, single-ended configuration and samples
CH0 only. This configuration can also be set by setting OPMODE_SEL to 000b or 001b,

The device can be configured to sample either CH0 or CH1 or both channels by setting bits in the
AUTO_SEQ_CHEN register to select the channels.

• To select a channel in AUTO sequence, set AUTO_SEQ_CHx bit in the AUTO_SEQ_CHEN register to 1.

• Set the bits in the OPMODE_SEL register to 100b or 101b for manual mode with AUTO sequence.

• Set the bits in the OPMODE_SEL register to 110b for Autonomous Modes with AUTO sequence.

• Set the bits in the OPMODE_SEL register to 111b for High Precision Mode with AUTO sequence.

7.3.1.2 Single-Channel, Single-Ended Configuration

See Figure 39 for a simplified block diagram showing a single-channel, single ended configuration. Set
CH0_CH1_IP_CFG bits = 01b to select this configuration. In this configuration, CS1samples the input signal
provided on the AINP/AIN0 pin whereas CS2samples input signal provided on the AINM/AIN1 pin. AINP/AIN0 pin
can accept input signals in the range 0 V to AVDD V and AINM/AIN1 pin can accept input signals in the range
–100 mV to +100 mV. This input configuration is useful in systems where the sensor and/or the signal
conditioning block is placed far from the device and there could be a small difference between the ground
potentials. In this channel configuration, remove channel 1 from AUTO sequence by setting the
AUTO_SEQ_CH1 bit to 0. Selecting channel 1 in AUTO sequence leads to an error condition and the device
sets an error flag in the SEQUENCE_STATUS register.

7.3.1.3 Single-Channel, Pseudo-Differential Configuration

See Figure 40 for a simplified block diagram showing a single-channel, pseudo-differential configuration. Set
CH0_CH1_IP_CFG bits = 10b to select this configuration. In this configuration, CS1samples the input signal
provided on the AINP/AIN0 pin whereas CS2samples input signal provided on the AINM/AIN1 pin. AINP/AIN0 pin
can accept input signals in the range 0 V to AVDD V and AINM/AIN1 pin can accept input signals in the range
(AVDD/2) - 100 mV to (AVDD/2) + 100 mV. This input configuration is useful to interface with sensors that
provide pseudo-differential signal with negative output as AVDD/2 like an electrochemical gas sensor. In this
channel configuration, remove channel 1 from AUTO sequence by setting the AUTO_SEQ_CH1 bit to 0.
Selecting channel 1 in AUTO sequence leads to an error condition and the device sets an error flag in
SEQUENCE_STATUS register.

7.3.2 OFFSET Calibration

The offset can be calibrated by setting the TRIG_OFFCAL bit in the OFFSET_CAL register. During offset
calibration, the sampling switches are open (Figure 37) and the device keeps BUSY/RDY pin high. The device
calculates its offset error and corrects for this error for subsequent conversions. The device calibrates the offset
on power up. To nullify the change in offset due to change in temperature or in AVDD voltage, it is recommended
to perform this calibration periodically.

7.3.3 Reference

The device uses the analog supply voltage (AVDD) as a reference for the analog-to-digital conversion process. It
is recommended to place a 220-nF, low-ESR ceramic decoupling capacitor between the AVDD pin and the GND
pin, close to the AVDD Pin. See Power Supply Recommendations section.

7.3.4 ADC Transfer Function

The ADC provides data in straight binary format. The ADC resolution can be computed by Equation 1:

1 LSB = V

REF

/ 2

N

where:

• V

• N = 12 for Autonomous Monitoring Modes and Manual Mode (1)

REF

= AVDD

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21

nCLK

frequencyOscillator

f

S

NFSC+1

PFSC

MC + 1

MC

ADC Code (Hex)

V

IN

NFSC

(V

REF

/2 ± 1 LSB)

1 LSB0(-V

REF

/2 + 1 LSB)

NFSC+1

PFSC

MC + 1

MC

ADC Code (Hex)

V

IN

NFSC

1 LSB

(V

REF

± 1 LSB)

(V

REF

/2 + 1 LSB)V

REF

/2

ADS7142-Q1

SBAS891A –NOVEMBER 2018–REVISED OCTOBER 2019

www.ti.com

Feature Description (continued)

Figure 41 and Figure 42 show the ideal transfer characteristics for single-ended input and pseudo-differential

input, respectively. Table 1 show the digital output codes for the transfer functions.

Figure 41. Ideal Transfer Characteristics for

Single-Ended Configurations

Figure 42. Ideal Transfer Characteristics for

Pseudo-Differential Configuration

Table 1. Transfer Characteristics

IDEAL

OUTPUT

INPUT VOLTAGE FOR SINGLE-ENDED INPUT

INPUT VOLTAGE FOR PSEUDO

DIFFERENTIAL INPUT

CODE DESCRIPTION

CODE

(Autonomous

Monitoring

Mode or

Manual Mode)

Negative full-scale

code

000

(V

REF

(V

/ 2) + 1 LSB to (V

REF

≤1 LSB ≤ (–V

1 LSB to 2 LSBs (–V

/ 2) to (V

≥ V

/ 2) + 1 LSB 0 LSB to 1 LSB MC Mid code 800

REF

/ 2) + 2 LSBs 1 LSB to 2 LSB MC + 1 — 801

REF

– 1 LSB ≥ V

REF

/ 2 + 1) to (–V

REF

/ 2 + 1) LSB NFSC

REF

/ 2 + 2) LSB NFSC + 1 — 001

REF

/ 2 – 1 LSB PFSC Positive full-scale code FFF

REF

7.3.5 Oscillator and Timing Control

The device uses one of the two internal oscillators (low power oscillator or high speed oscillator) for converting
the analog input voltage into a digital output code.

The steps for selecting the oscillator and setting the sampling speed are listed below:

1. Select the low power oscillator (OSC_SEL = 1b) to monitor slow moving signals (< 300 Hz) at extremely low

power consumption and sampling speeds (< 600 SPS). Select the high speed oscillator (OSC_SEL = 0b) to
scan the sensor signals with faster sampling speed (> 50 kHz).

2. Set sampling speed by programming the NCLK_SEL register:

22

• fs= Sampling speed

• Oscillator frequency = 1 / t
1 / t

HSO

or 1 / t

LPO

HSO

or 1 / t

depending on the OSC_SEL bit; see the Specifications section for

LPO

• nCLK is number of clocks in one conversion cycle (see the NCLK_SEL register) (2)

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R1

R2

AVDD

ADDR

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7.3.6 I2C Address Selector

The I2C address for the device is determined by connecting external resistors on ADDR pin. The device address
are selected on power-up based on the resistor values. The device retains this address until the next power up,
or until next device reset, or until the device receives a command to program its own address (General Call With

Write Software Programmable Part of Slave Address). Figure 43 provides the connection diagram for the ADDR

pin and Table 2 provides the resistor values for selecting different addresses of the device.

Figure 43. External Resistor Connection Diagram for ADDR Pin

Table 2. I2C Address Selection

(1)

R1

0 Ω DNP
11 kΩ DNP
33 kΩ DNP

100 kΩ DNP

(2)

DNP

(2)

DNP

(2)

DNP

(2)

DNP

(1) Tolerance for R1, R2 < ±5%.
(2) DNP = Do not populate.

RESISTORS

(1)

R2

(2)
(2)
(2)
(2)

0Ω or DNP

(2)

11 kΩ 0011001b (19h)
33 kΩ 0011010b (1Ah)

100 kΩ 0011011b (1Bh)

ADDRESS

0011111b (1Fh)
0011110b (1Eh)
0011101b (1Dh)
0011100b (1Ch)

0011000b (18h)

7.3.7 Data Buffer

When operating in autonomous monitoring mode, the device can use the internal data buffer for data storage.
The internal data buffer is 16-bit wide and 16-word deep and follows the first-in, first-out (FIFO) approach.

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Device Address (7 Bits) MSB for Data Buffer Entry 0 A LSB for Data Buffer Entry 0

LSB for Data Buffer Entry 15

R A A

P/Sr

Data from Host to Device

Data from Device to Host

S

N

MSB for Data Buffer Entry 1 A

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7.3.7.1 Filling of the Data Buffer

The write operation to the data buffer starts and stops as per the settings in the DATA_BUFFER_OPMODE
register. The DATA_BUFFER_STATUS register provides the number of entries filled in the data buffer and this
register can be read during an active sequence to get the current status of the data buffer.
The time between two consecutive conversions is set by the NCLK_SEL register and Equation 3 provides the
relationship for time between two consecutive conversions of the same channel and nCLK parameter.

tcc= k x nCLK x OscillatorTimePeriod

where

• tcc= Time between two consecutive conversions of same channel, tcc= k × t

• k = Number of channels enabled in the device sequence

• nCLK = Number of clocks used by device for one conversion cycle

• Oscillator timer period = t
or t

HSO

LPO

or t

depending on the OSC_SEL value; see the Specifications section for t

HSO

cycle

LPO

(3)

The format of the 16-bit contents of each entry in the data buffer are set by programming the
DOUT_FORMAT_CFG register. The DATA_OUT_CFG register enables the channel ID and DATA_VALID flag in
data buffer. Channel ID represents the channel number for the data entry in the data buffer. DATA_VALID is set
to zero in either of the following conditions:

• If the entry in the data buffer is not filled after the last start of sequence.

• If the I2C master tries to read more than 16 entries from the data buffer, the device provides zeros with
DATA_VALID set to zero

At the end of the write operation, the data buffer always has results of 16 (or lesser) consecutive conversions.
The data buffer is filled in the order that the data is converted by the ADC. The channels converted by the ADC
are controlled by the AUTO_SEQ_CHEN register. The entries that are not filled during an active sequence are
filled with zeros.

7.3.7.2 Reading Data From the Data Buffer

The device brings the BUSY/RDY pin low after completion of the sequence or after the SEQ_ABORT bit is set.
As illustrated in Figure 44, the device provides the contents of the data buffer (in FIFO fashion) on receiving I2C
read frame, which consists of the device address and the read bit set to 1.

Figure 44. Reading Data Buffer (16 Bit Words × 16 Words)

The device returns zeroes with DATA VALID flag set to zero for all I2C read frames received after all the valid
data words from the data buffer are read or when a I2C read frame is issued during an active sequence
(indicated by high on the BUSY/RDY pin). The I2C master needs to provide a NACK followed by a STOP or
RESTART condition in an I2C frame to finish the reading process. The data buffer is reset by setting the
SEQ_START bit or after resetting the device.

24

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